[people/ms/u-boot.git] / include / configs / MPC8260ADS.h

/*
 * (C) Copyright 2001
 * Stuart Hughes <stuarth@lineo.com>
 * This file is based on similar values for other boards found in other
 * U-Boot config files, and some that I found in the mpc8260ads manual.
 *
 * Note: my board is a PILOT rev.
 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
 *
 * (C) Copyright 2003 Arabella Software Ltd.
 * Yuli Barcohen <yuli@arabellasw.com>
 * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
 * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU   */
#define CONFIG_MPC8260ADS	1	/* ...on motorola ads board */

/* ADS flavours */
#define CFG_8260ADS		1	/* MPC8260ADS */
#define CFG_8266ADS		2	/* MPC8266ADS */
#define CFG_PQ2FADS		3	/* PQ2FADS-ZU or PQ2FADS-VR */

#ifndef CONFIG_ADSTYPE
#define CONFIG_ADSTYPE		CFG_8260ADS
#endif /* CONFIG_ADSTYPE */

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/

/* allow serial and ethaddr to be overwritten */
#define CONFIG_ENV_OVERWRITE

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef	CONFIG_CONS_NONE		/* define if console on something else */
#define CONFIG_CONS_INDEX	1	/* which serial channel for console */

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */

#ifdef CONFIG_ETHER_ON_FCC

#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */

#if (CONFIG_ETHER_INDEX == 2)
/*
 * - Rx-CLK is CLK13
 * - Tx-CLK is CLK14
 * - Select bus for bd/buffers (see 28-13)
 * - Full duplex
 */
# define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif	/* CONFIG_ETHER_INDEX */

#define CONFIG_MII			/* MII PHY management		*/
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	2		/* Port C */
#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
#define MDIO_READ	((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

#define MIIDELAY	udelay(1)

#endif /* CONFIG_ETHER_ON_FCC */

#if CONFIG_ADSTYPE == CFG_PQ2FADS
#undef CONFIG_SPD_EEPROM	/* On PQ2FADS-ZU, SDRAM is soldered  */
#else
#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
#define CFG_I2C_SPEED		100000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
#define CONFIG_SPD_ADDR         0x50
#endif
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */

#ifndef CONFIG_SDRAM_PBI
#define CONFIG_SDRAM_PBI        0 /* By default, use bank-based interleaving */
#endif

#ifndef CONFIG_8260_CLKIN
#if CONFIG_ADSTYPE == CFG_PQ2FADS
#define CONFIG_8260_CLKIN	100000000	/* in Hz */
#else
#define CONFIG_8260_CLKIN	66000000	/* in Hz */
#endif
#endif

#define CONFIG_BAUDRATE		115200

#define CFG_EXCLUDE		 CFG_CMD_BEDBUG | \
				 CFG_CMD_BMP	| \
				 CFG_CMD_BSP	| \
				 CFG_CMD_DATE	| \
				 CFG_CMD_DOC	| \
				 CFG_CMD_DTT	| \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_ELF    | \
				 CFG_CMD_FAT    | \
				 CFG_CMD_FDC	| \
				 CFG_CMD_FDOS	| \
				 CFG_CMD_HWFLOW	| \
				 CFG_CMD_IDE	| \
				 CFG_CMD_KGDB	| \
				 CFG_CMD_MMC	| \
				 CFG_CMD_NAND	| \
				 CFG_CMD_PCI	| \
				 CFG_CMD_PCMCIA | \
				 CFG_CMD_SCSI	| \
				 CFG_CMD_SPI	| \
				 CFG_CMD_USB	| \
				 CFG_CMD_VFD

#if CONFIG_ADSTYPE == CFG_PQ2FADS
#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
				 CFG_CMD_SDRAM	| \
				 CFG_CMD_I2C	| \
				 CFG_EXCLUDE	) )
#else
#define CONFIG_COMMANDS		(CFG_CMD_ALL & ~( \
				 CFG_EXCLUDE	) )
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
#endif

#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
#undef	CONFIG_WATCHDOG	/* disable platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE	256			/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16			/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CFG_FLASH_BASE		0xff800000
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
#define CFG_FLASH_SIZE		8
#define CFG_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
#define CFG_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */

#define CFG_JFFS2_FIRST_SECTOR  1
#define CFG_JFFS2_LAST_SECTOR   27
#define CFG_JFFS2_SORT_FRAGMENTS
#define CFG_JFFS_CUSTOM_PART

/* this is stuff came out of the Motorola docs */
#define CFG_DEFAULT_IMMR	0x0F010000

#define CFG_IMMR		0xF0000000
#define CFG_BCSR		0xF4500000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_LSDRAM_BASE		0xFD000000

#define RS232EN_1		0x02000002
#define RS232EN_2		0x01000001
#define FETHIEN1		0x08000008
#define FETH1_RST		0x04000004
#define FETHIEN2		0x01000000
#define FETH2_RST		0x08000000
#define BCSR_PCI_MODE		0x01000000

#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x4000	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/* 0x0EA28205 */
#define CFG_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
			    ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
			    ( HRCW_BMS | HRCW_APPC10 )			    |\
			    ( HRCW_MODCK_H0101 )			     \
			)

/* no slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
#define CFG_HRCW_SLAVE3 0
#define CFG_HRCW_SLAVE4 0
#define CFG_HRCW_SLAVE5 0
#define CFG_HRCW_SLAVE6 0
#define CFG_HRCW_SLAVE7 0

#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM	0x02	/* Software reboot	     */

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
#else
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
#endif /* CONFIG_BZIP2 */

#ifndef CFG_RAMBOOT
#  define CFG_ENV_IS_IN_FLASH	1
#  define CFG_ENV_SECT_SIZE	0x40000
#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
#else
#  define CFG_ENV_IS_IN_NVRAM	1
#  define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
#  define CFG_ENV_SIZE		0x200
#endif /* CFG_RAMBOOT */


#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif


#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )

#define CFG_HID2		0

#define CFG_SYPCR		0xFFFFFFC3
#define CFG_BCR			0x100C0000
#define CFG_SIUMCR		0x0A200000
#define CFG_SCCR		SCCR_DFBRG01
#define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00001801
#define CFG_OR0_PRELIM		0xFF800876
#define CFG_BR1_PRELIM		CFG_BCSR | 0x00001801
#define CFG_OR1_PRELIM		0xFFFF8010

#define CFG_RMR			RMR_CSRE
#define CFG_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR		0

#if CONFIG_ADSTYPE == CFG_8266ADS
#undef CFG_LSDRAM_BASE		/* No local bus SDRAM on MPC8266ADS */
#endif /* CONFIG_ADSTYPE == CFG_8266ADS */

#if CONFIG_ADSTYPE == CFG_PQ2FADS
#define CFG_OR2			0xFE002EC0
#define CFG_PSDMR		0x824B36A3
#define CFG_PSRT		0x13
#define CFG_LSDMR		0x828737A3
#define CFG_LSRT		0x13
#define CFG_MPTPR		0x2800
#else
#define CFG_OR2			0xFF000CA0
#define CFG_PSDMR		0x016EB452
#define CFG_PSRT		0x21
#define CFG_LSDMR		0x0086A522
#define CFG_LSRT		0x21
#define CFG_MPTPR		0x1900
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */

#define CFG_RESET_ADDRESS	0x04400000

#endif /* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2001
	3	* Stuart Hughes <stuarth@lineo.com>
	4	* This file is based on similar values for other boards found in other
	5	* U-Boot config files, and some that I found in the mpc8260ads manual.
	6	*
	7	* Note: my board is a PILOT rev.
	8	* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
	9	*
cceb871f WD	10	* (C) Copyright 2003 Arabella Software Ltd.
cceb871f WD	11	* Yuli Barcohen <yuli@arabellasw.com>
2535d602	12	* Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
ef5a9672	13	* Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
cceb871f	14	*
e2211743 WD	15	* See file CREDITS for list of people who contributed to this
	16	* project.
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License as
	20	* published by the Free Software Foundation; either version 2 of
	21	* the License, or (at your option) any later version.
	22	*
	23	* This program is distributed in the hope that it will be useful,
	24	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	25	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	26	* GNU General Public License for more details.
	27	*
	28	* You should have received a copy of the GNU General Public License
	29	* along with this program; if not, write to the Free Software
	30	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	31	* MA 02111-1307 USA
	32	*/
	33
e2211743 WD	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/*
	38	* High Level Configuration Options
	39	* (easy to change)
	40	*/
	41
	42	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	43	#define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */
	44
2535d602 WD	45	/* ADS flavours */
	46	#define CFG_8260ADS 1 /* MPC8260ADS */
	47	#define CFG_8266ADS 2 /* MPC8266ADS */
ef5a9672	48	#define CFG_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
2535d602 WD	49
	50	#ifndef CONFIG_ADSTYPE
	51	#define CONFIG_ADSTYPE CFG_8260ADS
	52	#endif /* CONFIG_ADSTYPE */
	53
c837dcb1	54	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
e2211743 WD	55
	56	/* allow serial and ethaddr to be overwritten */
	57	#define CONFIG_ENV_OVERWRITE
	58
	59	/*
	60	* select serial console configuration
	61	*
	62	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	63	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	64	* for SCC).
	65	*
	66	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	67	* defined elsewhere (for example, on the cogent platform, there are serial
	68	* ports on the motherboard which are used for the serial console - see
	69	* cogent/cma101/serial.[ch]).
	70	*/
	71	#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
	72	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	73	#undef CONFIG_CONS_NONE /* define if console on something else */
	74	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
	75
	76	/*
	77	* select ethernet configuration
	78	*
	79	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	80	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	81	* for FCC)
	82	*
	83	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
	84	* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
	85	* from CONFIG_COMMANDS to remove support for networking.
	86	*/
	87	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	88	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	89	#undef CONFIG_ETHER_NONE /* define if ether on something else */
e2211743	90
48b42616	91	#ifdef CONFIG_ETHER_ON_FCC
e2211743	92
48b42616 WD	93	#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
	94
	95	#if (CONFIG_ETHER_INDEX == 2)
e2211743 WD	96	/*
	97	* - Rx-CLK is CLK13
	98	* - Tx-CLK is CLK14
	99	* - Select bus for bd/buffers (see 28-13)
48b42616	100	* - Full duplex
e2211743 WD	101	*/
	102	# define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	103	# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	104	# define CFG_CPMFCR_RAMTYPE 0
48b42616	105	# define CFG_FCC_PSMR (FCC_PSMR_FDE \| FCC_PSMR_LPB)
e2211743 WD	106
	107	#endif /* CONFIG_ETHER_INDEX */
	108
48b42616 WD	109	#define CONFIG_MII /* MII PHY management */
	110	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
	111	/*
	112	* GPIO pins used for bit-banged MII communications
	113	*/
	114	#define MDIO_PORT 2 /* Port C */
	115	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	116	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	117	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	118
	119	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	120	else iop->pdat &= ~0x00400000
	121
	122	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	123	else iop->pdat &= ~0x00200000
	124
	125	#define MIIDELAY udelay(1)
	126
	127	#endif /* CONFIG_ETHER_ON_FCC */
	128
2535d602 WD	129	#if CONFIG_ADSTYPE == CFG_PQ2FADS
	130	#undef CONFIG_SPD_EEPROM /* On PQ2FADS-ZU, SDRAM is soldered */
	131	#else
e2211743	132	#define CONFIG_HARD_I2C 1 /* To enable I2C support */
ef5a9672	133	#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
e2211743 WD	134	#define CFG_I2C_SLAVE 0x7F
e2211743 WD	135
db2f721f WD	136	#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
	137	#define CONFIG_SPD_ADDR 0x50
	138	#endif
2535d602	139	#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
e2211743	140
db2f721f	141	#ifndef CONFIG_SDRAM_PBI
ef5a9672	142	#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
db2f721f WD	143	#endif
	144
	145	#ifndef CONFIG_8260_CLKIN
2535d602 WD	146	#if CONFIG_ADSTYPE == CFG_PQ2FADS
	147	#define CONFIG_8260_CLKIN 100000000 /* in Hz */
	148	#else
ef5a9672	149	#define CONFIG_8260_CLKIN 66000000 /* in Hz */
db2f721f	150	#endif
2535d602 WD	151	#endif
2535d602 WD	152
e2211743 WD	153	#define CONFIG_BAUDRATE 115200
e2211743 WD	154
2535d602	155	#define CFG_EXCLUDE CFG_CMD_BEDBUG \| \
824a1ebf	156	CFG_CMD_BMP \| \
e2211743 WD	157	CFG_CMD_BSP \| \
	158	CFG_CMD_DATE \| \
	159	CFG_CMD_DOC \| \
	160	CFG_CMD_DTT \| \
	161	CFG_CMD_EEPROM \| \
	162	CFG_CMD_ELF \| \
2535d602	163	CFG_CMD_FAT \| \
e2211743	164	CFG_CMD_FDC \| \
2262cfee	165	CFG_CMD_FDOS \| \
e2211743 WD	166	CFG_CMD_HWFLOW \| \
e2211743 WD	167	CFG_CMD_IDE \| \
e2211743	168	CFG_CMD_KGDB \| \
71f95118	169	CFG_CMD_MMC \| \
cceb871f	170	CFG_CMD_NAND \| \
e2211743 WD	171	CFG_CMD_PCI \| \
	172	CFG_CMD_PCMCIA \| \
	173	CFG_CMD_SCSI \| \
1d0350ed	174	CFG_CMD_SPI \| \
2535d602 WD	175	CFG_CMD_USB \| \
	176	CFG_CMD_VFD
	177
	178	#if CONFIG_ADSTYPE == CFG_PQ2FADS
	179	#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
	180	CFG_CMD_SDRAM \| \
	181	CFG_CMD_I2C \| \
	182	CFG_EXCLUDE ) )
	183	#else
	184	#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
	185	CFG_EXCLUDE ) )
	186	#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
e2211743 WD	187
	188	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	189	#include <cmd_confdefs.h>
	190
e2211743 WD	191	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	192	#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
	193	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	194
	195	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	196	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	197	#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	198	#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
	199	#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
	200	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
	201	#endif
	202
ef5a9672 WD	203	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
ef5a9672 WD	204	#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
e2211743 WD	205
	206	/*
	207	* Miscellaneous configurable options
	208	*/
326428cc WD	209	#define CFG_HUSH_PARSER
326428cc WD	210	#define CFG_PROMPT_HUSH_PS2 "> "
e2211743 WD	211	#define CFG_LONGHELP /* undef to save memory */
	212	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	213	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	214	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	215	#else
	216	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	217	#endif
	218	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	219	#define CFG_MAXARGS 16 /* max number of command args */
	220	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	221
	222	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	223	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	224
e2211743 WD	225	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	226
	227	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	228
	229	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	230
	231	#define CFG_FLASH_BASE 0xff800000
e2211743 WD	232	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
	233	#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
	234	#define CFG_FLASH_SIZE 8
	235	#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
	236	#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
8564acf9 WD	237	#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	238	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	239	#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	240
	241	#define CFG_JFFS2_FIRST_SECTOR 1
	242	#define CFG_JFFS2_LAST_SECTOR 27
	243	#define CFG_JFFS2_SORT_FRAGMENTS
	244	#define CFG_JFFS_CUSTOM_PART
e2211743 WD	245
	246	/* this is stuff came out of the Motorola docs */
	247	#define CFG_DEFAULT_IMMR 0x0F010000
	248
5d232d0e	249	#define CFG_IMMR 0xF0000000
2535d602	250	#define CFG_BCSR 0xF4500000
e2211743	251	#define CFG_SDRAM_BASE 0x00000000
326428cc	252	#define CFG_LSDRAM_BASE 0xFD000000
e2211743 WD	253
	254	#define RS232EN_1 0x02000002
	255	#define RS232EN_2 0x01000001
2535d602 WD	256	#define FETHIEN1 0x08000008
	257	#define FETH1_RST 0x04000004
	258	#define FETHIEN2 0x01000000
	259	#define FETH2_RST 0x08000000
326428cc	260	#define BCSR_PCI_MODE 0x01000000
e2211743 WD	261
	262	#define CFG_INIT_RAM_ADDR CFG_IMMR
	263	#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
	264	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	265	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	266	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	267
	268
	269	/* 0x0EA28205 */
	270	#define CFG_HRCW_MASTER ( ( HRCW_BPS11 \| HRCW_CIP ) \|\
	271	( HRCW_L2CPC10 \| HRCW_DPPC10 \| HRCW_ISB010 ) \|\
	272	( HRCW_BMS \| HRCW_APPC10 ) \|\
	273	( HRCW_MODCK_H0101 ) \
	274	)
	275
	276	/* no slaves */
	277	#define CFG_HRCW_SLAVE1 0
	278	#define CFG_HRCW_SLAVE2 0
	279	#define CFG_HRCW_SLAVE3 0
	280	#define CFG_HRCW_SLAVE4 0
	281	#define CFG_HRCW_SLAVE5 0
	282	#define CFG_HRCW_SLAVE6 0
	283	#define CFG_HRCW_SLAVE7 0
	284
	285	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	286	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	287
	288	#define CFG_MONITOR_BASE TEXT_BASE
	289	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	290	# define CFG_RAMBOOT
	291	#endif
	292
	293	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e2211743 WD	294	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	295
ef5a9672 WD	296	#ifdef CONFIG_BZIP2
	297	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
	298	#else
	299	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
	300	#endif /* CONFIG_BZIP2 */
	301
e2211743 WD	302	#ifndef CFG_RAMBOOT
e2211743 WD	303	# define CFG_ENV_IS_IN_FLASH 1
48b42616 WD	304	# define CFG_ENV_SECT_SIZE 0x40000
48b42616 WD	305	# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
e2211743 WD	306	#else
	307	# define CFG_ENV_IS_IN_NVRAM 1
	308	# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	309	# define CFG_ENV_SIZE 0x200
	310	#endif /* CFG_RAMBOOT */
	311
	312
	313	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
	314	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	315	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	316	#endif
	317
	318
	319	#define CFG_HID0_INIT 0
	320	#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE )
	321
	322	#define CFG_HID2 0
	323
	324	#define CFG_SYPCR 0xFFFFFFC3
	325	#define CFG_BCR 0x100C0000
	326	#define CFG_SIUMCR 0x0A200000
2535d602 WD	327	#define CFG_SCCR SCCR_DFBRG01
	328	#define CFG_BR0_PRELIM CFG_FLASH_BASE \| 0x00001801
	329	#define CFG_OR0_PRELIM 0xFF800876
	330	#define CFG_BR1_PRELIM CFG_BCSR \| 0x00001801
e2211743 WD	331	#define CFG_OR1_PRELIM 0xFFFF8010
e2211743 WD	332
2535d602	333	#define CFG_RMR RMR_CSRE
e2211743 WD	334	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	335	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	336	#define CFG_RCCR 0
2535d602	337
326428cc WD	338	#if CONFIG_ADSTYPE == CFG_8266ADS
	339	#undef CFG_LSDRAM_BASE /* No local bus SDRAM on MPC8266ADS */
	340	#endif /* CONFIG_ADSTYPE == CFG_8266ADS */
	341
2535d602	342	#if CONFIG_ADSTYPE == CFG_PQ2FADS
ef5a9672	343	#define CFG_OR2 0xFE002EC0
2535d602 WD	344	#define CFG_PSDMR 0x824B36A3
	345	#define CFG_PSRT 0x13
	346	#define CFG_LSDMR 0x828737A3
	347	#define CFG_LSRT 0x13
	348	#define CFG_MPTPR 0x2800
	349	#else
ef5a9672	350	#define CFG_OR2 0xFF000CA0
e2211743	351	#define CFG_PSDMR 0x016EB452
2535d602 WD	352	#define CFG_PSRT 0x21
	353	#define CFG_LSDMR 0x0086A522
	354	#define CFG_LSRT 0x21
	355	#define CFG_MPTPR 0x1900
	356	#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
e2211743 WD	357
	358	#define CFG_RESET_ADDRESS 0x04400000
	359
	360	#endif /* __CONFIG_H */