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5fb17030 IY |
1 | /* |
2 | * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. | |
3 | * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com | |
4 | * | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
5fb17030 IY |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
8afad91f | 16 | #define CONFIG_MPC830x 1 /* MPC830x family */ |
5fb17030 | 17 | #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ |
5fb17030 IY |
18 | |
19 | #define CONFIG_MISC_INIT_R | |
20 | ||
db1fc7d2 | 21 | #ifdef CONFIG_MMC |
db1fc7d2 | 22 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
db1fc7d2 | 23 | #define CONFIG_SYS_FSL_ESDHC_USE_PIO |
db1fc7d2 IS |
24 | #endif |
25 | ||
5fb17030 IY |
26 | /* |
27 | * On-board devices | |
28 | * | |
29 | * TSEC1 is SoC TSEC | |
30 | * TSEC2 is VSC switch | |
31 | */ | |
32 | #define CONFIG_TSEC1 | |
33 | #define CONFIG_VSC7385_ENET | |
34 | ||
35 | /* | |
36 | * System Clock Setup | |
37 | */ | |
38 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
39 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
40 | ||
41 | /* | |
42 | * Hardware Reset Configuration Word | |
43 | * if CLKIN is 66.66MHz, then | |
44 | * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz | |
45 | * We choose the A type silicon as default, so the core is 400Mhz. | |
46 | */ | |
47 | #define CONFIG_SYS_HRCW_LOW (\ | |
48 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
49 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
50 | HRCWL_SVCOD_DIV_2 |\ | |
51 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
52 | HRCWL_CORE_TO_CSB_3X1) | |
53 | /* | |
54 | * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits | |
55 | * in 8308's HRCWH according to the manual, but original Freescale's | |
56 | * code has them and I've expirienced some problems using the board | |
57 | * with BDI3000 attached when I've tried to set these bits to zero | |
58 | * (UART doesn't work after the 'reset run' command). | |
59 | */ | |
60 | #define CONFIG_SYS_HRCW_HIGH (\ | |
61 | HRCWH_PCI_HOST |\ | |
62 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
63 | HRCWH_CORE_ENABLE |\ | |
64 | HRCWH_FROM_0X00000100 |\ | |
65 | HRCWH_BOOTSEQ_DISABLE |\ | |
66 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
67 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
68 | HRCWH_RL_EXT_LEGACY |\ | |
69 | HRCWH_TSEC1M_IN_RGMII |\ | |
70 | HRCWH_TSEC2M_IN_RGMII |\ | |
71 | HRCWH_BIG_ENDIAN) | |
72 | ||
73 | /* | |
74 | * System IO Config | |
75 | */ | |
65ea7589 IY |
76 | #define CONFIG_SYS_SICRH (\ |
77 | SICRH_ESDHC_A_SD |\ | |
78 | SICRH_ESDHC_B_SD |\ | |
79 | SICRH_ESDHC_C_SD |\ | |
80 | SICRH_GPIO_A_TSEC2 |\ | |
81 | SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ | |
82 | SICRH_IEEE1588_A_GPIO |\ | |
83 | SICRH_USB |\ | |
84 | SICRH_GTM_GPIO |\ | |
85 | SICRH_IEEE1588_B_GPIO |\ | |
86 | SICRH_ETSEC2_CRS |\ | |
87 | SICRH_GPIOSEL_1 |\ | |
88 | SICRH_TMROBI_V3P3 |\ | |
89 | SICRH_TSOBI1_V2P5 |\ | |
90 | SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ | |
91 | #define CONFIG_SYS_SICRL (\ | |
92 | SICRL_SPI_PF0 |\ | |
93 | SICRL_UART_PF0 |\ | |
94 | SICRL_IRQ_PF0 |\ | |
95 | SICRL_I2C2_PF0 |\ | |
96 | SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ | |
5fb17030 IY |
97 | |
98 | /* | |
99 | * IMMR new address | |
100 | */ | |
101 | #define CONFIG_SYS_IMMR 0xE0000000 | |
102 | ||
103 | /* | |
104 | * SERDES | |
105 | */ | |
106 | #define CONFIG_FSL_SERDES | |
107 | #define CONFIG_FSL_SERDES1 0xe3000 | |
108 | ||
109 | /* | |
110 | * Arbiter Setup | |
111 | */ | |
112 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ | |
113 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ | |
114 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ | |
115 | ||
116 | /* | |
117 | * DDR Setup | |
118 | */ | |
119 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ | |
120 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
121 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
122 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
123 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | |
124 | | DDRCDR_PZ_LOZ \ | |
125 | | DDRCDR_NZ_LOZ \ | |
126 | | DDRCDR_ODT \ | |
127 | | DDRCDR_Q_DRN) | |
128 | /* 0x7b880001 */ | |
129 | /* | |
130 | * Manually set up DDR parameters | |
131 | * consist of two chips HY5PS12621BFP-C4 from HYNIX | |
132 | */ | |
133 | ||
134 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ | |
135 | ||
136 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 | |
137 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
2fef4020 JH |
138 | | CSCONFIG_ODT_RD_NEVER \ |
139 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
5fb17030 IY |
140 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
141 | /* 0x80010102 */ | |
142 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
143 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
144 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
145 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
146 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
147 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
148 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
149 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
150 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
151 | /* 0x00220802 */ | |
152 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ | |
153 | | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
154 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
155 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
156 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ | |
157 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
158 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
159 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
160 | /* 0x27256222 */ | |
161 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ | |
162 | | (4 << TIMING_CFG2_CPO_SHIFT) \ | |
163 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
164 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
165 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
166 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
167 | | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
168 | /* 0x121048c5 */ | |
169 | #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ | |
170 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
171 | /* 0x03600100 */ | |
172 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | |
173 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | |
2fef4020 | 174 | | SDRAM_CFG_DBW_32) |
5fb17030 IY |
175 | /* 0x43080000 */ |
176 | ||
177 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ | |
178 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ | |
179 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
180 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ | |
181 | #define CONFIG_SYS_DDR_MODE2 0x00000000 | |
182 | ||
183 | /* | |
184 | * Memory test | |
185 | */ | |
186 | #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ | |
187 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
188 | ||
189 | /* | |
190 | * The reserved memory | |
191 | */ | |
14d0a02a | 192 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5fb17030 | 193 | |
16c8c170 | 194 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
5fb17030 IY |
195 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
196 | ||
197 | /* | |
198 | * Initial RAM Base Address Setup | |
199 | */ | |
200 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
201 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
34f81968 | 202 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
5fb17030 | 203 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 204 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
5fb17030 IY |
205 | |
206 | /* | |
207 | * Local Bus Configuration & Clock Setup | |
208 | */ | |
209 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP | |
210 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
211 | #define CONFIG_SYS_LBC_LBCR 0x00040000 | |
212 | ||
213 | /* | |
214 | * FLASH on the Local Bus | |
215 | */ | |
216 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ | |
217 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
218 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
219 | ||
220 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
221 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ | |
222 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
223 | ||
224 | /* Window base at flash base */ | |
225 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
65ea7589 | 226 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
5fb17030 | 227 | |
7d6a0982 JH |
228 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
229 | | BR_PS_16 /* 16 bit port */ \ | |
230 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
231 | | BR_V) /* valid */ | |
232 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
5fb17030 IY |
233 | | OR_UPM_XAM \ |
234 | | OR_GPCM_CSNT \ | |
235 | | OR_GPCM_ACS_DIV2 \ | |
236 | | OR_GPCM_XACS \ | |
237 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
238 | | OR_GPCM_TRLX_SET \ |
239 | | OR_GPCM_EHTR_SET) | |
5fb17030 IY |
240 | |
241 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
242 | /* 127 64KB sectors and 8 8KB top sectors per device */ | |
243 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
244 | ||
245 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
246 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
247 | ||
248 | /* | |
249 | * NAND Flash on the Local Bus | |
250 | */ | |
34f81968 | 251 | #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ |
7d6a0982 | 252 | #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ |
34f81968 | 253 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 JH |
254 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
255 | | BR_PS_8 /* 8 bit Port */ \ | |
5fb17030 | 256 | | BR_MS_FCM /* MSEL = FCM */ \ |
34f81968 | 257 | | BR_V) /* valid */ |
7d6a0982 | 258 | #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ |
5fb17030 IY |
259 | | OR_FCM_CSCT \ |
260 | | OR_FCM_CST \ | |
261 | | OR_FCM_CHT \ | |
262 | | OR_FCM_SCY_1 \ | |
263 | | OR_FCM_TRLX \ | |
34f81968 | 264 | | OR_FCM_EHTR) |
5fb17030 IY |
265 | /* 0xFFFF8396 */ |
266 | ||
267 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE | |
65ea7589 | 268 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
5fb17030 IY |
269 | |
270 | #ifdef CONFIG_VSC7385_ENET | |
271 | #define CONFIG_TSEC2 | |
7d6a0982 | 272 | /* VSC7385 Base address on CS2 */ |
5fb17030 | 273 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
7d6a0982 JH |
274 | #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ |
275 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ | |
276 | | BR_PS_8 /* 8-bit port */ \ | |
277 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
278 | | BR_V) /* valid */ | |
279 | /* 0xF0000801 */ | |
280 | #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ | |
281 | | OR_GPCM_CSNT \ | |
282 | | OR_GPCM_XACS \ | |
283 | | OR_GPCM_SCY_15 \ | |
284 | | OR_GPCM_SETA \ | |
285 | | OR_GPCM_TRLX_SET \ | |
286 | | OR_GPCM_EHTR_SET) | |
287 | /* 0xFFFE09FF */ | |
5fb17030 IY |
288 | /* Access window base at VSC7385 base */ |
289 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
290 | /* Access window size 128K */ | |
65ea7589 | 291 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
5fb17030 IY |
292 | /* The flash address and size of the VSC7385 firmware image */ |
293 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
294 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
295 | #endif | |
296 | /* | |
297 | * Serial Port | |
298 | */ | |
5fb17030 IY |
299 | #define CONFIG_SYS_NS16550_SERIAL |
300 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
301 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
302 | ||
303 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
304 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
305 | ||
306 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) | |
307 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
308 | ||
5fb17030 | 309 | /* I2C */ |
00f792e0 HS |
310 | #define CONFIG_SYS_I2C |
311 | #define CONFIG_SYS_I2C_FSL | |
312 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
313 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
314 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
315 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
316 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
317 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
318 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
5fb17030 | 319 | |
ea1ea54e IS |
320 | /* |
321 | * SPI on header J8 | |
322 | * | |
323 | * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) | |
324 | * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. | |
325 | */ | |
326 | #ifdef CONFIG_MPC8XXX_SPI | |
ea1ea54e | 327 | #define CONFIG_USE_SPIFLASH |
ea1ea54e | 328 | #endif |
5fb17030 IY |
329 | |
330 | /* | |
331 | * Board info - revision and where boot from | |
332 | */ | |
333 | #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 | |
334 | ||
335 | /* | |
336 | * Config on-board RTC | |
337 | */ | |
338 | #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ | |
339 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
340 | ||
341 | /* | |
342 | * General PCI | |
343 | * Addresses are mapped 1-1. | |
344 | */ | |
345 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 | |
346 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 | |
347 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 | |
348 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
349 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 | |
350 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 | |
351 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
352 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 | |
353 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
354 | ||
65ea7589 IY |
355 | /* enable PCIE clock */ |
356 | #define CONFIG_SYS_SCCR_PCIEXP1CM 1 | |
5fb17030 | 357 | |
842033e6 | 358 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5fb17030 IY |
359 | #define CONFIG_PCIE |
360 | ||
5fb17030 IY |
361 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
362 | #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 | |
363 | ||
364 | /* | |
365 | * TSEC | |
366 | */ | |
5fb17030 IY |
367 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
368 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
369 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
370 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) | |
371 | ||
372 | /* | |
373 | * TSEC ethernet configuration | |
374 | */ | |
375 | #define CONFIG_MII 1 /* MII PHY management */ | |
376 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
377 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
378 | #define TSEC1_PHY_ADDR 2 | |
379 | #define TSEC2_PHY_ADDR 1 | |
380 | #define TSEC1_PHYIDX 0 | |
381 | #define TSEC2_PHYIDX 0 | |
382 | #define TSEC1_FLAGS TSEC_GIGABIT | |
383 | #define TSEC2_FLAGS TSEC_GIGABIT | |
384 | ||
385 | /* Options are: eTSEC[0-1] */ | |
386 | #define CONFIG_ETHPRIME "eTSEC0" | |
387 | ||
388 | /* | |
389 | * Environment | |
390 | */ | |
5fb17030 IY |
391 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ |
392 | CONFIG_SYS_MONITOR_LEN) | |
393 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ | |
394 | #define CONFIG_ENV_SIZE 0x2000 | |
395 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
396 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
397 | ||
398 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
399 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
400 | ||
401 | /* | |
402 | * BOOTP options | |
403 | */ | |
404 | #define CONFIG_BOOTP_BOOTFILESIZE | |
5fb17030 IY |
405 | |
406 | /* | |
407 | * Command line configuration. | |
408 | */ | |
5fb17030 | 409 | |
5fb17030 IY |
410 | /* |
411 | * Miscellaneous configurable options | |
412 | */ | |
5fb17030 | 413 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
5fb17030 IY |
414 | |
415 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
416 | ||
5fb17030 IY |
417 | /* Boot Argument Buffer Size */ |
418 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
5fb17030 IY |
419 | |
420 | /* | |
421 | * For booting Linux, the board info and command line data | |
9f530d59 | 422 | * have to be in the first 256 MB of memory, since this is |
5fb17030 IY |
423 | * the maximum mapped by the Linux kernel during initialization. |
424 | */ | |
9f530d59 | 425 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
63865278 | 426 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
5fb17030 IY |
427 | |
428 | /* | |
429 | * Core HID Setup | |
430 | */ | |
431 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
432 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
433 | HID0_ENABLE_INSTRUCTION_CACHE | \ | |
434 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) | |
435 | #define CONFIG_SYS_HID2 HID2_HBE | |
436 | ||
437 | /* | |
438 | * MMU Setup | |
439 | */ | |
440 | ||
441 | /* DDR: cache cacheable */ | |
72cd4087 | 442 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ |
5fb17030 IY |
443 | BATL_MEMCOHERENCE) |
444 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ | |
445 | BATU_VS | BATU_VP) | |
446 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
447 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
448 | ||
449 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
72cd4087 | 450 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ |
5fb17030 IY |
451 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
452 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ | |
453 | BATU_VP) | |
454 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
455 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
456 | ||
457 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
72cd4087 | 458 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
5fb17030 IY |
459 | BATL_MEMCOHERENCE) |
460 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ | |
461 | BATU_VS | BATU_VP) | |
72cd4087 | 462 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ |
5fb17030 IY |
463 | BATL_CACHEINHIBIT | \ |
464 | BATL_GUARDEDSTORAGE) | |
465 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
466 | ||
467 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 468 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
5fb17030 IY |
469 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ |
470 | BATU_VS | BATU_VP) | |
471 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
472 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
473 | ||
5fb17030 IY |
474 | /* |
475 | * Environment Configuration | |
476 | */ | |
477 | ||
478 | #define CONFIG_ENV_OVERWRITE | |
479 | ||
480 | #if defined(CONFIG_TSEC_ENET) | |
481 | #define CONFIG_HAS_ETH0 | |
482 | #define CONFIG_HAS_ETH1 | |
483 | #endif | |
484 | ||
5fb17030 IY |
485 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
486 | ||
5fb17030 | 487 | |
5fb17030 IY |
488 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
489 | "netdev=eth0\0" \ | |
490 | "consoledev=ttyS0\0" \ | |
491 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
492 | "nfsroot=${serverip}:${rootpath}\0" \ | |
493 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
494 | "addip=setenv bootargs ${bootargs} " \ | |
495 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
496 | ":${hostname}:${netdev}:off panic=1\0" \ | |
497 | "addtty=setenv bootargs ${bootargs}" \ | |
498 | " console=${consoledev},${baudrate}\0" \ | |
499 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ | |
500 | "addmisc=setenv bootargs ${bootargs}\0" \ | |
501 | "kernel_addr=FE080000\0" \ | |
502 | "fdt_addr=FE280000\0" \ | |
503 | "ramdisk_addr=FE290000\0" \ | |
504 | "u-boot=mpc8308rdb/u-boot.bin\0" \ | |
505 | "kernel_addr_r=1000000\0" \ | |
506 | "fdt_addr_r=C00000\0" \ | |
507 | "hostname=mpc8308rdb\0" \ | |
508 | "bootfile=mpc8308rdb/uImage\0" \ | |
509 | "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ | |
510 | "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ | |
511 | "flash_self=run ramargs addip addtty addmtd addmisc;" \ | |
512 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
513 | "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ | |
514 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
515 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
516 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
517 | "run nfsargs addip addtty addmtd addmisc;" \ | |
518 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
519 | "bootcmd=run flash_self\0" \ | |
520 | "load=tftp ${loadaddr} ${u-boot}\0" \ | |
93ea89f0 MV |
521 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ |
522 | " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ | |
5fb17030 | 523 | " +${filesize};cp.b ${fileaddr} " \ |
93ea89f0 | 524 | __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ |
5fb17030 IY |
525 | "upd=run load update\0" \ |
526 | ||
527 | #endif /* __CONFIG_H */ |