]>
Commit | Line | Data |
---|---|---|
8bd522ce DL |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __CONFIG_H | |
26 | #define __CONFIG_H | |
27 | ||
8bd522ce DL |
28 | /* |
29 | * High Level Configuration Options | |
30 | */ | |
31 | #define CONFIG_E300 1 /* E300 family */ | |
32 | #define CONFIG_MPC83XX 1 /* MPC83xx family */ | |
33 | #define CONFIG_MPC831X 1 /* MPC831x CPU family */ | |
34 | #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ | |
35 | #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ | |
36 | ||
37 | /* | |
38 | * System Clock Setup | |
39 | */ | |
40 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
41 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
42 | ||
43 | /* | |
44 | * Hardware Reset Configuration Word | |
45 | * if CLKIN is 66.66MHz, then | |
46 | * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz | |
47 | */ | |
48 | #define CFG_HRCW_LOW (\ | |
49 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
50 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
51 | HRCWL_SVCOD_DIV_2 |\ | |
52 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
53 | HRCWL_CORE_TO_CSB_3X1) | |
54 | #define CFG_HRCW_HIGH (\ | |
55 | HRCWH_PCI_HOST |\ | |
56 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
57 | HRCWH_CORE_ENABLE |\ | |
58 | HRCWH_FROM_0X00000100 |\ | |
59 | HRCWH_BOOTSEQ_DISABLE |\ | |
60 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
61 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
62 | HRCWH_RL_EXT_LEGACY |\ | |
63 | HRCWH_TSEC1M_IN_RGMII |\ | |
64 | HRCWH_TSEC2M_IN_RGMII |\ | |
65 | HRCWH_BIG_ENDIAN |\ | |
66 | HRCWH_LALE_NORMAL) | |
67 | ||
68 | /* | |
69 | * System IO Config | |
70 | */ | |
71 | #define CFG_SICRH 0x00000000 | |
72 | #define CFG_SICRL 0x00000000 /* 3.3V, no delay */ | |
73 | ||
74 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
75 | ||
76 | /* | |
77 | * IMMR new address | |
78 | */ | |
79 | #define CFG_IMMR 0xE0000000 | |
80 | ||
81 | /* | |
82 | * Arbiter Setup | |
83 | */ | |
84 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ | |
85 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ | |
86 | #define CFG_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ | |
87 | ||
88 | /* | |
89 | * DDR Setup | |
90 | */ | |
91 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ | |
92 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
93 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
94 | #define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
95 | #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ | |
96 | | DDRCDR_PZ_LOZ \ | |
97 | | DDRCDR_NZ_LOZ \ | |
98 | | DDRCDR_ODT \ | |
99 | | DDRCDR_Q_DRN ) | |
100 | /* 0x7b880001 */ | |
101 | /* | |
102 | * Manually set up DDR parameters | |
103 | * consist of two chips HY5PS12621BFP-C4 from HYNIX | |
104 | */ | |
105 | #define CFG_DDR_SIZE 128 /* MB */ | |
106 | #define CFG_DDR_CS0_BNDS 0x00000007 | |
107 | #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ | |
108 | | 0x00010000 /* ODT_WR to CSn */ \ | |
109 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) | |
110 | /* 0x80010102 */ | |
111 | #define CFG_DDR_TIMING_3 0x00000000 | |
112 | #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
113 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | |
114 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
115 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
116 | | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
117 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
118 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
119 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
120 | /* 0x00220802 */ | |
121 | #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
122 | | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | |
123 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
124 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
125 | | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ | |
126 | | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ | |
127 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
128 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
129 | /* 0x39356222 */ | |
130 | #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | |
131 | | ( 4 << TIMING_CFG2_CPO_SHIFT ) \ | |
132 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | |
133 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
134 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
135 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
136 | | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | |
137 | /* 0x121048c7 */ | |
138 | #define CFG_DDR_INTERVAL ( ( 0x0360 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | |
139 | | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | |
140 | /* 0x03600100 */ | |
141 | #define CFG_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
142 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | |
143 | | SDRAM_CFG_32_BE ) | |
144 | /* 0x43080000 */ | |
145 | #define CFG_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ | |
146 | #define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ | |
147 | | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) | |
148 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ | |
149 | #define CFG_DDR_MODE2 0x00000000 | |
150 | ||
151 | /* | |
152 | * Memory test | |
153 | */ | |
154 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
155 | #define CFG_MEMTEST_START 0x00040000 /* memtest region */ | |
156 | #define CFG_MEMTEST_END 0x00140000 | |
157 | ||
158 | /* | |
159 | * The reserved memory | |
160 | */ | |
161 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
162 | ||
163 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
164 | #define CFG_RAMBOOT | |
165 | #else | |
166 | #undef CFG_RAMBOOT | |
167 | #endif | |
168 | ||
169 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
170 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
171 | ||
172 | /* | |
173 | * Initial RAM Base Address Setup | |
174 | */ | |
175 | #define CFG_INIT_RAM_LOCK 1 | |
176 | #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
177 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
178 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
179 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
180 | ||
181 | /* | |
182 | * Local Bus Configuration & Clock Setup | |
183 | */ | |
184 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) | |
185 | #define CFG_LBC_LBCR 0x00040000 | |
186 | ||
187 | /* | |
188 | * FLASH on the Local Bus | |
189 | */ | |
190 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
00b1883a | 191 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
8bd522ce DL |
192 | #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
193 | ||
194 | #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
195 | #define CFG_FLASH_SIZE 8 /* FLASH size is 8M */ | |
196 | ||
197 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ | |
198 | #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ | |
199 | ||
200 | #define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \ | |
201 | | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | |
202 | | BR_V ) /* valid */ | |
203 | #define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \ | |
204 | | OR_UPM_XAM \ | |
205 | | OR_GPCM_CSNT \ | |
f9023afb | 206 | | OR_GPCM_ACS_DIV2 \ |
8bd522ce DL |
207 | | OR_GPCM_XACS \ |
208 | | OR_GPCM_SCY_15 \ | |
209 | | OR_GPCM_TRLX \ | |
210 | | OR_GPCM_EHTR \ | |
211 | | OR_GPCM_EAD ) | |
212 | ||
213 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
214 | #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors and 8 8KB top sectors per device */ | |
215 | ||
216 | #undef CFG_FLASH_CHECKSUM | |
217 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
218 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
219 | ||
220 | /* | |
221 | * NAND Flash on the Local Bus | |
222 | */ | |
223 | #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ | |
224 | #define CFG_MAX_NAND_DEVICE 1 | |
225 | #define NAND_MAX_CHIPS 1 | |
226 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
227 | ||
228 | #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ | |
229 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
230 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
231 | | BR_MS_FCM /* MSEL = FCM */ \ | |
232 | | BR_V ) /* valid */ | |
233 | #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
234 | | OR_FCM_CSCT \ | |
235 | | OR_FCM_CST \ | |
236 | | OR_FCM_CHT \ | |
237 | | OR_FCM_SCY_1 \ | |
238 | | OR_FCM_TRLX \ | |
239 | | OR_FCM_EHTR ) | |
240 | /* 0xFFFF8396 */ | |
241 | ||
242 | #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE | |
243 | #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ | |
244 | ||
245 | /* | |
246 | * Serial Port | |
247 | */ | |
248 | #define CONFIG_CONS_INDEX 1 | |
249 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
250 | #define CFG_NS16550 | |
251 | #define CFG_NS16550_SERIAL | |
252 | #define CFG_NS16550_REG_SIZE 1 | |
253 | #define CFG_NS16550_CLK get_bus_freq(0) | |
254 | ||
255 | #define CFG_BAUDRATE_TABLE \ | |
256 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
257 | ||
258 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) | |
259 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
260 | ||
261 | /* Use the HUSH parser */ | |
262 | #define CFG_HUSH_PARSER | |
263 | #ifdef CFG_HUSH_PARSER | |
264 | #define CFG_PROMPT_HUSH_PS2 "> " | |
265 | #endif | |
266 | ||
267 | /* Pass open firmware flat tree */ | |
268 | #define CONFIG_OF_LIBFDT 1 | |
269 | #define CONFIG_OF_BOARD_SETUP 1 | |
270 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
271 | ||
272 | /* I2C */ | |
273 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
274 | #define CONFIG_FSL_I2C | |
275 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
276 | #define CFG_I2C_SLAVE 0x7F | |
277 | #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
278 | #define CFG_I2C_OFFSET 0x3000 | |
279 | #define CFG_I2C2_OFFSET 0x3100 | |
280 | ||
281 | /* | |
282 | * Board info - revision and where boot from | |
283 | */ | |
284 | #define CFG_I2C_PCF8574A_ADDR 0x39 | |
285 | ||
286 | /* | |
287 | * Config on-board RTC | |
288 | */ | |
289 | #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ | |
290 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
291 | ||
292 | /* | |
293 | * General PCI | |
294 | * Addresses are mapped 1-1. | |
295 | */ | |
296 | #define CFG_PCI_MEM_BASE 0x80000000 | |
297 | #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE | |
298 | #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
299 | #define CFG_PCI_MMIO_BASE 0x90000000 | |
300 | #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE | |
301 | #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
a7ba32d4 | 302 | #define CFG_PCI_IO_BASE 0x00000000 |
8bd522ce DL |
303 | #define CFG_PCI_IO_PHYS 0xE0300000 |
304 | #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ | |
305 | ||
306 | #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE | |
307 | #define CFG_PCI_SLV_MEM_BUS 0x00000000 | |
308 | #define CFG_PCI_SLV_MEM_SIZE 0x80000000 | |
309 | ||
310 | #define CONFIG_PCI | |
311 | #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ | |
312 | ||
313 | #define CONFIG_NET_MULTI | |
314 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
315 | ||
316 | #define CONFIG_EEPRO100 | |
317 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
318 | #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
319 | ||
320 | #ifndef CONFIG_NET_MULTI | |
321 | #define CONFIG_NET_MULTI 1 | |
322 | #endif | |
323 | ||
25f5f0d4 AV |
324 | #define CONFIG_HAS_FSL_DR_USB |
325 | ||
8bd522ce DL |
326 | /* |
327 | * TSEC | |
328 | */ | |
329 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
330 | #define CFG_TSEC1_OFFSET 0x24000 | |
331 | #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) | |
332 | #define CFG_TSEC2_OFFSET 0x25000 | |
333 | #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) | |
334 | ||
335 | /* | |
336 | * TSEC ethernet configuration | |
337 | */ | |
338 | #define CONFIG_MII 1 /* MII PHY management */ | |
339 | #define CONFIG_TSEC1 1 | |
340 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
341 | #define CONFIG_TSEC2 1 | |
342 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
343 | #define TSEC1_PHY_ADDR 0 | |
344 | #define TSEC2_PHY_ADDR 1 | |
345 | #define TSEC1_PHYIDX 0 | |
346 | #define TSEC2_PHYIDX 0 | |
347 | #define TSEC1_FLAGS TSEC_GIGABIT | |
348 | #define TSEC2_FLAGS TSEC_GIGABIT | |
349 | ||
350 | /* Options are: eTSEC[0-1] */ | |
351 | #define CONFIG_ETHPRIME "eTSEC1" | |
352 | ||
730e7929 KP |
353 | /* |
354 | * SATA | |
355 | */ | |
356 | #define CONFIG_LIBATA | |
357 | #define CONFIG_FSL_SATA | |
358 | ||
359 | #define CFG_SATA_MAX_DEVICE 2 | |
360 | #define CONFIG_SATA1 | |
361 | #define CFG_SATA1_OFFSET 0x18000 | |
362 | #define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET) | |
363 | #define CFG_SATA1_FLAGS FLAGS_DMA | |
364 | #define CONFIG_SATA2 | |
365 | #define CFG_SATA2_OFFSET 0x19000 | |
366 | #define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET) | |
367 | #define CFG_SATA2_FLAGS FLAGS_DMA | |
368 | ||
369 | #ifdef CONFIG_FSL_SATA | |
370 | #define CONFIG_LBA48 | |
371 | #define CONFIG_CMD_SATA | |
372 | #define CONFIG_DOS_PARTITION | |
373 | #define CONFIG_CMD_EXT2 | |
374 | #endif | |
375 | ||
8bd522ce DL |
376 | /* |
377 | * Environment | |
378 | */ | |
379 | #ifndef CFG_RAMBOOT | |
380 | #define CFG_ENV_IS_IN_FLASH 1 | |
381 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) | |
382 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ | |
383 | #define CFG_ENV_SIZE 0x2000 | |
384 | #else | |
385 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
386 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
387 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
388 | #define CFG_ENV_SIZE 0x2000 | |
389 | #endif | |
390 | ||
391 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
392 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
393 | ||
394 | /* | |
395 | * BOOTP options | |
396 | */ | |
397 | #define CONFIG_BOOTP_BOOTFILESIZE | |
398 | #define CONFIG_BOOTP_BOOTPATH | |
399 | #define CONFIG_BOOTP_GATEWAY | |
400 | #define CONFIG_BOOTP_HOSTNAME | |
401 | ||
402 | /* | |
403 | * Command line configuration. | |
404 | */ | |
405 | #include <config_cmd_default.h> | |
406 | ||
407 | #define CONFIG_CMD_PING | |
408 | #define CONFIG_CMD_I2C | |
409 | #define CONFIG_CMD_MII | |
410 | #define CONFIG_CMD_DATE | |
411 | #define CONFIG_CMD_PCI | |
412 | ||
413 | #if defined(CFG_RAMBOOT) | |
414 | #undef CONFIG_CMD_ENV | |
415 | #undef CONFIG_CMD_LOADS | |
416 | #endif | |
417 | ||
418 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
419 | ||
420 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
421 | ||
422 | /* | |
423 | * Miscellaneous configurable options | |
424 | */ | |
425 | #define CFG_LONGHELP /* undef to save memory */ | |
426 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
427 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
428 | ||
429 | #if defined(CONFIG_CMD_KGDB) | |
430 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
431 | #else | |
432 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
433 | #endif | |
434 | ||
435 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
436 | #define CFG_MAXARGS 16 /* max number of command args */ | |
437 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
438 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
439 | ||
440 | /* | |
441 | * For booting Linux, the board info and command line data | |
442 | * have to be in the first 8 MB of memory, since this is | |
443 | * the maximum mapped by the Linux kernel during initialization. | |
444 | */ | |
445 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
446 | ||
447 | /* | |
448 | * Core HID Setup | |
449 | */ | |
450 | #define CFG_HID0_INIT 0x000000000 | |
451 | #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
452 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) | |
453 | #define CFG_HID2 HID2_HBE | |
454 | ||
455 | /* | |
456 | * MMU Setup | |
457 | */ | |
31d82672 | 458 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
8bd522ce DL |
459 | |
460 | /* DDR: cache cacheable */ | |
461 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
462 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) | |
463 | #define CFG_DBAT0L CFG_IBAT0L | |
464 | #define CFG_DBAT0U CFG_IBAT0U | |
465 | ||
466 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
467 | #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ | |
468 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
469 | #define CFG_IBAT1U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) | |
470 | #define CFG_DBAT1L CFG_IBAT1L | |
471 | #define CFG_DBAT1U CFG_IBAT1U | |
472 | ||
473 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
474 | #define CFG_IBAT2L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
475 | #define CFG_IBAT2U (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) | |
476 | #define CFG_DBAT2L (CFG_FLASH_BASE | BATL_PP_10 | \ | |
477 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
478 | #define CFG_DBAT2U CFG_IBAT2U | |
479 | ||
480 | /* Stack in dcache: cacheable, no memory coherence */ | |
481 | #define CFG_IBAT3L (CFG_INIT_RAM_ADDR | BATL_PP_10) | |
482 | #define CFG_IBAT3U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
483 | #define CFG_DBAT3L CFG_IBAT3L | |
484 | #define CFG_DBAT3U CFG_IBAT3U | |
485 | ||
486 | /* PCI MEM space: cacheable */ | |
487 | #define CFG_IBAT4L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) | |
488 | #define CFG_IBAT4U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
489 | #define CFG_DBAT4L CFG_IBAT4L | |
490 | #define CFG_DBAT4U CFG_IBAT4U | |
491 | ||
492 | /* PCI MMIO space: cache-inhibit and guarded */ | |
493 | #define CFG_IBAT5L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ | |
494 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
495 | #define CFG_IBAT5U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
496 | #define CFG_DBAT5L CFG_IBAT5L | |
497 | #define CFG_DBAT5U CFG_IBAT5U | |
498 | ||
499 | #define CFG_IBAT6L 0 | |
500 | #define CFG_IBAT6U 0 | |
501 | #define CFG_DBAT6L CFG_IBAT6L | |
502 | #define CFG_DBAT6U CFG_IBAT6U | |
503 | ||
504 | #define CFG_IBAT7L 0 | |
505 | #define CFG_IBAT7U 0 | |
506 | #define CFG_DBAT7L CFG_IBAT7L | |
507 | #define CFG_DBAT7U CFG_IBAT7U | |
508 | ||
509 | /* | |
510 | * Internal Definitions | |
511 | * | |
512 | * Boot Flags | |
513 | */ | |
514 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
515 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
516 | ||
517 | #if defined(CONFIG_CMD_KGDB) | |
518 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
519 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
520 | #endif | |
521 | ||
522 | /* | |
523 | * Environment Configuration | |
524 | */ | |
525 | ||
526 | #define CONFIG_ENV_OVERWRITE | |
527 | ||
528 | #if defined(CONFIG_TSEC_ENET) | |
529 | #define CONFIG_HAS_ETH0 | |
530 | #define CONFIG_ETHADDR 04:00:00:00:00:0A | |
531 | #define CONFIG_HAS_ETH1 | |
532 | #define CONFIG_ETH1ADDR 04:00:00:00:00:0B | |
533 | #endif | |
534 | ||
535 | #define CONFIG_BAUDRATE 115200 | |
536 | ||
b2115757 | 537 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
8bd522ce DL |
538 | |
539 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
540 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
541 | ||
542 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
543 | "netdev=eth0\0" \ | |
544 | "consoledev=ttyS0\0" \ | |
545 | "ramdiskaddr=1000000\0" \ | |
546 | "ramdiskfile=ramfs.83xx\0" \ | |
547 | "fdtaddr=400000\0" \ | |
548 | "fdtfile=mpc8315erdb.dtb\0" \ | |
549 | "" | |
550 | ||
551 | #define CONFIG_NFSBOOTCOMMAND \ | |
552 | "setenv bootargs root=/dev/nfs rw " \ | |
553 | "nfsroot=$serverip:$rootpath " \ | |
554 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
555 | "console=$consoledev,$baudrate $othbootargs;" \ | |
556 | "tftp $loadaddr $bootfile;" \ | |
557 | "tftp $fdtaddr $fdtfile;" \ | |
558 | "bootm $loadaddr - $fdtaddr" | |
559 | ||
560 | #define CONFIG_RAMBOOTCOMMAND \ | |
561 | "setenv bootargs root=/dev/ram rw " \ | |
562 | "console=$consoledev,$baudrate $othbootargs;" \ | |
563 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
564 | "tftp $loadaddr $bootfile;" \ | |
565 | "tftp $fdtaddr $fdtfile;" \ | |
566 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
567 | ||
568 | ||
569 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
570 | ||
571 | #endif /* __CONFIG_H */ |