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Commit | Line | Data |
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8bd522ce | 1 | /* |
e8d3ca8b | 2 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. |
8bd522ce DL |
3 | * |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
8bd522ce DL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
fdfaa29e KP |
12 | #define CONFIG_DISPLAY_BOARDINFO |
13 | ||
f1c574d4 SW |
14 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) |
15 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
16 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
17 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
18 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
19 | ||
2ae18241 WD |
20 | #ifndef CONFIG_SYS_TEXT_BASE |
21 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
2e95004d AV |
22 | #endif |
23 | ||
f1c574d4 SW |
24 | #ifndef CONFIG_SYS_MONITOR_BASE |
25 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
26 | #endif | |
27 | ||
8bd522ce DL |
28 | /* |
29 | * High Level Configuration Options | |
30 | */ | |
31 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 32 | #define CONFIG_MPC831x 1 /* MPC831x CPU family */ |
8bd522ce DL |
33 | #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ |
34 | #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ | |
35 | ||
36 | /* | |
37 | * System Clock Setup | |
38 | */ | |
39 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
40 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
41 | ||
42 | /* | |
43 | * Hardware Reset Configuration Word | |
44 | * if CLKIN is 66.66MHz, then | |
45 | * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz | |
46 | */ | |
6d0f6bcf | 47 | #define CONFIG_SYS_HRCW_LOW (\ |
8bd522ce DL |
48 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
49 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
50 | HRCWL_SVCOD_DIV_2 |\ | |
51 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
52 | HRCWL_CORE_TO_CSB_3X1) | |
2e95004d | 53 | #define CONFIG_SYS_HRCW_HIGH_BASE (\ |
8bd522ce DL |
54 | HRCWH_PCI_HOST |\ |
55 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
56 | HRCWH_CORE_ENABLE |\ | |
8bd522ce DL |
57 | HRCWH_BOOTSEQ_DISABLE |\ |
58 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
8bd522ce DL |
59 | HRCWH_TSEC1M_IN_RGMII |\ |
60 | HRCWH_TSEC2M_IN_RGMII |\ | |
61 | HRCWH_BIG_ENDIAN |\ | |
62 | HRCWH_LALE_NORMAL) | |
63 | ||
2e95004d AV |
64 | #ifdef CONFIG_NAND_SPL |
65 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ | |
66 | HRCWH_FROM_0XFFF00100 |\ | |
67 | HRCWH_ROM_LOC_NAND_SP_8BIT |\ | |
68 | HRCWH_RL_EXT_NAND) | |
69 | #else | |
70 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ | |
71 | HRCWH_FROM_0X00000100 |\ | |
72 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
73 | HRCWH_RL_EXT_LEGACY) | |
74 | #endif | |
75 | ||
8bd522ce DL |
76 | /* |
77 | * System IO Config | |
78 | */ | |
6d0f6bcf JCPV |
79 | #define CONFIG_SYS_SICRH 0x00000000 |
80 | #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ | |
8bd522ce DL |
81 | |
82 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
b8b71ffb | 83 | #define CONFIG_HWCONFIG |
8bd522ce DL |
84 | |
85 | /* | |
86 | * IMMR new address | |
87 | */ | |
6d0f6bcf | 88 | #define CONFIG_SYS_IMMR 0xE0000000 |
8bd522ce DL |
89 | |
90 | /* | |
91 | * Arbiter Setup | |
92 | */ | |
6d0f6bcf | 93 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
6f681b73 JH |
94 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
95 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ | |
8bd522ce DL |
96 | |
97 | /* | |
98 | * DDR Setup | |
99 | */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
101 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
102 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
103 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
6f681b73 | 104 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
8bd522ce DL |
105 | | DDRCDR_PZ_LOZ \ |
106 | | DDRCDR_NZ_LOZ \ | |
107 | | DDRCDR_ODT \ | |
6f681b73 | 108 | | DDRCDR_Q_DRN) |
8bd522ce DL |
109 | /* 0x7b880001 */ |
110 | /* | |
111 | * Manually set up DDR parameters | |
112 | * consist of two chips HY5PS12621BFP-C4 from HYNIX | |
113 | */ | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
115 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 | |
6f681b73 | 116 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
117 | | CSCONFIG_ODT_RD_NEVER \ |
118 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
6f681b73 JH |
119 | | CSCONFIG_ROW_BIT_13 \ |
120 | | CSCONFIG_COL_BIT_10) | |
8bd522ce | 121 | /* 0x80010102 */ |
6d0f6bcf | 122 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
6f681b73 JH |
123 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
124 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
125 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
126 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
127 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
128 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
129 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
130 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
8bd522ce | 131 | /* 0x00220802 */ |
6f681b73 JH |
132 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
133 | | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
134 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
135 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
136 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ | |
137 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
138 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
139 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
2f2a5c37 | 140 | /* 0x27256222 */ |
6f681b73 JH |
141 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
142 | | (4 << TIMING_CFG2_CPO_SHIFT) \ | |
143 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
144 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
145 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
146 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
147 | | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
2f2a5c37 | 148 | /* 0x121048c5 */ |
6f681b73 JH |
149 | #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
150 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
8bd522ce | 151 | /* 0x03600100 */ |
6f681b73 | 152 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
8bd522ce | 153 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 | 154 | | SDRAM_CFG_DBW_32) |
8bd522ce | 155 | /* 0x43080000 */ |
6d0f6bcf | 156 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
6f681b73 JH |
157 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
158 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
8bd522ce | 159 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
6f681b73 | 160 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
8bd522ce DL |
161 | |
162 | /* | |
163 | * Memory test | |
164 | */ | |
6d0f6bcf JCPV |
165 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
166 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
167 | #define CONFIG_SYS_MEMTEST_END 0x00140000 | |
8bd522ce DL |
168 | |
169 | /* | |
170 | * The reserved memory | |
171 | */ | |
6f681b73 JH |
172 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
173 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
8bd522ce DL |
174 | |
175 | /* | |
176 | * Initial RAM Base Address Setup | |
177 | */ | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
179 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 180 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
6f681b73 JH |
181 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
182 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
8bd522ce DL |
183 | |
184 | /* | |
185 | * Local Bus Configuration & Clock Setup | |
186 | */ | |
c7190f02 KP |
187 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
188 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
6d0f6bcf | 189 | #define CONFIG_SYS_LBC_LBCR 0x00040000 |
0914f483 | 190 | #define CONFIG_FSL_ELBC 1 |
8bd522ce DL |
191 | |
192 | /* | |
193 | * FLASH on the Local Bus | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 196 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf | 197 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
8bd522ce | 198 | |
6d0f6bcf | 199 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
6f681b73 JH |
200 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ |
201 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
8bd522ce | 202 | |
6f681b73 JH |
203 | /* Window base at flash base */ |
204 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 205 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
8bd522ce | 206 | |
2e95004d | 207 | #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
208 | | BR_PS_16 /* 16 bit port */ \ |
209 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
210 | | BR_V) /* valid */ | |
211 | #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
212 | | OR_UPM_XAM \ | |
213 | | OR_GPCM_CSNT \ | |
214 | | OR_GPCM_ACS_DIV2 \ | |
215 | | OR_GPCM_XACS \ | |
216 | | OR_GPCM_SCY_15 \ | |
217 | | OR_GPCM_TRLX_SET \ | |
218 | | OR_GPCM_EHTR_SET \ | |
219 | | OR_GPCM_EAD) | |
8bd522ce | 220 | |
6d0f6bcf | 221 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
6f681b73 JH |
222 | /* 127 64KB sectors and 8 8KB top sectors per device */ |
223 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
8bd522ce | 224 | |
6d0f6bcf JCPV |
225 | #undef CONFIG_SYS_FLASH_CHECKSUM |
226 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
227 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
8bd522ce DL |
228 | |
229 | /* | |
230 | * NAND Flash on the Local Bus | |
231 | */ | |
2e95004d AV |
232 | |
233 | #ifdef CONFIG_NAND_SPL | |
234 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
235 | #else | |
236 | #define CONFIG_SYS_NAND_BASE 0xE0600000 | |
237 | #endif | |
238 | ||
e8d3ca8b SW |
239 | #define CONFIG_MTD_DEVICE |
240 | #define CONFIG_MTD_PARTITION | |
241 | #define CONFIG_CMD_MTDPARTS | |
242 | #define MTDIDS_DEFAULT "nand0=e0600000.flash" | |
6f681b73 | 243 | #define MTDPARTS_DEFAULT \ |
e8d3ca8b SW |
244 | "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" |
245 | ||
6d0f6bcf | 246 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
1ac5744e DL |
247 | #define CONFIG_CMD_NAND 1 |
248 | #define CONFIG_NAND_FSL_ELBC 1 | |
7d6a0982 JH |
249 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 |
250 | #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ | |
2e95004d AV |
251 | |
252 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) | |
253 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
254 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
255 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
256 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
8bd522ce | 257 | |
2e95004d | 258 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 259 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
6f681b73 | 260 | | BR_PS_8 /* 8 bit port */ \ |
8bd522ce | 261 | | BR_MS_FCM /* MSEL = FCM */ \ |
6f681b73 | 262 | | BR_V) /* valid */ |
7d6a0982 JH |
263 | #define CONFIG_SYS_NAND_OR_PRELIM \ |
264 | (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | |
8bd522ce DL |
265 | | OR_FCM_CSCT \ |
266 | | OR_FCM_CST \ | |
267 | | OR_FCM_CHT \ | |
268 | | OR_FCM_SCY_1 \ | |
269 | | OR_FCM_TRLX \ | |
6f681b73 | 270 | | OR_FCM_EHTR) |
8bd522ce DL |
271 | /* 0xFFFF8396 */ |
272 | ||
2e95004d AV |
273 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM |
274 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
275 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
276 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
2e95004d | 277 | |
6d0f6bcf | 278 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 279 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
8bd522ce | 280 | |
2e95004d AV |
281 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM |
282 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
283 | ||
284 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ | |
285 | !defined(CONFIG_NAND_SPL) | |
286 | #define CONFIG_SYS_RAMBOOT | |
287 | #else | |
288 | #undef CONFIG_SYS_RAMBOOT | |
289 | #endif | |
290 | ||
8bd522ce DL |
291 | /* |
292 | * Serial Port | |
293 | */ | |
294 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_NS16550_SERIAL |
296 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
2e95004d | 297 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) |
8bd522ce | 298 | |
6d0f6bcf | 299 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
6f681b73 | 300 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
8bd522ce | 301 | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
303 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
8bd522ce DL |
304 | |
305 | /* Use the HUSH parser */ | |
6d0f6bcf | 306 | #define CONFIG_SYS_HUSH_PARSER |
8bd522ce DL |
307 | |
308 | /* Pass open firmware flat tree */ | |
8bd522ce DL |
309 | #define CONFIG_OF_BOARD_SETUP 1 |
310 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
311 | ||
312 | /* I2C */ | |
00f792e0 HS |
313 | #define CONFIG_SYS_I2C |
314 | #define CONFIG_SYS_I2C_FSL | |
315 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
316 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
317 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
318 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
8bd522ce DL |
319 | |
320 | /* | |
321 | * Board info - revision and where boot from | |
322 | */ | |
6d0f6bcf | 323 | #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 |
8bd522ce DL |
324 | |
325 | /* | |
326 | * Config on-board RTC | |
327 | */ | |
328 | #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
8bd522ce DL |
330 | |
331 | /* | |
332 | * General PCI | |
333 | * Addresses are mapped 1-1. | |
334 | */ | |
6f681b73 JH |
335 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
336 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
337 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
339 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
340 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
341 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
342 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
343 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
344 | ||
345 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
346 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
347 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
8bd522ce | 348 | |
8f11e34b AV |
349 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
350 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 | |
351 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 | |
352 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
353 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 | |
354 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 | |
355 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
356 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 | |
357 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
358 | ||
359 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
360 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 | |
361 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 | |
362 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
363 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 | |
364 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 | |
365 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
366 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 | |
367 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
368 | ||
8bd522ce | 369 | #define CONFIG_PCI |
842033e6 | 370 | #define CONFIG_PCI_INDIRECT_BRIDGE |
be9b56df | 371 | #define CONFIG_PCIE |
8bd522ce | 372 | |
8bd522ce DL |
373 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
374 | ||
375 | #define CONFIG_EEPRO100 | |
376 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 377 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
8bd522ce | 378 | |
25f5f0d4 | 379 | #define CONFIG_HAS_FSL_DR_USB |
6823e9b0 VM |
380 | #define CONFIG_SYS_SCCR_USBDRCM 3 |
381 | ||
382 | #define CONFIG_CMD_USB | |
383 | #define CONFIG_USB_STORAGE | |
384 | #define CONFIG_USB_EHCI | |
385 | #define CONFIG_USB_EHCI_FSL | |
6f681b73 | 386 | #define CONFIG_USB_PHY_TYPE "utmi" |
6823e9b0 | 387 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
25f5f0d4 | 388 | |
8bd522ce DL |
389 | /* |
390 | * TSEC | |
391 | */ | |
392 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
6d0f6bcf | 393 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
6f681b73 | 394 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 395 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
6f681b73 | 396 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
8bd522ce DL |
397 | |
398 | /* | |
399 | * TSEC ethernet configuration | |
400 | */ | |
401 | #define CONFIG_MII 1 /* MII PHY management */ | |
402 | #define CONFIG_TSEC1 1 | |
403 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
404 | #define CONFIG_TSEC2 1 | |
405 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
406 | #define TSEC1_PHY_ADDR 0 | |
407 | #define TSEC2_PHY_ADDR 1 | |
408 | #define TSEC1_PHYIDX 0 | |
409 | #define TSEC2_PHYIDX 0 | |
410 | #define TSEC1_FLAGS TSEC_GIGABIT | |
411 | #define TSEC2_FLAGS TSEC_GIGABIT | |
412 | ||
413 | /* Options are: eTSEC[0-1] */ | |
414 | #define CONFIG_ETHPRIME "eTSEC1" | |
415 | ||
730e7929 KP |
416 | /* |
417 | * SATA | |
418 | */ | |
419 | #define CONFIG_LIBATA | |
420 | #define CONFIG_FSL_SATA | |
421 | ||
6d0f6bcf | 422 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 423 | #define CONFIG_SATA1 |
6d0f6bcf | 424 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
6f681b73 JH |
425 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
426 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 427 | #define CONFIG_SATA2 |
6d0f6bcf | 428 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
6f681b73 JH |
429 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
430 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
431 | |
432 | #ifdef CONFIG_FSL_SATA | |
433 | #define CONFIG_LBA48 | |
434 | #define CONFIG_CMD_SATA | |
435 | #define CONFIG_DOS_PARTITION | |
436 | #define CONFIG_CMD_EXT2 | |
437 | #endif | |
438 | ||
8bd522ce DL |
439 | /* |
440 | * Environment | |
441 | */ | |
d0fb0fce | 442 | #if !defined(CONFIG_SYS_RAMBOOT) |
5a1aceb0 | 443 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6f681b73 JH |
444 | #define CONFIG_ENV_ADDR \ |
445 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
446 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
447 | #define CONFIG_ENV_SIZE 0x2000 | |
8bd522ce | 448 | #else |
6f681b73 | 449 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 450 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 451 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 452 | #define CONFIG_ENV_SIZE 0x2000 |
8bd522ce DL |
453 | #endif |
454 | ||
455 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 456 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8bd522ce DL |
457 | |
458 | /* | |
459 | * BOOTP options | |
460 | */ | |
461 | #define CONFIG_BOOTP_BOOTFILESIZE | |
462 | #define CONFIG_BOOTP_BOOTPATH | |
463 | #define CONFIG_BOOTP_GATEWAY | |
464 | #define CONFIG_BOOTP_HOSTNAME | |
465 | ||
466 | /* | |
467 | * Command line configuration. | |
468 | */ | |
8bd522ce DL |
469 | #define CONFIG_CMD_PING |
470 | #define CONFIG_CMD_I2C | |
471 | #define CONFIG_CMD_MII | |
472 | #define CONFIG_CMD_DATE | |
473 | #define CONFIG_CMD_PCI | |
474 | ||
8bd522ce | 475 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6f681b73 | 476 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
8bd522ce DL |
477 | |
478 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
479 | ||
480 | /* | |
481 | * Miscellaneous configurable options | |
482 | */ | |
6d0f6bcf JCPV |
483 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
484 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
8bd522ce DL |
485 | |
486 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 487 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8bd522ce | 488 | #else |
6d0f6bcf | 489 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8bd522ce DL |
490 | #endif |
491 | ||
6f681b73 JH |
492 | /* Print Buffer Size */ |
493 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
494 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
495 | /* Boot Argument Buffer Size */ | |
496 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
8bd522ce DL |
497 | |
498 | /* | |
499 | * For booting Linux, the board info and command line data | |
9f530d59 | 500 | * have to be in the first 256 MB of memory, since this is |
8bd522ce DL |
501 | * the maximum mapped by the Linux kernel during initialization. |
502 | */ | |
6f681b73 | 503 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
8bd522ce DL |
504 | |
505 | /* | |
506 | * Core HID Setup | |
507 | */ | |
1a2e203b KP |
508 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
509 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
510 | HID0_ENABLE_INSTRUCTION_CACHE | \ | |
8bd522ce | 511 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
6d0f6bcf | 512 | #define CONFIG_SYS_HID2 HID2_HBE |
8bd522ce DL |
513 | |
514 | /* | |
515 | * MMU Setup | |
516 | */ | |
31d82672 | 517 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
8bd522ce DL |
518 | |
519 | /* DDR: cache cacheable */ | |
6f681b73 | 520 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 521 | | BATL_PP_RW \ |
6f681b73 JH |
522 | | BATL_MEMCOHERENCE) |
523 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
524 | | BATU_BL_128M \ | |
525 | | BATU_VS \ | |
526 | | BATU_VP) | |
6d0f6bcf JCPV |
527 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
528 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
8bd522ce DL |
529 | |
530 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
6f681b73 | 531 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 532 | | BATL_PP_RW \ |
6f681b73 JH |
533 | | BATL_CACHEINHIBIT \ |
534 | | BATL_GUARDEDSTORAGE) | |
535 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
536 | | BATU_BL_8M \ | |
537 | | BATU_VS \ | |
538 | | BATU_VP) | |
6d0f6bcf JCPV |
539 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
540 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
8bd522ce DL |
541 | |
542 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
6f681b73 | 543 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 544 | | BATL_PP_RW \ |
6f681b73 JH |
545 | | BATL_MEMCOHERENCE) |
546 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ | |
547 | | BATU_BL_32M \ | |
548 | | BATU_VS \ | |
549 | | BATU_VP) | |
550 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 551 | | BATL_PP_RW \ |
6f681b73 JH |
552 | | BATL_CACHEINHIBIT \ |
553 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 554 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
8bd522ce DL |
555 | |
556 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 557 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
6f681b73 JH |
558 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ |
559 | | BATU_BL_128K \ | |
560 | | BATU_VS \ | |
561 | | BATU_VP) | |
6d0f6bcf JCPV |
562 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
563 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
8bd522ce DL |
564 | |
565 | /* PCI MEM space: cacheable */ | |
6f681b73 | 566 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 567 | | BATL_PP_RW \ |
6f681b73 JH |
568 | | BATL_MEMCOHERENCE) |
569 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ | |
570 | | BATU_BL_256M \ | |
571 | | BATU_VS \ | |
572 | | BATU_VP) | |
6d0f6bcf JCPV |
573 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
574 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
8bd522ce DL |
575 | |
576 | /* PCI MMIO space: cache-inhibit and guarded */ | |
6f681b73 | 577 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 578 | | BATL_PP_RW \ |
6f681b73 JH |
579 | | BATL_CACHEINHIBIT \ |
580 | | BATL_GUARDEDSTORAGE) | |
581 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
582 | | BATU_BL_256M \ | |
583 | | BATU_VS \ | |
584 | | BATU_VP) | |
6d0f6bcf JCPV |
585 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
586 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
587 | ||
588 | #define CONFIG_SYS_IBAT6L 0 | |
589 | #define CONFIG_SYS_IBAT6U 0 | |
590 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
591 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
592 | ||
593 | #define CONFIG_SYS_IBAT7L 0 | |
594 | #define CONFIG_SYS_IBAT7U 0 | |
595 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
596 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
8bd522ce | 597 | |
8bd522ce DL |
598 | #if defined(CONFIG_CMD_KGDB) |
599 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
8bd522ce DL |
600 | #endif |
601 | ||
602 | /* | |
603 | * Environment Configuration | |
604 | */ | |
605 | ||
606 | #define CONFIG_ENV_OVERWRITE | |
607 | ||
608 | #if defined(CONFIG_TSEC_ENET) | |
609 | #define CONFIG_HAS_ETH0 | |
8bd522ce | 610 | #define CONFIG_HAS_ETH1 |
8bd522ce DL |
611 | #endif |
612 | ||
613 | #define CONFIG_BAUDRATE 115200 | |
614 | ||
79f516bc | 615 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
8bd522ce DL |
616 | |
617 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
618 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
619 | ||
620 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
6f681b73 JH |
621 | "netdev=eth0\0" \ |
622 | "consoledev=ttyS0\0" \ | |
623 | "ramdiskaddr=1000000\0" \ | |
624 | "ramdiskfile=ramfs.83xx\0" \ | |
625 | "fdtaddr=780000\0" \ | |
626 | "fdtfile=mpc8315erdb.dtb\0" \ | |
627 | "usb_phy_type=utmi\0" \ | |
628 | "" | |
8bd522ce DL |
629 | |
630 | #define CONFIG_NFSBOOTCOMMAND \ | |
6f681b73 JH |
631 | "setenv bootargs root=/dev/nfs rw " \ |
632 | "nfsroot=$serverip:$rootpath " \ | |
633 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
634 | "$netdev:off " \ | |
635 | "console=$consoledev,$baudrate $othbootargs;" \ | |
636 | "tftp $loadaddr $bootfile;" \ | |
637 | "tftp $fdtaddr $fdtfile;" \ | |
638 | "bootm $loadaddr - $fdtaddr" | |
8bd522ce DL |
639 | |
640 | #define CONFIG_RAMBOOTCOMMAND \ | |
6f681b73 JH |
641 | "setenv bootargs root=/dev/ram rw " \ |
642 | "console=$consoledev,$baudrate $othbootargs;" \ | |
643 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
644 | "tftp $loadaddr $bootfile;" \ | |
645 | "tftp $fdtaddr $fdtfile;" \ | |
646 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
8bd522ce DL |
647 | |
648 | ||
649 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
650 | ||
651 | #endif /* __CONFIG_H */ |