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Commit | Line | Data |
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8bd522ce | 1 | /* |
e8d3ca8b | 2 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. |
8bd522ce DL |
3 | * |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
8bd522ce DL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
f1c574d4 SW |
12 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) |
13 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
14 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
15 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
16 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
17 | ||
f1c574d4 SW |
18 | #ifndef CONFIG_SYS_MONITOR_BASE |
19 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
20 | #endif | |
21 | ||
8bd522ce DL |
22 | /* |
23 | * High Level Configuration Options | |
24 | */ | |
25 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 26 | #define CONFIG_MPC831x 1 /* MPC831x CPU family */ |
8bd522ce DL |
27 | #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ |
28 | #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ | |
29 | ||
30 | /* | |
31 | * System Clock Setup | |
32 | */ | |
33 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
34 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
35 | ||
36 | /* | |
37 | * Hardware Reset Configuration Word | |
38 | * if CLKIN is 66.66MHz, then | |
39 | * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz | |
40 | */ | |
6d0f6bcf | 41 | #define CONFIG_SYS_HRCW_LOW (\ |
8bd522ce DL |
42 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
43 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
44 | HRCWL_SVCOD_DIV_2 |\ | |
45 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
46 | HRCWL_CORE_TO_CSB_3X1) | |
2e95004d | 47 | #define CONFIG_SYS_HRCW_HIGH_BASE (\ |
8bd522ce DL |
48 | HRCWH_PCI_HOST |\ |
49 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
50 | HRCWH_CORE_ENABLE |\ | |
8bd522ce DL |
51 | HRCWH_BOOTSEQ_DISABLE |\ |
52 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
8bd522ce DL |
53 | HRCWH_TSEC1M_IN_RGMII |\ |
54 | HRCWH_TSEC2M_IN_RGMII |\ | |
55 | HRCWH_BIG_ENDIAN |\ | |
56 | HRCWH_LALE_NORMAL) | |
57 | ||
2e95004d AV |
58 | #ifdef CONFIG_NAND_SPL |
59 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ | |
60 | HRCWH_FROM_0XFFF00100 |\ | |
61 | HRCWH_ROM_LOC_NAND_SP_8BIT |\ | |
62 | HRCWH_RL_EXT_NAND) | |
63 | #else | |
64 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ | |
65 | HRCWH_FROM_0X00000100 |\ | |
66 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
67 | HRCWH_RL_EXT_LEGACY) | |
68 | #endif | |
69 | ||
8bd522ce DL |
70 | /* |
71 | * System IO Config | |
72 | */ | |
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_SICRH 0x00000000 |
74 | #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ | |
8bd522ce | 75 | |
b8b71ffb | 76 | #define CONFIG_HWCONFIG |
8bd522ce DL |
77 | |
78 | /* | |
79 | * IMMR new address | |
80 | */ | |
6d0f6bcf | 81 | #define CONFIG_SYS_IMMR 0xE0000000 |
8bd522ce DL |
82 | |
83 | /* | |
84 | * Arbiter Setup | |
85 | */ | |
6d0f6bcf | 86 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
6f681b73 JH |
87 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
88 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ | |
8bd522ce DL |
89 | |
90 | /* | |
91 | * DDR Setup | |
92 | */ | |
6d0f6bcf JCPV |
93 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
94 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
95 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
96 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
6f681b73 | 97 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
8bd522ce DL |
98 | | DDRCDR_PZ_LOZ \ |
99 | | DDRCDR_NZ_LOZ \ | |
100 | | DDRCDR_ODT \ | |
6f681b73 | 101 | | DDRCDR_Q_DRN) |
8bd522ce DL |
102 | /* 0x7b880001 */ |
103 | /* | |
104 | * Manually set up DDR parameters | |
105 | * consist of two chips HY5PS12621BFP-C4 from HYNIX | |
106 | */ | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
108 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 | |
6f681b73 | 109 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
110 | | CSCONFIG_ODT_RD_NEVER \ |
111 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
6f681b73 JH |
112 | | CSCONFIG_ROW_BIT_13 \ |
113 | | CSCONFIG_COL_BIT_10) | |
8bd522ce | 114 | /* 0x80010102 */ |
6d0f6bcf | 115 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
6f681b73 JH |
116 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
117 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
118 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
119 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
120 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
121 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
122 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
123 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
8bd522ce | 124 | /* 0x00220802 */ |
6f681b73 JH |
125 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
126 | | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
127 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
128 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
129 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ | |
130 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
131 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
132 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
2f2a5c37 | 133 | /* 0x27256222 */ |
6f681b73 JH |
134 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
135 | | (4 << TIMING_CFG2_CPO_SHIFT) \ | |
136 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
137 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
138 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
139 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
140 | | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
2f2a5c37 | 141 | /* 0x121048c5 */ |
6f681b73 JH |
142 | #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
143 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
8bd522ce | 144 | /* 0x03600100 */ |
6f681b73 | 145 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
8bd522ce | 146 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 | 147 | | SDRAM_CFG_DBW_32) |
8bd522ce | 148 | /* 0x43080000 */ |
6d0f6bcf | 149 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
6f681b73 JH |
150 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
151 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
8bd522ce | 152 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
6f681b73 | 153 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
8bd522ce DL |
154 | |
155 | /* | |
156 | * Memory test | |
157 | */ | |
6d0f6bcf JCPV |
158 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
159 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
160 | #define CONFIG_SYS_MEMTEST_END 0x00140000 | |
8bd522ce DL |
161 | |
162 | /* | |
163 | * The reserved memory | |
164 | */ | |
16c8c170 | 165 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
6f681b73 | 166 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
8bd522ce DL |
167 | |
168 | /* | |
169 | * Initial RAM Base Address Setup | |
170 | */ | |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
172 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 173 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
6f681b73 JH |
174 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
175 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
8bd522ce DL |
176 | |
177 | /* | |
178 | * Local Bus Configuration & Clock Setup | |
179 | */ | |
c7190f02 KP |
180 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
181 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
6d0f6bcf | 182 | #define CONFIG_SYS_LBC_LBCR 0x00040000 |
0914f483 | 183 | #define CONFIG_FSL_ELBC 1 |
8bd522ce DL |
184 | |
185 | /* | |
186 | * FLASH on the Local Bus | |
187 | */ | |
6d0f6bcf | 188 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 189 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf | 190 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
8bd522ce | 191 | |
6d0f6bcf | 192 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
6f681b73 JH |
193 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ |
194 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
8bd522ce | 195 | |
6f681b73 JH |
196 | /* Window base at flash base */ |
197 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 198 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
8bd522ce | 199 | |
2e95004d | 200 | #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
201 | | BR_PS_16 /* 16 bit port */ \ |
202 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
203 | | BR_V) /* valid */ | |
204 | #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
205 | | OR_UPM_XAM \ | |
206 | | OR_GPCM_CSNT \ | |
207 | | OR_GPCM_ACS_DIV2 \ | |
208 | | OR_GPCM_XACS \ | |
209 | | OR_GPCM_SCY_15 \ | |
210 | | OR_GPCM_TRLX_SET \ | |
211 | | OR_GPCM_EHTR_SET \ | |
212 | | OR_GPCM_EAD) | |
8bd522ce | 213 | |
6d0f6bcf | 214 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
6f681b73 JH |
215 | /* 127 64KB sectors and 8 8KB top sectors per device */ |
216 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
8bd522ce | 217 | |
6d0f6bcf JCPV |
218 | #undef CONFIG_SYS_FLASH_CHECKSUM |
219 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
220 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
8bd522ce DL |
221 | |
222 | /* | |
223 | * NAND Flash on the Local Bus | |
224 | */ | |
2e95004d AV |
225 | |
226 | #ifdef CONFIG_NAND_SPL | |
227 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
228 | #else | |
229 | #define CONFIG_SYS_NAND_BASE 0xE0600000 | |
230 | #endif | |
231 | ||
e8d3ca8b SW |
232 | #define CONFIG_MTD_DEVICE |
233 | #define CONFIG_MTD_PARTITION | |
e8d3ca8b | 234 | |
6d0f6bcf | 235 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
1ac5744e | 236 | #define CONFIG_NAND_FSL_ELBC 1 |
7d6a0982 JH |
237 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 |
238 | #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ | |
2e95004d AV |
239 | |
240 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) | |
241 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
242 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
243 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
244 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
8bd522ce | 245 | |
2e95004d | 246 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 247 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
6f681b73 | 248 | | BR_PS_8 /* 8 bit port */ \ |
8bd522ce | 249 | | BR_MS_FCM /* MSEL = FCM */ \ |
6f681b73 | 250 | | BR_V) /* valid */ |
7d6a0982 JH |
251 | #define CONFIG_SYS_NAND_OR_PRELIM \ |
252 | (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | |
8bd522ce DL |
253 | | OR_FCM_CSCT \ |
254 | | OR_FCM_CST \ | |
255 | | OR_FCM_CHT \ | |
256 | | OR_FCM_SCY_1 \ | |
257 | | OR_FCM_TRLX \ | |
6f681b73 | 258 | | OR_FCM_EHTR) |
8bd522ce DL |
259 | /* 0xFFFF8396 */ |
260 | ||
2e95004d AV |
261 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM |
262 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
263 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
264 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
2e95004d | 265 | |
6d0f6bcf | 266 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 267 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
8bd522ce | 268 | |
2e95004d AV |
269 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM |
270 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
271 | ||
272 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ | |
273 | !defined(CONFIG_NAND_SPL) | |
274 | #define CONFIG_SYS_RAMBOOT | |
275 | #else | |
276 | #undef CONFIG_SYS_RAMBOOT | |
277 | #endif | |
278 | ||
8bd522ce DL |
279 | /* |
280 | * Serial Port | |
281 | */ | |
282 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_NS16550_SERIAL |
284 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
2e95004d | 285 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) |
8bd522ce | 286 | |
6d0f6bcf | 287 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
6f681b73 | 288 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
8bd522ce | 289 | |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
291 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
8bd522ce | 292 | |
8bd522ce | 293 | /* I2C */ |
00f792e0 HS |
294 | #define CONFIG_SYS_I2C |
295 | #define CONFIG_SYS_I2C_FSL | |
296 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
297 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
298 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
299 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
8bd522ce DL |
300 | |
301 | /* | |
302 | * Board info - revision and where boot from | |
303 | */ | |
6d0f6bcf | 304 | #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 |
8bd522ce DL |
305 | |
306 | /* | |
307 | * Config on-board RTC | |
308 | */ | |
309 | #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ | |
6d0f6bcf | 310 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
8bd522ce DL |
311 | |
312 | /* | |
313 | * General PCI | |
314 | * Addresses are mapped 1-1. | |
315 | */ | |
6f681b73 JH |
316 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
317 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
318 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
320 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
321 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
322 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
323 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
324 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
325 | ||
326 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
327 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
328 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
8bd522ce | 329 | |
8f11e34b AV |
330 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
331 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 | |
332 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 | |
333 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
334 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 | |
335 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 | |
336 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
337 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 | |
338 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
339 | ||
340 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
341 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 | |
342 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 | |
343 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
344 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 | |
345 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 | |
346 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
347 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 | |
348 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
349 | ||
842033e6 | 350 | #define CONFIG_PCI_INDIRECT_BRIDGE |
be9b56df | 351 | #define CONFIG_PCIE |
8bd522ce | 352 | |
8bd522ce DL |
353 | #define CONFIG_EEPRO100 |
354 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 355 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
8bd522ce | 356 | |
25f5f0d4 | 357 | #define CONFIG_HAS_FSL_DR_USB |
6823e9b0 VM |
358 | #define CONFIG_SYS_SCCR_USBDRCM 3 |
359 | ||
6823e9b0 | 360 | #define CONFIG_USB_EHCI_FSL |
6f681b73 | 361 | #define CONFIG_USB_PHY_TYPE "utmi" |
6823e9b0 | 362 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
25f5f0d4 | 363 | |
8bd522ce DL |
364 | /* |
365 | * TSEC | |
366 | */ | |
367 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
6d0f6bcf | 368 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
6f681b73 | 369 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 370 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
6f681b73 | 371 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
8bd522ce DL |
372 | |
373 | /* | |
374 | * TSEC ethernet configuration | |
375 | */ | |
376 | #define CONFIG_MII 1 /* MII PHY management */ | |
377 | #define CONFIG_TSEC1 1 | |
378 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
379 | #define CONFIG_TSEC2 1 | |
380 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
381 | #define TSEC1_PHY_ADDR 0 | |
382 | #define TSEC2_PHY_ADDR 1 | |
383 | #define TSEC1_PHYIDX 0 | |
384 | #define TSEC2_PHYIDX 0 | |
385 | #define TSEC1_FLAGS TSEC_GIGABIT | |
386 | #define TSEC2_FLAGS TSEC_GIGABIT | |
387 | ||
388 | /* Options are: eTSEC[0-1] */ | |
389 | #define CONFIG_ETHPRIME "eTSEC1" | |
390 | ||
730e7929 KP |
391 | /* |
392 | * SATA | |
393 | */ | |
6d0f6bcf | 394 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 395 | #define CONFIG_SATA1 |
6d0f6bcf | 396 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
6f681b73 JH |
397 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
398 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 399 | #define CONFIG_SATA2 |
6d0f6bcf | 400 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
6f681b73 JH |
401 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
402 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
403 | |
404 | #ifdef CONFIG_FSL_SATA | |
405 | #define CONFIG_LBA48 | |
730e7929 KP |
406 | #endif |
407 | ||
8bd522ce DL |
408 | /* |
409 | * Environment | |
410 | */ | |
d0fb0fce | 411 | #if !defined(CONFIG_SYS_RAMBOOT) |
6f681b73 JH |
412 | #define CONFIG_ENV_ADDR \ |
413 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
414 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
415 | #define CONFIG_ENV_SIZE 0x2000 | |
8bd522ce | 416 | #else |
6d0f6bcf | 417 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 418 | #define CONFIG_ENV_SIZE 0x2000 |
8bd522ce DL |
419 | #endif |
420 | ||
421 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 422 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8bd522ce DL |
423 | |
424 | /* | |
425 | * BOOTP options | |
426 | */ | |
427 | #define CONFIG_BOOTP_BOOTFILESIZE | |
428 | #define CONFIG_BOOTP_BOOTPATH | |
429 | #define CONFIG_BOOTP_GATEWAY | |
430 | #define CONFIG_BOOTP_HOSTNAME | |
431 | ||
432 | /* | |
433 | * Command line configuration. | |
434 | */ | |
8bd522ce | 435 | |
8bd522ce | 436 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6f681b73 | 437 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
8bd522ce DL |
438 | |
439 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
440 | ||
441 | /* | |
442 | * Miscellaneous configurable options | |
443 | */ | |
6d0f6bcf JCPV |
444 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
445 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
8bd522ce | 446 | |
8bd522ce DL |
447 | /* |
448 | * For booting Linux, the board info and command line data | |
9f530d59 | 449 | * have to be in the first 256 MB of memory, since this is |
8bd522ce DL |
450 | * the maximum mapped by the Linux kernel during initialization. |
451 | */ | |
6f681b73 | 452 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
63865278 | 453 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
8bd522ce DL |
454 | |
455 | /* | |
456 | * Core HID Setup | |
457 | */ | |
1a2e203b KP |
458 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
459 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
460 | HID0_ENABLE_INSTRUCTION_CACHE | \ | |
8bd522ce | 461 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
6d0f6bcf | 462 | #define CONFIG_SYS_HID2 HID2_HBE |
8bd522ce DL |
463 | |
464 | /* | |
465 | * MMU Setup | |
466 | */ | |
31d82672 | 467 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
8bd522ce DL |
468 | |
469 | /* DDR: cache cacheable */ | |
6f681b73 | 470 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 471 | | BATL_PP_RW \ |
6f681b73 JH |
472 | | BATL_MEMCOHERENCE) |
473 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
474 | | BATU_BL_128M \ | |
475 | | BATU_VS \ | |
476 | | BATU_VP) | |
6d0f6bcf JCPV |
477 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
478 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
8bd522ce DL |
479 | |
480 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
6f681b73 | 481 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 482 | | BATL_PP_RW \ |
6f681b73 JH |
483 | | BATL_CACHEINHIBIT \ |
484 | | BATL_GUARDEDSTORAGE) | |
485 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
486 | | BATU_BL_8M \ | |
487 | | BATU_VS \ | |
488 | | BATU_VP) | |
6d0f6bcf JCPV |
489 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
490 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
8bd522ce DL |
491 | |
492 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
6f681b73 | 493 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 494 | | BATL_PP_RW \ |
6f681b73 JH |
495 | | BATL_MEMCOHERENCE) |
496 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ | |
497 | | BATU_BL_32M \ | |
498 | | BATU_VS \ | |
499 | | BATU_VP) | |
500 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 501 | | BATL_PP_RW \ |
6f681b73 JH |
502 | | BATL_CACHEINHIBIT \ |
503 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 504 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
8bd522ce DL |
505 | |
506 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 507 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
6f681b73 JH |
508 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ |
509 | | BATU_BL_128K \ | |
510 | | BATU_VS \ | |
511 | | BATU_VP) | |
6d0f6bcf JCPV |
512 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
513 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
8bd522ce DL |
514 | |
515 | /* PCI MEM space: cacheable */ | |
6f681b73 | 516 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 517 | | BATL_PP_RW \ |
6f681b73 JH |
518 | | BATL_MEMCOHERENCE) |
519 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ | |
520 | | BATU_BL_256M \ | |
521 | | BATU_VS \ | |
522 | | BATU_VP) | |
6d0f6bcf JCPV |
523 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
524 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
8bd522ce DL |
525 | |
526 | /* PCI MMIO space: cache-inhibit and guarded */ | |
6f681b73 | 527 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 528 | | BATL_PP_RW \ |
6f681b73 JH |
529 | | BATL_CACHEINHIBIT \ |
530 | | BATL_GUARDEDSTORAGE) | |
531 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
532 | | BATU_BL_256M \ | |
533 | | BATU_VS \ | |
534 | | BATU_VP) | |
6d0f6bcf JCPV |
535 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
536 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
537 | ||
538 | #define CONFIG_SYS_IBAT6L 0 | |
539 | #define CONFIG_SYS_IBAT6U 0 | |
540 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
541 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
542 | ||
543 | #define CONFIG_SYS_IBAT7L 0 | |
544 | #define CONFIG_SYS_IBAT7U 0 | |
545 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
546 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
8bd522ce | 547 | |
8bd522ce DL |
548 | #if defined(CONFIG_CMD_KGDB) |
549 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
8bd522ce DL |
550 | #endif |
551 | ||
552 | /* | |
553 | * Environment Configuration | |
554 | */ | |
555 | ||
556 | #define CONFIG_ENV_OVERWRITE | |
557 | ||
558 | #if defined(CONFIG_TSEC_ENET) | |
559 | #define CONFIG_HAS_ETH0 | |
8bd522ce | 560 | #define CONFIG_HAS_ETH1 |
8bd522ce DL |
561 | #endif |
562 | ||
79f516bc | 563 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
8bd522ce | 564 | |
8bd522ce | 565 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
6f681b73 JH |
566 | "netdev=eth0\0" \ |
567 | "consoledev=ttyS0\0" \ | |
568 | "ramdiskaddr=1000000\0" \ | |
569 | "ramdiskfile=ramfs.83xx\0" \ | |
570 | "fdtaddr=780000\0" \ | |
571 | "fdtfile=mpc8315erdb.dtb\0" \ | |
572 | "usb_phy_type=utmi\0" \ | |
573 | "" | |
8bd522ce DL |
574 | |
575 | #define CONFIG_NFSBOOTCOMMAND \ | |
6f681b73 JH |
576 | "setenv bootargs root=/dev/nfs rw " \ |
577 | "nfsroot=$serverip:$rootpath " \ | |
578 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
579 | "$netdev:off " \ | |
580 | "console=$consoledev,$baudrate $othbootargs;" \ | |
581 | "tftp $loadaddr $bootfile;" \ | |
582 | "tftp $fdtaddr $fdtfile;" \ | |
583 | "bootm $loadaddr - $fdtaddr" | |
8bd522ce DL |
584 | |
585 | #define CONFIG_RAMBOOTCOMMAND \ | |
6f681b73 JH |
586 | "setenv bootargs root=/dev/ram rw " \ |
587 | "console=$consoledev,$baudrate $othbootargs;" \ | |
588 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
589 | "tftp $loadaddr $bootfile;" \ | |
590 | "tftp $fdtaddr $fdtfile;" \ | |
591 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
8bd522ce | 592 | |
8bd522ce DL |
593 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
594 | ||
595 | #endif /* __CONFIG_H */ |