[thirdparty/u-boot.git] / include / configs / MPC8315ERDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
 *
 * Dave Liu <daveliu@freescale.com>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000

#ifndef CONFIG_SYS_MONITOR_BASE
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH		0x00000000
#define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */

#define CONFIG_HWCONFIG

/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 */
#define CONFIG_SYS_DDR_SIZE		128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_32)
				/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2	0x00000000

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * NAND Flash on the Local Bus
 */

#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE		0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE		0xE0600000
#endif

#define CONFIG_MTD_PARTITION

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_NAND_FSL_ELBC		1
#define CONFIG_SYS_NAND_BLOCK_SIZE	16384
#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */

#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000


/* Still needed for spl_minimal.c */
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM

#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
	!defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Board info - revision and where boot from
 */
#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_PCI_IO_BASE		0x00000000
#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000

#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

#define CONFIG_SYS_PCIE2_BASE		0xC0000000
#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_SYS_SCCR_USBDRCM		3

#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_PHY_TYPE	"utmi"
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

/*
 * TSEC
 */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC1"

/*
 * SATA
 */
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET	0x18000
#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET	0x19000
#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA

#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#endif

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * MMU Setup
 */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=ramfs.83xx\0"					\
	"fdtaddr=780000\0"						\
	"fdtfile=mpc8315erdb.dtb\0"					\
	"usb_phy_type=utmi\0"						\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
8bd522ce	2	/*
e8d3ca8b	3	* Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
8bd522ce DL	4	*
8bd522ce DL	5	* Dave Liu <daveliu@freescale.com>
8bd522ce DL	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
f1c574d4 SW	11	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	12	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	13	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	14	#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
	15	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
	16
f1c574d4 SW	17	#ifndef CONFIG_SYS_MONITOR_BASE
	18	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	19	#endif
	20
8bd522ce DL	21	/*
	22	* High Level Configuration Options
	23	*/
	24	#define CONFIG_E300 1 /* E300 family */
8bd522ce	25
8bd522ce DL	26	/*
	27	* System IO Config
	28	*/
6d0f6bcf JCPV	29	#define CONFIG_SYS_SICRH 0x00000000
6d0f6bcf JCPV	30	#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
8bd522ce	31
b8b71ffb	32	#define CONFIG_HWCONFIG
8bd522ce	33
8bd522ce DL	34	/*
	35	* DDR Setup
	36	*/
8a81bfd2	37	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
6d0f6bcf	38	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
6f681b73	39	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
8bd522ce DL	40	\| DDRCDR_PZ_LOZ \
	41	\| DDRCDR_NZ_LOZ \
	42	\| DDRCDR_ODT \
6f681b73	43	\| DDRCDR_Q_DRN)
8bd522ce DL	44	/* 0x7b880001 */
	45	/*
	46	* Manually set up DDR parameters
	47	* consist of two chips HY5PS12621BFP-C4 from HYNIX
	48	*/
6d0f6bcf JCPV	49	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
6d0f6bcf JCPV	50	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
6f681b73	51	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
2fef4020 JH	52	\| CSCONFIG_ODT_RD_NEVER \
2fef4020 JH	53	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
6f681b73 JH	54	\| CSCONFIG_ROW_BIT_13 \
6f681b73 JH	55	\| CSCONFIG_COL_BIT_10)
8bd522ce	56	/* 0x80010102 */
6d0f6bcf	57	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
6f681b73 JH	58	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	59	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	60	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	61	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	62	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	63	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	64	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	65	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
8bd522ce	66	/* 0x00220802 */
6f681b73 JH	67	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	68	\| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	69	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	70	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	71	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
	72	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	73	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	74	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
2f2a5c37	75	/* 0x27256222 */
6f681b73 JH	76	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	77	\| (4 << TIMING_CFG2_CPO_SHIFT) \
	78	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	79	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	80	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	81	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	82	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
2f2a5c37	83	/* 0x121048c5 */
6f681b73 JH	84	#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
6f681b73 JH	85	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
8bd522ce	86	/* 0x03600100 */
6f681b73	87	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
8bd522ce	88	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
2fef4020	89	\| SDRAM_CFG_DBW_32)
8bd522ce	90	/* 0x43080000 */
6d0f6bcf	91	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
6f681b73 JH	92	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
6f681b73 JH	93	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
8bd522ce	94	/* ODT 150ohm CL=3, AL=1 on SDRAM */
6f681b73	95	#define CONFIG_SYS_DDR_MODE2 0x00000000
8bd522ce DL	96
	97	/*
	98	* Memory test
	99	*/
6d0f6bcf	100	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
8bd522ce DL	101
	102	/*
	103	* The reserved memory
	104	*/
16c8c170	105	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
6f681b73	106	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
8bd522ce DL	107
	108	/*
	109	* Initial RAM Base Address Setup
	110	*/
6d0f6bcf JCPV	111	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	112	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
553f0982	113	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
6f681b73 JH	114	#define CONFIG_SYS_GBL_DATA_OFFSET \
6f681b73 JH	115	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
8bd522ce	116
8bd522ce DL	117	/*
	118	* FLASH on the Local Bus
	119	*/
6d0f6bcf	120	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
8bd522ce	121
6d0f6bcf	122	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
6f681b73	123	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
8bd522ce	124
6d0f6bcf	125	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
6f681b73 JH	126	/* 127 64KB sectors and 8 8KB top sectors per device */
6f681b73 JH	127	#define CONFIG_SYS_MAX_FLASH_SECT 135
8bd522ce	128
6d0f6bcf JCPV	129	#undef CONFIG_SYS_FLASH_CHECKSUM
	130	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	131	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
8bd522ce DL	132
	133	/*
	134	* NAND Flash on the Local Bus
	135	*/
2e95004d AV	136
	137	#ifdef CONFIG_NAND_SPL
	138	#define CONFIG_SYS_NAND_BASE 0xFFF00000
	139	#else
	140	#define CONFIG_SYS_NAND_BASE 0xE0600000
	141	#endif
	142
e8d3ca8b	143	#define CONFIG_MTD_PARTITION
e8d3ca8b	144
6d0f6bcf	145	#define CONFIG_SYS_MAX_NAND_DEVICE 1
1ac5744e	146	#define CONFIG_NAND_FSL_ELBC 1
7d6a0982 JH	147	#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
7d6a0982 JH	148	#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
2e95004d AV	149
	150	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	151	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	152	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	153	#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
	154	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
8bd522ce	155
a8f97539	156
8bd522ce	157
7577cb19 MS	158	/* Still needed for spl_minimal.c */
	159	#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
	160	#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
2e95004d	161
2e95004d AV	162	#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
	163	!defined(CONFIG_NAND_SPL)
	164	#define CONFIG_SYS_RAMBOOT
	165	#else
	166	#undef CONFIG_SYS_RAMBOOT
	167	#endif
	168
8bd522ce DL	169	/*
	170	* Serial Port
	171	*/
6d0f6bcf JCPV	172	#define CONFIG_SYS_NS16550_SERIAL
6d0f6bcf JCPV	173	#define CONFIG_SYS_NS16550_REG_SIZE 1
0f06f57c	174	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
8bd522ce	175
6d0f6bcf	176	#define CONFIG_SYS_BAUDRATE_TABLE \
6f681b73	177	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
8bd522ce	178
6d0f6bcf JCPV	179	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	180	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
8bd522ce	181
8bd522ce	182	/* I2C */
00f792e0 HS	183	#define CONFIG_SYS_I2C
	184	#define CONFIG_SYS_I2C_FSL
	185	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	186	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	187	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	188	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
8bd522ce DL	189
	190	/*
	191	* Board info - revision and where boot from
	192	*/
6d0f6bcf	193	#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
8bd522ce DL	194
	195	/*
	196	* Config on-board RTC
	197	*/
	198	#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
6d0f6bcf	199	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
8bd522ce DL	200
	201	/*
	202	* General PCI
	203	* Addresses are mapped 1-1.
	204	*/
6f681b73 JH	205	#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
	206	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
	207	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
6d0f6bcf JCPV	208	#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
	209	#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
	210	#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
	211	#define CONFIG_SYS_PCI_IO_BASE 0x00000000
	212	#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
	213	#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
	214
	215	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
	216	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
	217	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
8bd522ce	218
8f11e34b AV	219	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	220	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	221	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	222	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	223	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	224	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	225	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	226	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	227	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	228
	229	#define CONFIG_SYS_PCIE2_BASE 0xC0000000
	230	#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
	231	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
	232	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
	233	#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
	234	#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
	235	#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
	236	#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
	237	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
	238
842033e6	239	#define CONFIG_PCI_INDIRECT_BRIDGE
be9b56df	240	#define CONFIG_PCIE
8bd522ce	241
8bd522ce DL	242	#define CONFIG_EEPRO100
8bd522ce DL	243	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	244	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
8bd522ce	245
25f5f0d4	246	#define CONFIG_HAS_FSL_DR_USB
6823e9b0 VM	247	#define CONFIG_SYS_SCCR_USBDRCM 3
6823e9b0 VM	248
6823e9b0	249	#define CONFIG_USB_EHCI_FSL
6f681b73	250	#define CONFIG_USB_PHY_TYPE "utmi"
6823e9b0	251	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
25f5f0d4	252
8bd522ce DL	253	/*
	254	* TSEC
	255	*/
6d0f6bcf	256	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
6f681b73	257	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf	258	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
6f681b73	259	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
8bd522ce DL	260
	261	/*
	262	* TSEC ethernet configuration
	263	*/
8bd522ce DL	264	#define CONFIG_TSEC1 1
	265	#define CONFIG_TSEC1_NAME "eTSEC0"
	266	#define CONFIG_TSEC2 1
	267	#define CONFIG_TSEC2_NAME "eTSEC1"
	268	#define TSEC1_PHY_ADDR 0
	269	#define TSEC2_PHY_ADDR 1
	270	#define TSEC1_PHYIDX 0
	271	#define TSEC2_PHYIDX 0
	272	#define TSEC1_FLAGS TSEC_GIGABIT
	273	#define TSEC2_FLAGS TSEC_GIGABIT
	274
	275	/* Options are: eTSEC[0-1] */
	276	#define CONFIG_ETHPRIME "eTSEC1"
	277
730e7929 KP	278	/*
	279	* SATA
	280	*/
6d0f6bcf	281	#define CONFIG_SYS_SATA_MAX_DEVICE 2
730e7929	282	#define CONFIG_SATA1
6d0f6bcf	283	#define CONFIG_SYS_SATA1_OFFSET 0x18000
6f681b73 JH	284	#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
6f681b73 JH	285	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
730e7929	286	#define CONFIG_SATA2
6d0f6bcf	287	#define CONFIG_SYS_SATA2_OFFSET 0x19000
6f681b73 JH	288	#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
6f681b73 JH	289	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
730e7929 KP	290
	291	#ifdef CONFIG_FSL_SATA
	292	#define CONFIG_LBA48
730e7929 KP	293	#endif
730e7929 KP	294
8bd522ce DL	295	/*
	296	* Environment
	297	*/
8bd522ce DL	298
8bd522ce DL	299	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	300	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
8bd522ce DL	301
	302	/*
	303	* BOOTP options
	304	*/
	305	#define CONFIG_BOOTP_BOOTFILESIZE
8bd522ce DL	306
	307	/*
	308	* Command line configuration.
	309	*/
8bd522ce	310
8bd522ce DL	311	#undef CONFIG_WATCHDOG /* watchdog disabled */
	312
	313	/*
	314	* Miscellaneous configurable options
	315	*/
6d0f6bcf	316	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
8bd522ce	317
8bd522ce DL	318	/*
8bd522ce DL	319	* For booting Linux, the board info and command line data
9f530d59	320	* have to be in the first 256 MB of memory, since this is
8bd522ce DL	321	* the maximum mapped by the Linux kernel during initialization.
8bd522ce DL	322	*/
6f681b73	323	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
63865278	324	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
8bd522ce	325
8bd522ce DL	326	/*
	327	* MMU Setup
	328	*/
	329
8bd522ce DL	330	#if defined(CONFIG_CMD_KGDB)
8bd522ce DL	331	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
8bd522ce DL	332	#endif
	333
	334	/*
	335	* Environment Configuration
	336	*/
	337
	338	#define CONFIG_ENV_OVERWRITE
	339
	340	#if defined(CONFIG_TSEC_ENET)
	341	#define CONFIG_HAS_ETH0
8bd522ce	342	#define CONFIG_HAS_ETH1
8bd522ce DL	343	#endif
8bd522ce DL	344
79f516bc	345	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
8bd522ce	346
8bd522ce	347	#define CONFIG_EXTRA_ENV_SETTINGS \
6f681b73 JH	348	"netdev=eth0\0" \
	349	"consoledev=ttyS0\0" \
	350	"ramdiskaddr=1000000\0" \
	351	"ramdiskfile=ramfs.83xx\0" \
	352	"fdtaddr=780000\0" \
	353	"fdtfile=mpc8315erdb.dtb\0" \
	354	"usb_phy_type=utmi\0" \
	355	""
8bd522ce DL	356
8bd522ce DL	357	#define CONFIG_NFSBOOTCOMMAND \
6f681b73 JH	358	"setenv bootargs root=/dev/nfs rw " \
	359	"nfsroot=$serverip:$rootpath " \
	360	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	361	"$netdev:off " \
	362	"console=$consoledev,$baudrate $othbootargs;" \
	363	"tftp $loadaddr $bootfile;" \
	364	"tftp $fdtaddr $fdtfile;" \
	365	"bootm $loadaddr - $fdtaddr"
8bd522ce DL	366
8bd522ce DL	367	#define CONFIG_RAMBOOTCOMMAND \
6f681b73 JH	368	"setenv bootargs root=/dev/ram rw " \
	369	"console=$consoledev,$baudrate $othbootargs;" \
	370	"tftp $ramdiskaddr $ramdiskfile;" \
	371	"tftp $loadaddr $bootfile;" \
	372	"tftp $fdtaddr $fdtfile;" \
	373	"bootm $loadaddr $ramdiskaddr $fdtaddr"
8bd522ce	374
8bd522ce DL	375	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	376
	377	#endif /* __CONFIG_H */