[people/ms/u-boot.git] / include / configs / MPC8323ERDB.h

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 family */
#define CONFIG_QE		1	/* Has QE */
#define CONFIG_MPC832x		1	/* MPC832x CPU specific */

#define	CONFIG_SYS_TEXT_BASE	0xFE000000

#define CONFIG_PCI		1

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	66666667	/* in Hz */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
#endif

/*
 * Hardware Reset Configuration Word
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CSB_TO_CLKIN_2X1 |\
	HRCWL_CORE_TO_CSB_2_5X1 |\
	HRCWL_CE_PLL_VCO_DIV_2 |\
	HRCWL_CE_PLL_DIV_1X1 |\
	HRCWL_CE_TO_PLL_1X3)

#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_NORMAL)

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRL		0x00000000

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * System performance
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
#define CONFIG_SYS_SPCR_OPT	1

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE

#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
 */
#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
#else
/* Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE	64	/* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_9)
				/* 0x80010101 */
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (3 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x26253222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (31 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x1f9048c7 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
				/* 0x02000000 */
#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* 0x44480232 */
#define CONFIG_SYS_DDR_MODE2	0x8000c000
#define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_32_BE)
				/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#endif

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x03f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00000000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_GPCM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
				/* 0xFE006FF7 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Config on-board EEPROM
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#define CONFIG_UEC_ETH1		/* ETH3 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	4
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

#define CONFIG_UEC_ETH2		/* ETH4 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR	0
#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
	#define CONFIG_ENV_IS_IN_FLASH	1
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x20000
	#define CONFIG_ENV_SIZE		0x2000
#else
	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ASKENV

#if defined(CONFIG_PCI)
	#define CONFIG_CMD_PCI
#endif

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#if (CONFIG_CMD_KGDB)
	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

				/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
				/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
					/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */
#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
				| BATU_BL_4M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_32M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_MEM_PHYS \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_MEM_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MMIO_PHYS \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MMIO_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#else
#define CONFIG_SYS_IBAT5L	(0)
#define CONFIG_SYS_IBAT5U	(0)
#define CONFIG_SYS_IBAT6L	(0)
#define CONFIG_SYS_IBAT6U	(0)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#endif

/* Nothing in BAT7 */
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
#define CONFIG_HAS_ETH1		/* add support for "eth1addr" */

/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 * (see CONFIG_SYS_I2C_EEPROM) */
					/* MAC address offset in I2C EEPROM */
#define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00

#define CONFIG_NETDEV		"eth1"

#define CONFIG_HOSTNAME		mpc8323erdb
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot.bin"
#define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		800000
#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
#define CONFIG_BAUDRATE		115200

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0"					\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftp $loadaddr $uboot;"				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=780000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"					\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
								"$netdev:off "\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
1c274c4e KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License version 2 as published
	6	* by the Free Software Foundation.
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
fdfaa29e KP	12	#define CONFIG_SYS_GENERIC_BOARD
	13	#define CONFIG_DISPLAY_BOARDINFO
	14
1c274c4e KP	15	/*
	16	* High Level Configuration Options
	17	*/
	18	#define CONFIG_E300 1 /* E300 family */
	19	#define CONFIG_QE 1 /* Has QE */
2c7920af	20	#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
1c274c4e	21
2ae18241 WD	22	#define CONFIG_SYS_TEXT_BASE 0xFE000000
2ae18241 WD	23
1c274c4e	24	#define CONFIG_PCI 1
1c274c4e KP	25
	26	/*
	27	* System Clock Setup
	28	*/
	29	#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
	30
	31	#ifndef CONFIG_SYS_CLK_FREQ
	32	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	33	#endif
	34
	35	/*
	36	* Hardware Reset Configuration Word
	37	*/
6d0f6bcf	38	#define CONFIG_SYS_HRCW_LOW (\
1c274c4e KP	39	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	40	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	41	HRCWL_VCO_1X2 \|\
	42	HRCWL_CSB_TO_CLKIN_2X1 \|\
	43	HRCWL_CORE_TO_CSB_2_5X1 \|\
	44	HRCWL_CE_PLL_VCO_DIV_2 \|\
	45	HRCWL_CE_PLL_DIV_1X1 \|\
	46	HRCWL_CE_TO_PLL_1X3)
	47
6d0f6bcf	48	#define CONFIG_SYS_HRCW_HIGH (\
1c274c4e KP	49	HRCWH_PCI_HOST \|\
	50	HRCWH_PCI1_ARBITER_ENABLE \|\
	51	HRCWH_CORE_ENABLE \|\
	52	HRCWH_FROM_0X00000100 \|\
	53	HRCWH_BOOTSEQ_DISABLE \|\
	54	HRCWH_SW_WATCHDOG_DISABLE \|\
	55	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	56	HRCWH_BIG_ENDIAN \|\
	57	HRCWH_LALE_NORMAL)
	58
	59	/*
	60	* System IO Config
	61	*/
6d0f6bcf	62	#define CONFIG_SYS_SICRL 0x00000000
1c274c4e	63
1c274c4e KP	64	/*
	65	* IMMR new address
	66	*/
6d0f6bcf	67	#define CONFIG_SYS_IMMR 0xE0000000
1c274c4e	68
5bbeea86 MB	69	/*
	70	* System performance
	71	*/
6d0f6bcf	72	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
4dde49d8 JH	73	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
	74	/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
	75	#define CONFIG_SYS_SPCR_OPT 1
5bbeea86	76
1c274c4e KP	77	/*
	78	* DDR Setup
	79	*/
4dde49d8 JH	80	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
4dde49d8 JH	81	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf	82	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
1c274c4e KP	83
	84	#undef CONFIG_SPD_EEPROM
	85	#if defined(CONFIG_SPD_EEPROM)
	86	/* Determine DDR configuration from I2C interface
	87	*/
	88	#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
	89	#else
	90	/* Manually set up DDR parameters
	91	*/
4dde49d8 JH	92	#define CONFIG_SYS_DDR_SIZE 64 /* MB */
4dde49d8 JH	93	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
4dde49d8 JH	94	\| CSCONFIG_ROW_BIT_13 \
4dde49d8 JH	95	\| CSCONFIG_COL_BIT_9)
5bbeea86	96	/* 0x80010101 */
4dde49d8 JH	97	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	98	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	99	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	100	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	101	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	102	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	103	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	104	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
fc549c87	105	/* 0x00220802 */
4dde49d8 JH	106	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	107	\| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	108	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	109	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	110	\| (3 << TIMING_CFG1_REFREC_SHIFT) \
	111	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	112	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	113	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
5bbeea86	114	/* 0x26253222 */
4dde49d8 JH	115	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	116	\| (31 << TIMING_CFG2_CPO_SHIFT) \
	117	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	118	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	119	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	120	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	121	\| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
5bbeea86	122	/* 0x1f9048c7 */
6d0f6bcf JCPV	123	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
6d0f6bcf JCPV	124	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
fc549c87	125	/* 0x02000000 */
4dde49d8 JH	126	#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
4dde49d8 JH	127	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
5bbeea86	128	/* 0x44480232 */
4dde49d8 JH	129	#define CONFIG_SYS_DDR_MODE2 0x8000c000
	130	#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
	131	\| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
fc549c87	132	/* 0x03200064 */
6d0f6bcf	133	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
4dde49d8	134	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
fc549c87	135	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
4dde49d8	136	\| SDRAM_CFG_32_BE)
fc549c87	137	/* 0x43080000 */
6d0f6bcf	138	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
1c274c4e KP	139	#endif
	140
	141	/*
	142	* Memory test
	143	*/
6d0f6bcf JCPV	144	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	145	#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
	146	#define CONFIG_SYS_MEMTEST_END 0x03f00000
1c274c4e KP	147
	148	/*
	149	* The reserved memory
	150	*/
14d0a02a	151	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
1c274c4e	152
6d0f6bcf JCPV	153	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	154	#define CONFIG_SYS_RAMBOOT
1c274c4e	155	#else
6d0f6bcf	156	#undef CONFIG_SYS_RAMBOOT
1c274c4e KP	157	#endif
1c274c4e KP	158
6d0f6bcf	159	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
4dde49d8	160	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
c8a90646	161	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
1c274c4e KP	162
	163	/*
	164	* Initial RAM Base Address Setup
	165	*/
6d0f6bcf	166	#define CONFIG_SYS_INIT_RAM_LOCK 1
4dde49d8 JH	167	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	168	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
	169	#define CONFIG_SYS_GBL_DATA_OFFSET \
	170	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
1c274c4e KP	171
	172	/*
	173	* Local Bus Configuration & Clock Setup
	174	*/
c7190f02 KP	175	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	176	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
6d0f6bcf	177	#define CONFIG_SYS_LBC_LBCR 0x00000000
1c274c4e KP	178
	179	/*
	180	* FLASH on the Local Bus
	181	*/
6d0f6bcf	182	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
00b1883a	183	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
4dde49d8	184	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
6d0f6bcf	185	#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
4dde49d8	186	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
1c274c4e	187
4dde49d8 JH	188	/* Window base at flash base */
4dde49d8 JH	189	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	190	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_32MB)
1c274c4e	191
4dde49d8	192	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
7d6a0982 JH	193	\| BR_PS_16 /* 16 bit port */ \
	194	\| BR_MS_GPCM /* MSEL = GPCM */ \
	195	\| BR_V) /* valid */
	196	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
	197	\| OR_GPCM_XAM \
	198	\| OR_GPCM_CSNT \
	199	\| OR_GPCM_ACS_DIV2 \
	200	\| OR_GPCM_XACS \
	201	\| OR_GPCM_SCY_15 \
	202	\| OR_GPCM_TRLX_SET \
	203	\| OR_GPCM_EHTR_SET \
	204	\| OR_GPCM_EAD)
	205	/* 0xFE006FF7 */
1c274c4e	206
4dde49d8 JH	207	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
4dde49d8 JH	208	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
1c274c4e	209
6d0f6bcf	210	#undef CONFIG_SYS_FLASH_CHECKSUM
1c274c4e	211
1c274c4e KP	212	/*
	213	* Serial Port
	214	*/
	215	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	216	#define CONFIG_SYS_NS16550
	217	#define CONFIG_SYS_NS16550_SERIAL
	218	#define CONFIG_SYS_NS16550_REG_SIZE 1
	219	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
1c274c4e	220
6d0f6bcf	221	#define CONFIG_SYS_BAUDRATE_TABLE \
4dde49d8	222	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
1c274c4e	223
6d0f6bcf JCPV	224	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	225	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
1c274c4e KP	226
1c274c4e KP	227	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
a059e90e	228	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
1c274c4e	229	/* Use the HUSH parser */
6d0f6bcf	230	#define CONFIG_SYS_HUSH_PARSER
1c274c4e KP	231
	232	/* pass open firmware flat tree */
	233	#define CONFIG_OF_LIBFDT 1
	234	#define CONFIG_OF_BOARD_SETUP 1
5b8bc606	235	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
1c274c4e KP	236
1c274c4e KP	237	/* I2C */
00f792e0 HS	238	#define CONFIG_SYS_I2C
	239	#define CONFIG_SYS_I2C_FSL
	240	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	241	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	242	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	243	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
1c274c4e KP	244
1c274c4e KP	245	/*
0fa7a1b4	246	* Config on-board EEPROM
1c274c4e	247	*/
6d0f6bcf JCPV	248	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	249	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	250	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	251	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
1c274c4e KP	252
	253	/*
	254	* General PCI
	255	* Addresses are mapped 1-1.
	256	*/
6d0f6bcf JCPV	257	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	258	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	259	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	260	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	261	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	262	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	263	#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
	264	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	265	#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
1c274c4e KP	266
1c274c4e KP	267	#ifdef CONFIG_PCI
842033e6	268	#define CONFIG_PCI_INDIRECT_BRIDGE
8f325cff	269	#define CONFIG_PCI_SKIP_HOST_BRIDGE
1c274c4e KP	270	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	271
	272	#undef CONFIG_EEPRO100
	273	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	274	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
1c274c4e KP	275
	276	#endif /* CONFIG_PCI */
	277
1c274c4e KP	278	/*
	279	* QE UEC ethernet configuration
	280	*/
	281	#define CONFIG_UEC_ETH
78b7a8ef	282	#define CONFIG_ETHPRIME "UEC0"
1c274c4e KP	283
	284	#define CONFIG_UEC_ETH1 /* ETH3 */
	285
	286	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	287	#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
	288	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
	289	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
	290	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	291	#define CONFIG_SYS_UEC1_PHY_ADDR 4
865ff856	292	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	293	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
1c274c4e KP	294	#endif
	295
	296	#define CONFIG_UEC_ETH2 /* ETH4 */
	297
	298	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	299	#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
	300	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
	301	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
	302	#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
	303	#define CONFIG_SYS_UEC2_PHY_ADDR 0
865ff856	304	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	305	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
1c274c4e KP	306	#endif
	307
	308	/*
	309	* Environment
	310	*/
6d0f6bcf	311	#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0	312	#define CONFIG_ENV_IS_IN_FLASH 1
4dde49d8 JH	313	#define CONFIG_ENV_ADDR \
4dde49d8 JH	314	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586 JCPV	315	#define CONFIG_ENV_SECT_SIZE 0x20000
0e8d1586 JCPV	316	#define CONFIG_ENV_SIZE 0x2000
1c274c4e	317	#else
4dde49d8	318	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725	319	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	320	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	321	#define CONFIG_ENV_SIZE 0x2000
1c274c4e KP	322	#endif
	323
	324	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	325	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
1c274c4e KP	326
	327	/*
	328	* BOOTP options
	329	*/
	330	#define CONFIG_BOOTP_BOOTFILESIZE
	331	#define CONFIG_BOOTP_BOOTPATH
	332	#define CONFIG_BOOTP_GATEWAY
	333	#define CONFIG_BOOTP_HOSTNAME
	334
	335	/*
	336	* Command line configuration.
	337	*/
1c274c4e KP	338	#define CONFIG_CMD_PING
1c274c4e KP	339	#define CONFIG_CMD_I2C
0fa7a1b4	340	#define CONFIG_CMD_EEPROM
1c274c4e KP	341	#define CONFIG_CMD_ASKENV
	342
	343	#if defined(CONFIG_PCI)
	344	#define CONFIG_CMD_PCI
	345	#endif
1c274c4e KP	346
	347	#undef CONFIG_WATCHDOG /* watchdog disabled */
	348
	349	/*
	350	* Miscellaneous configurable options
	351	*/
4dde49d8 JH	352	#define CONFIG_SYS_LONGHELP /* undef to save memory */
4dde49d8 JH	353	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
1c274c4e KP	354
1c274c4e KP	355	#if (CONFIG_CMD_KGDB)
6d0f6bcf	356	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
1c274c4e	357	#else
6d0f6bcf	358	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1c274c4e KP	359	#endif
1c274c4e KP	360
4dde49d8 JH	361	/* Print Buffer Size */
4dde49d8 JH	362	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
6d0f6bcf	363	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
4dde49d8 JH	364	/* Boot Argument Buffer Size */
4dde49d8 JH	365	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
1c274c4e KP	366
	367	/*
	368	* For booting Linux, the board info and command line data
9f530d59	369	* have to be in the first 256 MB of memory, since this is
1c274c4e KP	370	* the maximum mapped by the Linux kernel during initialization.
1c274c4e KP	371	*/
4dde49d8 JH	372	/* Initial Memory map for Linux */
4dde49d8 JH	373	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
1c274c4e KP	374
	375	/*
	376	* Core HID Setup
	377	*/
1a2e203b KP	378	#define CONFIG_SYS_HID0_INIT 0x000000000
	379	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	380	HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf	381	#define CONFIG_SYS_HID2 HID2_HBE
1c274c4e	382
1c274c4e KP	383	/*
	384	* MMU Setup
	385	*/
31d82672	386	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
1c274c4e KP	387
1c274c4e KP	388	/* DDR: cache cacheable */
4dde49d8	389	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	390	\| BATL_PP_RW \
4dde49d8 JH	391	\| BATL_MEMCOHERENCE)
	392	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	393	\| BATU_BL_256M \
	394	\| BATU_VS \
	395	\| BATU_VP)
6d0f6bcf JCPV	396	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
6d0f6bcf JCPV	397	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
1c274c4e KP	398
1c274c4e KP	399	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
4dde49d8	400	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
72cd4087	401	\| BATL_PP_RW \
4dde49d8 JH	402	\| BATL_CACHEINHIBIT \
	403	\| BATL_GUARDEDSTORAGE)
	404	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
	405	\| BATU_BL_4M \
	406	\| BATU_VS \
	407	\| BATU_VP)
6d0f6bcf JCPV	408	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
6d0f6bcf JCPV	409	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
1c274c4e KP	410
1c274c4e KP	411	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
4dde49d8	412	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
72cd4087	413	\| BATL_PP_RW \
4dde49d8 JH	414	\| BATL_MEMCOHERENCE)
	415	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
	416	\| BATU_BL_32M \
	417	\| BATU_VS \
	418	\| BATU_VP)
	419	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
72cd4087	420	\| BATL_PP_RW \
4dde49d8 JH	421	\| BATL_CACHEINHIBIT \
4dde49d8 JH	422	\| BATL_GUARDEDSTORAGE)
6d0f6bcf	423	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
1c274c4e	424
6d0f6bcf JCPV	425	#define CONFIG_SYS_IBAT3L (0)
	426	#define CONFIG_SYS_IBAT3U (0)
	427	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	428	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
1c274c4e KP	429
1c274c4e KP	430	/* Stack in dcache: cacheable, no memory coherence */
72cd4087	431	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
4dde49d8 JH	432	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
	433	\| BATU_BL_128K \
	434	\| BATU_VS \
	435	\| BATU_VP)
6d0f6bcf JCPV	436	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
6d0f6bcf JCPV	437	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
1c274c4e KP	438
	439	#ifdef CONFIG_PCI
	440	/* PCI MEM space: cacheable */
4dde49d8	441	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
72cd4087	442	\| BATL_PP_RW \
4dde49d8 JH	443	\| BATL_MEMCOHERENCE)
	444	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
	445	\| BATU_BL_256M \
	446	\| BATU_VS \
	447	\| BATU_VP)
6d0f6bcf JCPV	448	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
6d0f6bcf JCPV	449	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
1c274c4e	450	/* PCI MMIO space: cache-inhibit and guarded */
4dde49d8	451	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
72cd4087	452	\| BATL_PP_RW \
4dde49d8 JH	453	\| BATL_CACHEINHIBIT \
	454	\| BATL_GUARDEDSTORAGE)
	455	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
	456	\| BATU_BL_256M \
	457	\| BATU_VS \
	458	\| BATU_VP)
6d0f6bcf JCPV	459	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
6d0f6bcf JCPV	460	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
1c274c4e	461	#else
6d0f6bcf JCPV	462	#define CONFIG_SYS_IBAT5L (0)
	463	#define CONFIG_SYS_IBAT5U (0)
	464	#define CONFIG_SYS_IBAT6L (0)
	465	#define CONFIG_SYS_IBAT6U (0)
	466	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	467	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	468	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	469	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
1c274c4e KP	470	#endif
	471
	472	/* Nothing in BAT7 */
6d0f6bcf JCPV	473	#define CONFIG_SYS_IBAT7L (0)
	474	#define CONFIG_SYS_IBAT7U (0)
	475	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	476	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
1c274c4e	477
1c274c4e KP	478	#if (CONFIG_CMD_KGDB)
1c274c4e KP	479	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
1c274c4e KP	480	#endif
	481
	482	/*
	483	* Environment Configuration
	484	*/
	485	#define CONFIG_ENV_OVERWRITE
	486
4dde49d8 JH	487	#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
4dde49d8 JH	488	#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
1c274c4e	489
4dde49d8 JH	490	/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
	491	* (see CONFIG_SYS_I2C_EEPROM) */
	492	/* MAC address offset in I2C EEPROM */
	493	#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
5b2793a3	494
4dde49d8	495	#define CONFIG_NETDEV "eth1"
1c274c4e KP	496
1c274c4e KP	497	#define CONFIG_HOSTNAME mpc8323erdb
8b3637c6	498	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	499	#define CONFIG_BOOTFILE "uImage"
4dde49d8 JH	500	/* U-Boot image on TFTP server */
	501	#define CONFIG_UBOOTPATH "u-boot.bin"
	502	#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
	503	#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
1c274c4e	504
4dde49d8 JH	505	/* default location for tftp and bootm */
4dde49d8 JH	506	#define CONFIG_LOADADDR 800000
7fd0bea2	507	#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
1c274c4e KP	508	#define CONFIG_BAUDRATE 115200
1c274c4e KP	509
1c274c4e	510	#define CONFIG_EXTRA_ENV_SETTINGS \
4dde49d8 JH	511	"netdev=" CONFIG_NETDEV "\0" \
4dde49d8 JH	512	"uboot=" CONFIG_UBOOTPATH "\0" \
1c274c4e	513	"tftpflash=tftp $loadaddr $uboot;" \
5368c55d MV	514	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	515	" +$filesize; " \
	516	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	517	" +$filesize; " \
	518	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	519	" $filesize; " \
	520	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	521	" +$filesize; " \
	522	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	523	" $filesize\0" \
79f516bc	524	"fdtaddr=780000\0" \
4dde49d8	525	"fdtfile=" CONFIG_FDTFILE "\0" \
1c274c4e	526	"ramdiskaddr=1000000\0" \
4dde49d8	527	"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
1c274c4e KP	528	"console=ttyS0\0" \
1c274c4e KP	529	"setbootargs=setenv bootargs " \
4dde49d8	530	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
1c274c4e	531	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
4dde49d8 JH	532	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
4dde49d8 JH	533	"$netdev:off "\
1c274c4e KP	534	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
	535
	536	#define CONFIG_NFSBOOTCOMMAND \
	537	"setenv rootdev /dev/nfs;" \
	538	"run setbootargs;" \
	539	"run setipargs;" \
	540	"tftp $loadaddr $bootfile;" \
	541	"tftp $fdtaddr $fdtfile;" \
	542	"bootm $loadaddr - $fdtaddr"
	543
	544	#define CONFIG_RAMBOOTCOMMAND \
	545	"setenv rootdev /dev/ram;" \
	546	"run setbootargs;" \
	547	"tftp $ramdiskaddr $ramdiskfile;" \
	548	"tftp $loadaddr $bootfile;" \
	549	"tftp $fdtaddr $fdtfile;" \
	550	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	551
1c274c4e	552	#endif /* __CONFIG_H */