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1c274c4e KP |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License version 2 as published | |
6 | * by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
1c274c4e KP |
12 | /* |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
16 | #define CONFIG_QE 1 /* Has QE */ | |
0f898604 | 17 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
2c7920af | 18 | #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ |
1c274c4e | 19 | |
2ae18241 WD |
20 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
21 | ||
1c274c4e | 22 | #define CONFIG_PCI 1 |
1c274c4e KP |
23 | |
24 | /* | |
25 | * System Clock Setup | |
26 | */ | |
27 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
28 | ||
29 | #ifndef CONFIG_SYS_CLK_FREQ | |
30 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
31 | #endif | |
32 | ||
33 | /* | |
34 | * Hardware Reset Configuration Word | |
35 | */ | |
6d0f6bcf | 36 | #define CONFIG_SYS_HRCW_LOW (\ |
1c274c4e KP |
37 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
38 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
39 | HRCWL_VCO_1X2 |\ | |
40 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
41 | HRCWL_CORE_TO_CSB_2_5X1 |\ | |
42 | HRCWL_CE_PLL_VCO_DIV_2 |\ | |
43 | HRCWL_CE_PLL_DIV_1X1 |\ | |
44 | HRCWL_CE_TO_PLL_1X3) | |
45 | ||
6d0f6bcf | 46 | #define CONFIG_SYS_HRCW_HIGH (\ |
1c274c4e KP |
47 | HRCWH_PCI_HOST |\ |
48 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
49 | HRCWH_CORE_ENABLE |\ | |
50 | HRCWH_FROM_0X00000100 |\ | |
51 | HRCWH_BOOTSEQ_DISABLE |\ | |
52 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
53 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
54 | HRCWH_BIG_ENDIAN |\ | |
55 | HRCWH_LALE_NORMAL) | |
56 | ||
57 | /* | |
58 | * System IO Config | |
59 | */ | |
6d0f6bcf | 60 | #define CONFIG_SYS_SICRL 0x00000000 |
1c274c4e KP |
61 | |
62 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
63 | ||
64 | /* | |
65 | * IMMR new address | |
66 | */ | |
6d0f6bcf | 67 | #define CONFIG_SYS_IMMR 0xE0000000 |
1c274c4e | 68 | |
5bbeea86 MB |
69 | /* |
70 | * System performance | |
71 | */ | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
73 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
74 | #define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ | |
5bbeea86 | 75 | |
1c274c4e KP |
76 | /* |
77 | * DDR Setup | |
78 | */ | |
6d0f6bcf JCPV |
79 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
80 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
81 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
82 | #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ | |
1c274c4e KP |
83 | |
84 | #undef CONFIG_SPD_EEPROM | |
85 | #if defined(CONFIG_SPD_EEPROM) | |
86 | /* Determine DDR configuration from I2C interface | |
87 | */ | |
88 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ | |
89 | #else | |
90 | /* Manually set up DDR parameters | |
91 | */ | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_DDR_SIZE 64 /* MB */ |
93 | #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ | |
5bbeea86 | 94 | | CSCONFIG_ODT_WR_ACS \ |
fc549c87 | 95 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) |
5bbeea86 | 96 | /* 0x80010101 */ |
6d0f6bcf | 97 | #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ |
fc549c87 MB |
98 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ |
99 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
100 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
101 | | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
102 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
103 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
104 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
105 | /* 0x00220802 */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ |
5bbeea86 MB |
107 | | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ |
108 | | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
fc549c87 | 109 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ |
5bbeea86 MB |
110 | | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ |
111 | | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ | |
fc549c87 MB |
112 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ |
113 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
5bbeea86 | 114 | /* 0x26253222 */ |
6d0f6bcf | 115 | #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
5bbeea86 | 116 | | (31 << TIMING_CFG2_CPO_SHIFT ) \ |
fc549c87 MB |
117 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ |
118 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
119 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
120 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
5bbeea86 MB |
121 | | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) |
122 | /* 0x1f9048c7 */ | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
124 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
fc549c87 | 125 | /* 0x02000000 */ |
6d0f6bcf | 126 | #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ |
fc549c87 | 127 | | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) |
5bbeea86 | 128 | /* 0x44480232 */ |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 |
130 | #define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | |
fc549c87 MB |
131 | | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) |
132 | /* 0x03200064 */ | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 |
134 | #define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
fc549c87 MB |
135 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
136 | | SDRAM_CFG_32_BE ) | |
137 | /* 0x43080000 */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
1c274c4e KP |
139 | #endif |
140 | ||
141 | /* | |
142 | * Memory test | |
143 | */ | |
6d0f6bcf JCPV |
144 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
145 | #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ | |
146 | #define CONFIG_SYS_MEMTEST_END 0x03f00000 | |
1c274c4e KP |
147 | |
148 | /* | |
149 | * The reserved memory | |
150 | */ | |
14d0a02a | 151 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
1c274c4e | 152 | |
6d0f6bcf JCPV |
153 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
154 | #define CONFIG_SYS_RAMBOOT | |
1c274c4e | 155 | #else |
6d0f6bcf | 156 | #undef CONFIG_SYS_RAMBOOT |
1c274c4e KP |
157 | #endif |
158 | ||
6d0f6bcf | 159 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
4a9932a4 | 160 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
6d0f6bcf | 161 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
1c274c4e KP |
162 | |
163 | /* | |
164 | * Initial RAM Base Address Setup | |
165 | */ | |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
167 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 168 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
25ddd1fb | 169 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
1c274c4e KP |
170 | |
171 | /* | |
172 | * Local Bus Configuration & Clock Setup | |
173 | */ | |
c7190f02 KP |
174 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
175 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
6d0f6bcf | 176 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
1c274c4e KP |
177 | |
178 | /* | |
179 | * FLASH on the Local Bus | |
180 | */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 182 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
184 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ | |
185 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
1c274c4e | 186 | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ |
188 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
1c274c4e | 189 | |
6d0f6bcf | 190 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ |
1c274c4e KP |
191 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ |
192 | BR_V) /* valid */ | |
6d0f6bcf | 193 | #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ |
1c274c4e | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
196 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
1c274c4e | 197 | |
6d0f6bcf | 198 | #undef CONFIG_SYS_FLASH_CHECKSUM |
1c274c4e KP |
199 | |
200 | /* | |
201 | * SDRAM on the Local Bus | |
202 | */ | |
6d0f6bcf | 203 | #undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ |
1c274c4e | 204 | |
6d0f6bcf JCPV |
205 | #ifdef CONFIG_SYS_LB_SDRAM |
206 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ | |
207 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
1c274c4e | 208 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE |
210 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ | |
1c274c4e KP |
211 | |
212 | /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ | |
213 | /* | |
214 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 215 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
1c274c4e KP |
216 | * |
217 | * For BR2, need: | |
218 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
219 | * port size = 32-bits = BR2[19:20] = 11 | |
220 | * no parity checking = BR2[21:22] = 00 | |
221 | * SDRAM for MSEL = BR2[24:26] = 011 | |
222 | * Valid = BR[31] = 1 | |
223 | * | |
224 | * 0 4 8 12 16 20 24 28 | |
225 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
226 | * | |
6d0f6bcf | 227 | * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
1c274c4e KP |
228 | * the top 17 bits of BR2. |
229 | */ | |
230 | ||
6d0f6bcf | 231 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ |
1c274c4e KP |
232 | |
233 | /* | |
6d0f6bcf | 234 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
1c274c4e KP |
235 | * |
236 | * For OR2, need: | |
237 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
238 | * XAM, OR2[17:18] = 11 | |
239 | * 9 columns OR2[19-21] = 010 | |
240 | * 13 rows OR2[23-25] = 100 | |
241 | * EAD set for extra time OR[31] = 1 | |
242 | * | |
243 | * 0 4 8 12 16 20 24 28 | |
244 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
245 | */ | |
246 | ||
6d0f6bcf | 247 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
1c274c4e | 248 | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
250 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
1c274c4e | 251 | |
6d0f6bcf | 252 | #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 |
1c274c4e | 253 | |
1c274c4e KP |
254 | #endif |
255 | ||
256 | /* | |
257 | * Windows to access PIB via local bus | |
258 | */ | |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ |
260 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ | |
1c274c4e KP |
261 | |
262 | /* | |
263 | * Serial Port | |
264 | */ | |
265 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
266 | #define CONFIG_SYS_NS16550 |
267 | #define CONFIG_SYS_NS16550_SERIAL | |
268 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
269 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
1c274c4e | 270 | |
6d0f6bcf | 271 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
1c274c4e KP |
272 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
273 | ||
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
275 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
1c274c4e KP |
276 | |
277 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
a059e90e | 278 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
1c274c4e | 279 | /* Use the HUSH parser */ |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_HUSH_PARSER |
281 | #ifdef CONFIG_SYS_HUSH_PARSER | |
282 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
1c274c4e KP |
283 | #endif |
284 | ||
285 | /* pass open firmware flat tree */ | |
286 | #define CONFIG_OF_LIBFDT 1 | |
287 | #define CONFIG_OF_BOARD_SETUP 1 | |
5b8bc606 | 288 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
1c274c4e KP |
289 | |
290 | /* I2C */ | |
291 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
292 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
293 | #define CONFIG_FSL_I2C | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
295 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
296 | #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
297 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
1c274c4e KP |
298 | |
299 | /* | |
0fa7a1b4 | 300 | * Config on-board EEPROM |
1c274c4e | 301 | */ |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
303 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
304 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
305 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
1c274c4e KP |
306 | |
307 | /* | |
308 | * General PCI | |
309 | * Addresses are mapped 1-1. | |
310 | */ | |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
312 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
313 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
314 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
315 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
316 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
317 | #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 | |
318 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
319 | #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ | |
1c274c4e KP |
320 | |
321 | #ifdef CONFIG_PCI | |
8f325cff | 322 | #define CONFIG_PCI_SKIP_HOST_BRIDGE |
1c274c4e KP |
323 | #define CONFIG_NET_MULTI |
324 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
325 | ||
326 | #undef CONFIG_EEPRO100 | |
327 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 328 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
1c274c4e KP |
329 | |
330 | #endif /* CONFIG_PCI */ | |
331 | ||
332 | ||
333 | #ifndef CONFIG_NET_MULTI | |
334 | #define CONFIG_NET_MULTI 1 | |
335 | #endif | |
336 | ||
337 | /* | |
338 | * QE UEC ethernet configuration | |
339 | */ | |
340 | #define CONFIG_UEC_ETH | |
78b7a8ef | 341 | #define CONFIG_ETHPRIME "UEC0" |
1c274c4e KP |
342 | |
343 | #define CONFIG_UEC_ETH1 /* ETH3 */ | |
344 | ||
345 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ |
347 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 | |
348 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 | |
349 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
350 | #define CONFIG_SYS_UEC1_PHY_ADDR 4 | |
865ff856 | 351 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 352 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
1c274c4e KP |
353 | #endif |
354 | ||
355 | #define CONFIG_UEC_ETH2 /* ETH4 */ | |
356 | ||
357 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
359 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 | |
360 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 | |
361 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
362 | #define CONFIG_SYS_UEC2_PHY_ADDR 0 | |
865ff856 | 363 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 364 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
1c274c4e KP |
365 | #endif |
366 | ||
367 | /* | |
368 | * Environment | |
369 | */ | |
6d0f6bcf | 370 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 371 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 372 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
373 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
374 | #define CONFIG_ENV_SIZE 0x2000 | |
1c274c4e | 375 | #else |
6d0f6bcf | 376 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 377 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 378 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 379 | #define CONFIG_ENV_SIZE 0x2000 |
1c274c4e KP |
380 | #endif |
381 | ||
382 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 383 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
1c274c4e KP |
384 | |
385 | /* | |
386 | * BOOTP options | |
387 | */ | |
388 | #define CONFIG_BOOTP_BOOTFILESIZE | |
389 | #define CONFIG_BOOTP_BOOTPATH | |
390 | #define CONFIG_BOOTP_GATEWAY | |
391 | #define CONFIG_BOOTP_HOSTNAME | |
392 | ||
393 | /* | |
394 | * Command line configuration. | |
395 | */ | |
396 | #include <config_cmd_default.h> | |
397 | ||
398 | #define CONFIG_CMD_PING | |
399 | #define CONFIG_CMD_I2C | |
0fa7a1b4 | 400 | #define CONFIG_CMD_EEPROM |
1c274c4e KP |
401 | #define CONFIG_CMD_ASKENV |
402 | ||
403 | #if defined(CONFIG_PCI) | |
404 | #define CONFIG_CMD_PCI | |
405 | #endif | |
6d0f6bcf | 406 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 407 | #undef CONFIG_CMD_SAVEENV |
1c274c4e KP |
408 | #undef CONFIG_CMD_LOADS |
409 | #endif | |
410 | ||
411 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
412 | ||
413 | /* | |
414 | * Miscellaneous configurable options | |
415 | */ | |
6d0f6bcf JCPV |
416 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
417 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
418 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
1c274c4e KP |
419 | |
420 | #if (CONFIG_CMD_KGDB) | |
6d0f6bcf | 421 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
1c274c4e | 422 | #else |
6d0f6bcf | 423 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
1c274c4e KP |
424 | #endif |
425 | ||
6d0f6bcf JCPV |
426 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
427 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
428 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
429 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
1c274c4e KP |
430 | |
431 | /* | |
432 | * For booting Linux, the board info and command line data | |
9f530d59 | 433 | * have to be in the first 256 MB of memory, since this is |
1c274c4e KP |
434 | * the maximum mapped by the Linux kernel during initialization. |
435 | */ | |
9f530d59 | 436 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
1c274c4e KP |
437 | |
438 | /* | |
439 | * Core HID Setup | |
440 | */ | |
1a2e203b KP |
441 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
442 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
443 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 444 | #define CONFIG_SYS_HID2 HID2_HBE |
1c274c4e | 445 | |
1c274c4e KP |
446 | /* |
447 | * MMU Setup | |
448 | */ | |
31d82672 | 449 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
1c274c4e KP |
450 | |
451 | /* DDR: cache cacheable */ | |
6d0f6bcf JCPV |
452 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
453 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
454 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
455 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
1c274c4e KP |
456 | |
457 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
6d0f6bcf | 458 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ |
1c274c4e | 459 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
460 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
461 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
462 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
1c274c4e KP |
463 | |
464 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
6d0f6bcf JCPV |
465 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
466 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
467 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ | |
1c274c4e | 468 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf | 469 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
1c274c4e | 470 | |
6d0f6bcf JCPV |
471 | #define CONFIG_SYS_IBAT3L (0) |
472 | #define CONFIG_SYS_IBAT3U (0) | |
473 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
474 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
1c274c4e KP |
475 | |
476 | /* Stack in dcache: cacheable, no memory coherence */ | |
6d0f6bcf JCPV |
477 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) |
478 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
479 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
480 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
1c274c4e KP |
481 | |
482 | #ifdef CONFIG_PCI | |
483 | /* PCI MEM space: cacheable */ | |
6d0f6bcf JCPV |
484 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
485 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
486 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
487 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
1c274c4e | 488 | /* PCI MMIO space: cache-inhibit and guarded */ |
6d0f6bcf | 489 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ |
1c274c4e | 490 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
491 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
492 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
493 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
1c274c4e | 494 | #else |
6d0f6bcf JCPV |
495 | #define CONFIG_SYS_IBAT5L (0) |
496 | #define CONFIG_SYS_IBAT5U (0) | |
497 | #define CONFIG_SYS_IBAT6L (0) | |
498 | #define CONFIG_SYS_IBAT6U (0) | |
499 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
500 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
501 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
502 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
1c274c4e KP |
503 | #endif |
504 | ||
505 | /* Nothing in BAT7 */ | |
6d0f6bcf JCPV |
506 | #define CONFIG_SYS_IBAT7L (0) |
507 | #define CONFIG_SYS_IBAT7U (0) | |
508 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
509 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
1c274c4e | 510 | |
1c274c4e KP |
511 | #if (CONFIG_CMD_KGDB) |
512 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
513 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
514 | #endif | |
515 | ||
516 | /* | |
517 | * Environment Configuration | |
518 | */ | |
519 | #define CONFIG_ENV_OVERWRITE | |
520 | ||
977b5758 | 521 | #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ |
1c274c4e | 522 | #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ |
1c274c4e | 523 | |
6d0f6bcf JCPV |
524 | /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ |
525 | #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */ | |
5b2793a3 | 526 | |
1c274c4e KP |
527 | #define CONFIG_NETDEV eth1 |
528 | ||
529 | #define CONFIG_HOSTNAME mpc8323erdb | |
530 | #define CONFIG_ROOTPATH /nfsroot | |
531 | #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot | |
532 | #define CONFIG_BOOTFILE uImage | |
533 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
534 | #define CONFIG_FDTFILE mpc832x_rdb.dtb | |
535 | ||
79f516bc | 536 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
7fd0bea2 | 537 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
1c274c4e KP |
538 | #define CONFIG_BAUDRATE 115200 |
539 | ||
540 | #define XMK_STR(x) #x | |
541 | #define MK_STR(x) XMK_STR(x) | |
542 | ||
543 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
544 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
545 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
546 | "tftpflash=tftp $loadaddr $uboot;" \ | |
14d0a02a WD |
547 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
548 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
549 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
550 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
551 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
79f516bc | 552 | "fdtaddr=780000\0" \ |
1c274c4e KP |
553 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ |
554 | "ramdiskaddr=1000000\0" \ | |
555 | "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ | |
556 | "console=ttyS0\0" \ | |
557 | "setbootargs=setenv bootargs " \ | |
558 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
559 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
560 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
561 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" | |
562 | ||
563 | #define CONFIG_NFSBOOTCOMMAND \ | |
564 | "setenv rootdev /dev/nfs;" \ | |
565 | "run setbootargs;" \ | |
566 | "run setipargs;" \ | |
567 | "tftp $loadaddr $bootfile;" \ | |
568 | "tftp $fdtaddr $fdtfile;" \ | |
569 | "bootm $loadaddr - $fdtaddr" | |
570 | ||
571 | #define CONFIG_RAMBOOTCOMMAND \ | |
572 | "setenv rootdev /dev/ram;" \ | |
573 | "run setbootargs;" \ | |
574 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
575 | "tftp $loadaddr $bootfile;" \ | |
576 | "tftp $fdtaddr $fdtfile;" \ | |
577 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
578 | ||
579 | #undef MK_STR | |
580 | #undef XMK_STR | |
581 | ||
582 | #endif /* __CONFIG_H */ |