[thirdparty/u-boot.git] / include / configs / MPC8323ERDB.h

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <linux/stringify.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 family */

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRL		0x00000000

/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory */

#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
 */
#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
#else
/* Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE	64	/* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_9)
				/* 0x80010101 */
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (3 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x26253222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (31 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x1f9048c7 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
				/* 0x02000000 */
#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* 0x44480232 */
#define CONFIG_SYS_DDR_MODE2	0x8000c000
#define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_32_BE)
				/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#endif

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */


#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Config on-board EEPROM
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#define CONFIG_UEC_ETH1		/* ETH3 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	4
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

#define CONFIG_UEC_ETH2		/* ETH4 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR	0
#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
					/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
#define CONFIG_HAS_ETH1		/* add support for "eth1addr" */

/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 * (see CONFIG_SYS_I2C_EEPROM) */
					/* MAC address offset in I2C EEPROM */
#define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00

#define CONFIG_NETDEV		"eth1"

#define CONFIG_HOSTNAME		"mpc8323erdb"
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot.bin"
#define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		800000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0"					\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftp $loadaddr $uboot;"				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=780000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"					\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
								"$netdev:off "\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
1c274c4e KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License version 2 as published
	6	* by the Free Software Foundation.
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
1af3c7f4 SG	12	#include <linux/stringify.h>
1af3c7f4 SG	13
1c274c4e KP	14	/*
	15	* High Level Configuration Options
	16	*/
	17	#define CONFIG_E300 1 /* E300 family */
1c274c4e	18
1c274c4e KP	19	/*
	20	* System IO Config
	21	*/
6d0f6bcf	22	#define CONFIG_SYS_SICRL 0x00000000
1c274c4e	23
1c274c4e KP	24	/*
	25	* DDR Setup
	26	*/
8a81bfd2	27	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
1c274c4e KP	28
	29	#undef CONFIG_SPD_EEPROM
	30	#if defined(CONFIG_SPD_EEPROM)
	31	/* Determine DDR configuration from I2C interface
	32	*/
	33	#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
	34	#else
	35	/* Manually set up DDR parameters
	36	*/
4dde49d8 JH	37	#define CONFIG_SYS_DDR_SIZE 64 /* MB */
4dde49d8 JH	38	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
4dde49d8 JH	39	\| CSCONFIG_ROW_BIT_13 \
4dde49d8 JH	40	\| CSCONFIG_COL_BIT_9)
5bbeea86	41	/* 0x80010101 */
4dde49d8 JH	42	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	43	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	44	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	45	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	46	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	47	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	48	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	49	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
fc549c87	50	/* 0x00220802 */
4dde49d8 JH	51	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	52	\| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	53	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	54	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	55	\| (3 << TIMING_CFG1_REFREC_SHIFT) \
	56	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	57	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	58	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
5bbeea86	59	/* 0x26253222 */
4dde49d8 JH	60	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	61	\| (31 << TIMING_CFG2_CPO_SHIFT) \
	62	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	63	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	64	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	65	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	66	\| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
5bbeea86	67	/* 0x1f9048c7 */
6d0f6bcf JCPV	68	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
6d0f6bcf JCPV	69	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
fc549c87	70	/* 0x02000000 */
4dde49d8 JH	71	#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
4dde49d8 JH	72	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
5bbeea86	73	/* 0x44480232 */
4dde49d8 JH	74	#define CONFIG_SYS_DDR_MODE2 0x8000c000
	75	#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
	76	\| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
fc549c87	77	/* 0x03200064 */
6d0f6bcf	78	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
4dde49d8	79	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
fc549c87	80	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
4dde49d8	81	\| SDRAM_CFG_32_BE)
fc549c87	82	/* 0x43080000 */
6d0f6bcf	83	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
1c274c4e KP	84	#endif
	85
	86	/*
	87	* Memory test
	88	*/
6d0f6bcf	89	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
1c274c4e KP	90
	91	/*
	92	* The reserved memory
	93	*/
14d0a02a	94	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
1c274c4e	95
6d0f6bcf JCPV	96	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	97	#define CONFIG_SYS_RAMBOOT
1c274c4e	98	#else
6d0f6bcf	99	#undef CONFIG_SYS_RAMBOOT
1c274c4e KP	100	#endif
1c274c4e KP	101
6d0f6bcf	102	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170	103	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
c8a90646	104	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
1c274c4e KP	105
	106	/*
	107	* Initial RAM Base Address Setup
	108	*/
6d0f6bcf	109	#define CONFIG_SYS_INIT_RAM_LOCK 1
4dde49d8 JH	110	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	111	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
	112	#define CONFIG_SYS_GBL_DATA_OFFSET \
	113	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
1c274c4e	114
1c274c4e KP	115	/*
	116	* FLASH on the Local Bus
	117	*/
4dde49d8	118	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
6d0f6bcf	119	#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
1c274c4e	120
1c274c4e	121
1c274c4e	122
4dde49d8 JH	123	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
4dde49d8 JH	124	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
1c274c4e	125
6d0f6bcf	126	#undef CONFIG_SYS_FLASH_CHECKSUM
1c274c4e	127
1c274c4e KP	128	/*
	129	* Serial Port
	130	*/
6d0f6bcf JCPV	131	#define CONFIG_SYS_NS16550_SERIAL
	132	#define CONFIG_SYS_NS16550_REG_SIZE 1
	133	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
1c274c4e	134
6d0f6bcf	135	#define CONFIG_SYS_BAUDRATE_TABLE \
4dde49d8	136	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
1c274c4e	137
6d0f6bcf JCPV	138	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	139	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
1c274c4e	140
1c274c4e	141	/* I2C */
00f792e0 HS	142	#define CONFIG_SYS_I2C
	143	#define CONFIG_SYS_I2C_FSL
	144	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	145	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	146	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	147	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
1c274c4e KP	148
1c274c4e KP	149	/*
0fa7a1b4	150	* Config on-board EEPROM
1c274c4e	151	*/
6d0f6bcf JCPV	152	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	153	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	154	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	155	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
1c274c4e KP	156
	157	/*
	158	* General PCI
	159	* Addresses are mapped 1-1.
	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	162	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	163	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	164	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	165	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	166	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	167	#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
	168	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	169	#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
1c274c4e KP	170
1c274c4e KP	171	#ifdef CONFIG_PCI
842033e6	172	#define CONFIG_PCI_INDIRECT_BRIDGE
8f325cff	173	#define CONFIG_PCI_SKIP_HOST_BRIDGE
1c274c4e KP	174
	175	#undef CONFIG_EEPRO100
	176	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	177	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
1c274c4e KP	178
	179	#endif /* CONFIG_PCI */
	180
1c274c4e KP	181	/*
	182	* QE UEC ethernet configuration
	183	*/
	184	#define CONFIG_UEC_ETH
78b7a8ef	185	#define CONFIG_ETHPRIME "UEC0"
1c274c4e KP	186
	187	#define CONFIG_UEC_ETH1 /* ETH3 */
	188
	189	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	190	#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
	191	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
	192	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
	193	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	194	#define CONFIG_SYS_UEC1_PHY_ADDR 4
865ff856	195	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	196	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
1c274c4e KP	197	#endif
	198
	199	#define CONFIG_UEC_ETH2 /* ETH4 */
	200
	201	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	202	#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
	203	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
	204	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
	205	#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
	206	#define CONFIG_SYS_UEC2_PHY_ADDR 0
865ff856	207	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	208	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
1c274c4e KP	209	#endif
	210
	211	/*
	212	* Environment
	213	*/
1c274c4e KP	214
1c274c4e KP	215	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	216	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
1c274c4e KP	217
	218	/*
	219	* BOOTP options
	220	*/
	221	#define CONFIG_BOOTP_BOOTFILESIZE
1c274c4e KP	222
	223	/*
	224	* Command line configuration.
	225	*/
1c274c4e	226
1c274c4e KP	227	#undef CONFIG_WATCHDOG /* watchdog disabled */
	228
	229	/*
	230	* Miscellaneous configurable options
	231	*/
4dde49d8	232	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
1c274c4e	233
1c274c4e KP	234	/*
1c274c4e KP	235	* For booting Linux, the board info and command line data
9f530d59	236	* have to be in the first 256 MB of memory, since this is
1c274c4e KP	237	* the maximum mapped by the Linux kernel during initialization.
1c274c4e KP	238	*/
4dde49d8 JH	239	/* Initial Memory map for Linux */
4dde49d8 JH	240	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	241	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
1c274c4e	242
1c274c4e KP	243	#if (CONFIG_CMD_KGDB)
1c274c4e KP	244	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
1c274c4e KP	245	#endif
	246
	247	/*
	248	* Environment Configuration
	249	*/
	250	#define CONFIG_ENV_OVERWRITE
	251
4dde49d8 JH	252	#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
4dde49d8 JH	253	#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
1c274c4e	254
4dde49d8 JH	255	/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
	256	* (see CONFIG_SYS_I2C_EEPROM) */
	257	/* MAC address offset in I2C EEPROM */
	258	#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
5b2793a3	259
4dde49d8	260	#define CONFIG_NETDEV "eth1"
1c274c4e	261
5bc0543d	262	#define CONFIG_HOSTNAME "mpc8323erdb"
8b3637c6	263	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	264	#define CONFIG_BOOTFILE "uImage"
4dde49d8 JH	265	/* U-Boot image on TFTP server */
	266	#define CONFIG_UBOOTPATH "u-boot.bin"
	267	#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
	268	#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
1c274c4e	269
4dde49d8 JH	270	/* default location for tftp and bootm */
4dde49d8 JH	271	#define CONFIG_LOADADDR 800000
1c274c4e	272
1c274c4e	273	#define CONFIG_EXTRA_ENV_SETTINGS \
4dde49d8 JH	274	"netdev=" CONFIG_NETDEV "\0" \
4dde49d8 JH	275	"uboot=" CONFIG_UBOOTPATH "\0" \
1c274c4e	276	"tftpflash=tftp $loadaddr $uboot;" \
5368c55d MV	277	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	278	" +$filesize; " \
	279	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	280	" +$filesize; " \
	281	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	282	" $filesize; " \
	283	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	284	" +$filesize; " \
	285	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	286	" $filesize\0" \
79f516bc	287	"fdtaddr=780000\0" \
4dde49d8	288	"fdtfile=" CONFIG_FDTFILE "\0" \
1c274c4e	289	"ramdiskaddr=1000000\0" \
4dde49d8	290	"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
1c274c4e KP	291	"console=ttyS0\0" \
1c274c4e KP	292	"setbootargs=setenv bootargs " \
4dde49d8	293	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
1c274c4e	294	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
4dde49d8 JH	295	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
4dde49d8 JH	296	"$netdev:off "\
1c274c4e KP	297	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
	298
	299	#define CONFIG_NFSBOOTCOMMAND \
	300	"setenv rootdev /dev/nfs;" \
	301	"run setbootargs;" \
	302	"run setipargs;" \
	303	"tftp $loadaddr $bootfile;" \
	304	"tftp $fdtaddr $fdtfile;" \
	305	"bootm $loadaddr - $fdtaddr"
	306
	307	#define CONFIG_RAMBOOTCOMMAND \
	308	"setenv rootdev /dev/ram;" \
	309	"run setbootargs;" \
	310	"tftp $ramdiskaddr $ramdiskfile;" \
	311	"tftp $loadaddr $bootfile;" \
	312	"tftp $fdtaddr $fdtfile;" \
	313	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	314
1c274c4e	315	#endif /* __CONFIG_H */