projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 1c274c4e KP |
1 | /* |
| 2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms of the GNU General Public License version 2 as published | |
| 6 | * by the Free Software Foundation. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __CONFIG_H | |
| 10 | #define __CONFIG_H | |
| 11 | ||
| 1c274c4e KP |
12 | /* |
| 13 | * High Level Configuration Options | |
| 14 | */ | |
| 15 | #define CONFIG_E300 1 /* E300 family */ | |
| 16 | #define CONFIG_QE 1 /* Has QE */ | |
| 17 | #define CONFIG_MPC83XX 1 /* MPC83xx family */ | |
| 18 | #define CONFIG_MPC832X 1 /* MPC832x CPU specific */ | |
| 19 | ||
| 20 | #define CONFIG_PCI 1 | |
| 21 | #define CONFIG_83XX_GENERIC_PCI 1 | |
| 22 | ||
| 23 | /* | |
| 24 | * System Clock Setup | |
| 25 | */ | |
| 26 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
| 27 | ||
| 28 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 29 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
| 30 | #endif | |
| 31 | ||
| 32 | /* | |
| 33 | * Hardware Reset Configuration Word | |
| 34 | */ | |
| 6d0f6bcf | 35 | #define CONFIG_SYS_HRCW_LOW (\ |
| 1c274c4e KP |
36 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 37 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
| 38 | HRCWL_VCO_1X2 |\ | |
| 39 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
| 40 | HRCWL_CORE_TO_CSB_2_5X1 |\ | |
| 41 | HRCWL_CE_PLL_VCO_DIV_2 |\ | |
| 42 | HRCWL_CE_PLL_DIV_1X1 |\ | |
| 43 | HRCWL_CE_TO_PLL_1X3) | |
| 44 | ||
| 6d0f6bcf | 45 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 1c274c4e KP |
46 | HRCWH_PCI_HOST |\ |
| 47 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 48 | HRCWH_CORE_ENABLE |\ | |
| 49 | HRCWH_FROM_0X00000100 |\ | |
| 50 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 51 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 52 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 53 | HRCWH_BIG_ENDIAN |\ | |
| 54 | HRCWH_LALE_NORMAL) | |
| 55 | ||
| 56 | /* | |
| 57 | * System IO Config | |
| 58 | */ | |
| 6d0f6bcf | 59 | #define CONFIG_SYS_SICRL 0x00000000 |
| 1c274c4e KP |
60 | |
| 61 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
| 62 | ||
| 63 | /* | |
| 64 | * IMMR new address | |
| 65 | */ | |
| 6d0f6bcf | 66 | #define CONFIG_SYS_IMMR 0xE0000000 |
| 1c274c4e | 67 | |
| 5bbeea86 MB |
68 | /* |
| 69 | * System performance | |
| 70 | */ | |
| 6d0f6bcf JCPV |
71 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
| 72 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
| 73 | #define CONFIG_SYS_SPCR_OPT 1 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ | |
| 5bbeea86 | 74 | |
| 1c274c4e KP |
75 | /* |
| 76 | * DDR Setup | |
| 77 | */ | |
| 6d0f6bcf JCPV |
78 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
| 79 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 80 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 81 | #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ | |
| 1c274c4e KP |
82 | |
| 83 | #undef CONFIG_SPD_EEPROM | |
| 84 | #if defined(CONFIG_SPD_EEPROM) | |
| 85 | /* Determine DDR configuration from I2C interface | |
| 86 | */ | |
| 87 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ | |
| 88 | #else | |
| 89 | /* Manually set up DDR parameters | |
| 90 | */ | |
| 6d0f6bcf JCPV |
91 | #define CONFIG_SYS_DDR_SIZE 64 /* MB */ |
| 92 | #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ | |
| 5bbeea86 | 93 | | CSCONFIG_ODT_WR_ACS \ |
| fc549c87 | 94 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) |
| 5bbeea86 | 95 | /* 0x80010101 */ |
| 6d0f6bcf | 96 | #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ |
| fc549c87 MB |
97 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ |
| 98 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
| 99 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
| 100 | | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
| 101 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
| 102 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
| 103 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
| 104 | /* 0x00220802 */ | |
| 6d0f6bcf | 105 | #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ |
| 5bbeea86 MB |
106 | | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ |
| 107 | | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
| fc549c87 | 108 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ |
| 5bbeea86 MB |
109 | | ( 3 << TIMING_CFG1_REFREC_SHIFT ) \ |
| 110 | | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ | |
| fc549c87 MB |
111 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ |
| 112 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
| 5bbeea86 | 113 | /* 0x26253222 */ |
| 6d0f6bcf | 114 | #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
| 5bbeea86 | 115 | | (31 << TIMING_CFG2_CPO_SHIFT ) \ |
| fc549c87 MB |
116 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ |
| 117 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
| 118 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
| 119 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
| 5bbeea86 MB |
120 | | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) |
| 121 | /* 0x1f9048c7 */ | |
| 6d0f6bcf JCPV |
122 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 123 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
| fc549c87 | 124 | /* 0x02000000 */ |
| 6d0f6bcf | 125 | #define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ |
| fc549c87 | 126 | | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) |
| 5bbeea86 | 127 | /* 0x44480232 */ |
| 6d0f6bcf JCPV |
128 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 |
| 129 | #define CONFIG_SYS_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | |
| fc549c87 MB |
130 | | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) |
| 131 | /* 0x03200064 */ | |
| 6d0f6bcf JCPV |
132 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 |
| 133 | #define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
| fc549c87 MB |
134 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
| 135 | | SDRAM_CFG_32_BE ) | |
| 136 | /* 0x43080000 */ | |
| 6d0f6bcf | 137 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
| 1c274c4e KP |
138 | #endif |
| 139 | ||
| 140 | /* | |
| 141 | * Memory test | |
| 142 | */ | |
| 6d0f6bcf JCPV |
143 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 144 | #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ | |
| 145 | #define CONFIG_SYS_MEMTEST_END 0x03f00000 | |
| 1c274c4e KP |
146 | |
| 147 | /* | |
| 148 | * The reserved memory | |
| 149 | */ | |
| 6d0f6bcf | 150 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 1c274c4e | 151 | |
| 6d0f6bcf JCPV |
152 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 153 | #define CONFIG_SYS_RAMBOOT | |
| 1c274c4e | 154 | #else |
| 6d0f6bcf | 155 | #undef CONFIG_SYS_RAMBOOT |
| 1c274c4e KP |
156 | #endif |
| 157 | ||
| 6d0f6bcf JCPV |
158 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
| 159 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 160 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 1c274c4e KP |
161 | |
| 162 | /* | |
| 163 | * Initial RAM Base Address Setup | |
| 164 | */ | |
| 6d0f6bcf JCPV |
165 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 166 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
| 167 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
| 168 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
| 169 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 1c274c4e KP |
170 | |
| 171 | /* | |
| 172 | * Local Bus Configuration & Clock Setup | |
| 173 | */ | |
| 6d0f6bcf JCPV |
174 | #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) |
| 175 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
| 1c274c4e KP |
176 | |
| 177 | /* | |
| 178 | * FLASH on the Local Bus | |
| 179 | */ | |
| 6d0f6bcf | 180 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 00b1883a | 181 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| 6d0f6bcf JCPV |
182 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
| 183 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ | |
| 184 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
| 1c274c4e | 185 | |
| 6d0f6bcf JCPV |
186 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ |
| 187 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
| 1c274c4e | 188 | |
| 6d0f6bcf | 189 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ |
| 1c274c4e KP |
190 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ |
| 191 | BR_V) /* valid */ | |
| 6d0f6bcf | 192 | #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ |
| 1c274c4e | 193 | |
| 6d0f6bcf JCPV |
194 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 195 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
| 1c274c4e | 196 | |
| 6d0f6bcf | 197 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 1c274c4e KP |
198 | |
| 199 | /* | |
| 200 | * SDRAM on the Local Bus | |
| 201 | */ | |
| 6d0f6bcf | 202 | #undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ |
| 1c274c4e | 203 | |
| 6d0f6bcf JCPV |
204 | #ifdef CONFIG_SYS_LB_SDRAM |
| 205 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ | |
| 206 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
| 1c274c4e | 207 | |
| 6d0f6bcf JCPV |
208 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE |
| 209 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ | |
| 1c274c4e KP |
210 | |
| 211 | /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ | |
| 212 | /* | |
| 213 | * Base Register 2 and Option Register 2 configure SDRAM. | |
| 6d0f6bcf | 214 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| 1c274c4e KP |
215 | * |
| 216 | * For BR2, need: | |
| 217 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 218 | * port size = 32-bits = BR2[19:20] = 11 | |
| 219 | * no parity checking = BR2[21:22] = 00 | |
| 220 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 221 | * Valid = BR[31] = 1 | |
| 222 | * | |
| 223 | * 0 4 8 12 16 20 24 28 | |
| 224 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
| 225 | * | |
| 6d0f6bcf | 226 | * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
| 1c274c4e KP |
227 | * the top 17 bits of BR2. |
| 228 | */ | |
| 229 | ||
| 6d0f6bcf | 230 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ |
| 1c274c4e KP |
231 | |
| 232 | /* | |
| 6d0f6bcf | 233 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 1c274c4e KP |
234 | * |
| 235 | * For OR2, need: | |
| 236 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
| 237 | * XAM, OR2[17:18] = 11 | |
| 238 | * 9 columns OR2[19-21] = 010 | |
| 239 | * 13 rows OR2[23-25] = 100 | |
| 240 | * EAD set for extra time OR[31] = 1 | |
| 241 | * | |
| 242 | * 0 4 8 12 16 20 24 28 | |
| 243 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
| 244 | */ | |
| 245 | ||
| 6d0f6bcf | 246 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
| 1c274c4e | 247 | |
| 6d0f6bcf JCPV |
248 | #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
| 249 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
| 1c274c4e KP |
250 | |
| 251 | /* | |
| 252 | * LSDMR masks | |
| 253 | */ | |
| 6d0f6bcf JCPV |
254 | #define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
| 255 | #define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
| 256 | #define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
| 257 | #define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) | |
| 258 | #define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
| 259 | #define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) | |
| 260 | #define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
| 261 | #define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) | |
| 1c274c4e | 262 | |
| 6d0f6bcf | 263 | #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 |
| 1c274c4e KP |
264 | |
| 265 | /* | |
| 266 | * SDRAM Controller configuration sequence. | |
| 267 | */ | |
| 6d0f6bcf JCPV |
268 | #define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \ |
| 269 | | CONFIG_SYS_LBC_LSDMR_OP_PCHALL) | |
| 270 | #define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \ | |
| 271 | | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) | |
| 272 | #define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \ | |
| 273 | | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) | |
| 274 | #define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \ | |
| 275 | | CONFIG_SYS_LBC_LSDMR_OP_MRW) | |
| 276 | #define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \ | |
| 277 | | CONFIG_SYS_LBC_LSDMR_OP_NORMAL) | |
| 1c274c4e KP |
278 | |
| 279 | #endif | |
| 280 | ||
| 281 | /* | |
| 282 | * Windows to access PIB via local bus | |
| 283 | */ | |
| 6d0f6bcf JCPV |
284 | #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ |
| 285 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ | |
| 1c274c4e KP |
286 | |
| 287 | /* | |
| 288 | * Serial Port | |
| 289 | */ | |
| 290 | #define CONFIG_CONS_INDEX 1 | |
| 291 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 6d0f6bcf JCPV |
292 | #define CONFIG_SYS_NS16550 |
| 293 | #define CONFIG_SYS_NS16550_SERIAL | |
| 294 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 295 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 1c274c4e | 296 | |
| 6d0f6bcf | 297 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 1c274c4e KP |
298 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 299 | ||
| 6d0f6bcf JCPV |
300 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 301 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
| 1c274c4e KP |
302 | |
| 303 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 304 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
305 | #define CONFIG_SYS_HUSH_PARSER |
| 306 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 307 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 1c274c4e KP |
308 | #endif |
| 309 | ||
| 310 | /* pass open firmware flat tree */ | |
| 311 | #define CONFIG_OF_LIBFDT 1 | |
| 312 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 5b8bc606 | 313 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 1c274c4e KP |
314 | |
| 315 | /* I2C */ | |
| 316 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 317 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 318 | #define CONFIG_FSL_I2C | |
| 6d0f6bcf JCPV |
319 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 320 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 321 | #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
| 322 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 1c274c4e KP |
323 | |
| 324 | /* | |
| 0fa7a1b4 | 325 | * Config on-board EEPROM |
| 1c274c4e | 326 | */ |
| 6d0f6bcf JCPV |
327 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
| 328 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 329 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
| 330 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 1c274c4e KP |
331 | |
| 332 | /* | |
| 333 | * General PCI | |
| 334 | * Addresses are mapped 1-1. | |
| 335 | */ | |
| 6d0f6bcf JCPV |
336 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 337 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 338 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 339 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 340 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 341 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 342 | #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 | |
| 343 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
| 344 | #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ | |
| 1c274c4e KP |
345 | |
| 346 | #ifdef CONFIG_PCI | |
| 8f325cff | 347 | #define CONFIG_PCI_SKIP_HOST_BRIDGE |
| 1c274c4e KP |
348 | #define CONFIG_NET_MULTI |
| 349 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 350 | ||
| 351 | #undef CONFIG_EEPRO100 | |
| 352 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 6d0f6bcf | 353 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
| 1c274c4e KP |
354 | |
| 355 | #endif /* CONFIG_PCI */ | |
| 356 | ||
| 357 | ||
| 358 | #ifndef CONFIG_NET_MULTI | |
| 359 | #define CONFIG_NET_MULTI 1 | |
| 360 | #endif | |
| 361 | ||
| 362 | /* | |
| 363 | * QE UEC ethernet configuration | |
| 364 | */ | |
| 365 | #define CONFIG_UEC_ETH | |
| 711a7946 | 366 | #define CONFIG_ETHPRIME "FSL UEC0" |
| 1c274c4e KP |
367 | |
| 368 | #define CONFIG_UEC_ETH1 /* ETH3 */ | |
| 369 | ||
| 370 | #ifdef CONFIG_UEC_ETH1 | |
| 6d0f6bcf JCPV |
371 | #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ |
| 372 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 | |
| 373 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 | |
| 374 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
| 375 | #define CONFIG_SYS_UEC1_PHY_ADDR 4 | |
| 376 | #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_MII | |
| 1c274c4e KP |
377 | #endif |
| 378 | ||
| 379 | #define CONFIG_UEC_ETH2 /* ETH4 */ | |
| 380 | ||
| 381 | #ifdef CONFIG_UEC_ETH2 | |
| 6d0f6bcf JCPV |
382 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
| 383 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 | |
| 384 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 | |
| 385 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
| 386 | #define CONFIG_SYS_UEC2_PHY_ADDR 0 | |
| 387 | #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_MII | |
| 1c274c4e KP |
388 | #endif |
| 389 | ||
| 390 | /* | |
| 391 | * Environment | |
| 392 | */ | |
| 6d0f6bcf | 393 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 394 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 395 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 0e8d1586 JCPV |
396 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 397 | #define CONFIG_ENV_SIZE 0x2000 | |
| 1c274c4e | 398 | #else |
| 6d0f6bcf | 399 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
| 93f6d725 | 400 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 6d0f6bcf | 401 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 0e8d1586 | 402 | #define CONFIG_ENV_SIZE 0x2000 |
| 1c274c4e KP |
403 | #endif |
| 404 | ||
| 405 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 406 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 1c274c4e KP |
407 | |
| 408 | /* | |
| 409 | * BOOTP options | |
| 410 | */ | |
| 411 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 412 | #define CONFIG_BOOTP_BOOTPATH | |
| 413 | #define CONFIG_BOOTP_GATEWAY | |
| 414 | #define CONFIG_BOOTP_HOSTNAME | |
| 415 | ||
| 416 | /* | |
| 417 | * Command line configuration. | |
| 418 | */ | |
| 419 | #include <config_cmd_default.h> | |
| 420 | ||
| 421 | #define CONFIG_CMD_PING | |
| 422 | #define CONFIG_CMD_I2C | |
| 0fa7a1b4 | 423 | #define CONFIG_CMD_EEPROM |
| 1c274c4e KP |
424 | #define CONFIG_CMD_ASKENV |
| 425 | ||
| 426 | #if defined(CONFIG_PCI) | |
| 427 | #define CONFIG_CMD_PCI | |
| 428 | #endif | |
| 6d0f6bcf | 429 | #if defined(CONFIG_SYS_RAMBOOT) |
| 1c274c4e KP |
430 | #undef CONFIG_CMD_ENV |
| 431 | #undef CONFIG_CMD_LOADS | |
| 432 | #endif | |
| 433 | ||
| 434 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 435 | ||
| 436 | /* | |
| 437 | * Miscellaneous configurable options | |
| 438 | */ | |
| 6d0f6bcf JCPV |
439 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 440 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 441 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 1c274c4e KP |
442 | |
| 443 | #if (CONFIG_CMD_KGDB) | |
| 6d0f6bcf | 444 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 1c274c4e | 445 | #else |
| 6d0f6bcf | 446 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 1c274c4e KP |
447 | #endif |
| 448 | ||
| 6d0f6bcf JCPV |
449 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 450 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 451 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 452 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 1c274c4e KP |
453 | |
| 454 | /* | |
| 455 | * For booting Linux, the board info and command line data | |
| 456 | * have to be in the first 8 MB of memory, since this is | |
| 457 | * the maximum mapped by the Linux kernel during initialization. | |
| 458 | */ | |
| 6d0f6bcf | 459 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 1c274c4e KP |
460 | |
| 461 | /* | |
| 462 | * Core HID Setup | |
| 463 | */ | |
| 6d0f6bcf JCPV |
464 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 465 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
| 466 | #define CONFIG_SYS_HID2 HID2_HBE | |
| 1c274c4e | 467 | |
| 1c274c4e KP |
468 | /* |
| 469 | * MMU Setup | |
| 470 | */ | |
| 31d82672 | 471 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 1c274c4e KP |
472 | |
| 473 | /* DDR: cache cacheable */ | |
| 6d0f6bcf JCPV |
474 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 475 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 476 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 477 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 1c274c4e KP |
478 | |
| 479 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
| 6d0f6bcf | 480 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ |
| 1c274c4e | 481 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
482 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
| 483 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 484 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 1c274c4e KP |
485 | |
| 486 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
| 6d0f6bcf JCPV |
487 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 488 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 489 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ | |
| 1c274c4e | 490 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf | 491 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
| 1c274c4e | 492 | |
| 6d0f6bcf JCPV |
493 | #define CONFIG_SYS_IBAT3L (0) |
| 494 | #define CONFIG_SYS_IBAT3U (0) | |
| 495 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 496 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 1c274c4e KP |
497 | |
| 498 | /* Stack in dcache: cacheable, no memory coherence */ | |
| 6d0f6bcf JCPV |
499 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) |
| 500 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 501 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 502 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 1c274c4e KP |
503 | |
| 504 | #ifdef CONFIG_PCI | |
| 505 | /* PCI MEM space: cacheable */ | |
| 6d0f6bcf JCPV |
506 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 507 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 508 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 509 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 1c274c4e | 510 | /* PCI MMIO space: cache-inhibit and guarded */ |
| 6d0f6bcf | 511 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ |
| 1c274c4e | 512 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
513 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
| 514 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 515 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 1c274c4e | 516 | #else |
| 6d0f6bcf JCPV |
517 | #define CONFIG_SYS_IBAT5L (0) |
| 518 | #define CONFIG_SYS_IBAT5U (0) | |
| 519 | #define CONFIG_SYS_IBAT6L (0) | |
| 520 | #define CONFIG_SYS_IBAT6U (0) | |
| 521 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 522 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 523 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 524 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 1c274c4e KP |
525 | #endif |
| 526 | ||
| 527 | /* Nothing in BAT7 */ | |
| 6d0f6bcf JCPV |
528 | #define CONFIG_SYS_IBAT7L (0) |
| 529 | #define CONFIG_SYS_IBAT7U (0) | |
| 530 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 531 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 1c274c4e KP |
532 | |
| 533 | /* | |
| 534 | * Internal Definitions | |
| 535 | * | |
| 536 | * Boot Flags | |
| 537 | */ | |
| 538 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 539 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 540 | ||
| 541 | #if (CONFIG_CMD_KGDB) | |
| 542 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
| 543 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 544 | #endif | |
| 545 | ||
| 546 | /* | |
| 547 | * Environment Configuration | |
| 548 | */ | |
| 549 | #define CONFIG_ENV_OVERWRITE | |
| 550 | ||
| 977b5758 | 551 | #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ |
| 1c274c4e KP |
552 | #define CONFIG_ETHADDR 00:04:9f:ef:03:01 |
| 553 | #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ | |
| 554 | #define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 | |
| 555 | ||
| 6d0f6bcf JCPV |
556 | /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ |
| 557 | #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 /* MAC address offset in I2C EEPROM */ | |
| 5b2793a3 | 558 | |
| 1c274c4e KP |
559 | #define CONFIG_IPADDR 10.0.0.2 |
| 560 | #define CONFIG_SERVERIP 10.0.0.1 | |
| 561 | #define CONFIG_GATEWAYIP 10.0.0.1 | |
| 562 | #define CONFIG_NETMASK 255.0.0.0 | |
| 563 | #define CONFIG_NETDEV eth1 | |
| 564 | ||
| 565 | #define CONFIG_HOSTNAME mpc8323erdb | |
| 566 | #define CONFIG_ROOTPATH /nfsroot | |
| 567 | #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot | |
| 568 | #define CONFIG_BOOTFILE uImage | |
| 569 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
| 570 | #define CONFIG_FDTFILE mpc832x_rdb.dtb | |
| 571 | ||
| b2115757 | 572 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
| 7fd0bea2 | 573 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
| 1c274c4e KP |
574 | #define CONFIG_BAUDRATE 115200 |
| 575 | ||
| 576 | #define XMK_STR(x) #x | |
| 577 | #define MK_STR(x) XMK_STR(x) | |
| 578 | ||
| 579 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 580 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
| 581 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 582 | "tftpflash=tftp $loadaddr $uboot;" \ | |
| 583 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 584 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 585 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 586 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 587 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 588 | "fdtaddr=400000\0" \ | |
| 589 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ | |
| 590 | "ramdiskaddr=1000000\0" \ | |
| 591 | "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ | |
| 592 | "console=ttyS0\0" \ | |
| 593 | "setbootargs=setenv bootargs " \ | |
| 594 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
| 595 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
| 596 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 597 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" | |
| 598 | ||
| 599 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 600 | "setenv rootdev /dev/nfs;" \ | |
| 601 | "run setbootargs;" \ | |
| 602 | "run setipargs;" \ | |
| 603 | "tftp $loadaddr $bootfile;" \ | |
| 604 | "tftp $fdtaddr $fdtfile;" \ | |
| 605 | "bootm $loadaddr - $fdtaddr" | |
| 606 | ||
| 607 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 608 | "setenv rootdev /dev/ram;" \ | |
| 609 | "run setbootargs;" \ | |
| 610 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 611 | "tftp $loadaddr $bootfile;" \ | |
| 612 | "tftp $fdtaddr $fdtfile;" \ | |
| 613 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 614 | ||
| 615 | #undef MK_STR | |
| 616 | #undef XMK_STR | |
| 617 | ||
| 618 | #endif /* __CONFIG_H */ |