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Commit | Line | Data |
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24c3aca3 DL |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
24c3aca3 DL |
5 | */ |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
24c3aca3 DL |
10 | /* |
11 | * High Level Configuration Options | |
12 | */ | |
13 | #define CONFIG_E300 1 /* E300 family */ | |
14 | #define CONFIG_QE 1 /* Has QE */ | |
2c7920af | 15 | #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ |
24c3aca3 | 16 | #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ |
2ae18241 WD |
17 | |
18 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
24c3aca3 DL |
19 | |
20 | /* | |
21 | * System Clock Setup | |
22 | */ | |
23 | #ifdef CONFIG_PCISLAVE | |
24 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
25 | #else | |
26 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
27 | #endif | |
28 | ||
29 | #ifndef CONFIG_SYS_CLK_FREQ | |
30 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
31 | #endif | |
32 | ||
33 | /* | |
34 | * Hardware Reset Configuration Word | |
35 | */ | |
6d0f6bcf | 36 | #define CONFIG_SYS_HRCW_LOW (\ |
24c3aca3 DL |
37 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
38 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
39 | HRCWL_VCO_1X2 |\ | |
40 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
41 | HRCWL_CORE_TO_CSB_2X1 |\ | |
42 | HRCWL_CE_PLL_VCO_DIV_2 |\ | |
43 | HRCWL_CE_PLL_DIV_1X1 |\ | |
44 | HRCWL_CE_TO_PLL_1X3) | |
45 | ||
46 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 47 | #define CONFIG_SYS_HRCW_HIGH (\ |
24c3aca3 DL |
48 | HRCWH_PCI_AGENT |\ |
49 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
50 | HRCWH_CORE_ENABLE |\ | |
51 | HRCWH_FROM_0XFFF00100 |\ | |
52 | HRCWH_BOOTSEQ_DISABLE |\ | |
53 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
54 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
55 | HRCWH_BIG_ENDIAN |\ | |
56 | HRCWH_LALE_NORMAL) | |
57 | #else | |
6d0f6bcf | 58 | #define CONFIG_SYS_HRCW_HIGH (\ |
24c3aca3 DL |
59 | HRCWH_PCI_HOST |\ |
60 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
61 | HRCWH_CORE_ENABLE |\ | |
62 | HRCWH_FROM_0X00000100 |\ | |
63 | HRCWH_BOOTSEQ_DISABLE |\ | |
64 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
65 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
66 | HRCWH_BIG_ENDIAN |\ | |
67 | HRCWH_LALE_NORMAL) | |
68 | #endif | |
69 | ||
70 | /* | |
71 | * System IO Config | |
72 | */ | |
6d0f6bcf | 73 | #define CONFIG_SYS_SICRL 0x00000000 |
24c3aca3 | 74 | |
14778585 | 75 | #define CONFIG_BOARD_EARLY_INIT_R |
24c3aca3 DL |
76 | |
77 | /* | |
78 | * IMMR new address | |
79 | */ | |
6d0f6bcf | 80 | #define CONFIG_SYS_IMMR 0xE0000000 |
24c3aca3 DL |
81 | |
82 | /* | |
83 | * DDR Setup | |
84 | */ | |
989091ac JH |
85 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
86 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 87 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
989091ac | 88 | #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ |
24c3aca3 DL |
89 | |
90 | #undef CONFIG_SPD_EEPROM | |
91 | #if defined(CONFIG_SPD_EEPROM) | |
92 | /* Determine DDR configuration from I2C interface | |
93 | */ | |
94 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ | |
95 | #else | |
96 | /* Manually set up DDR parameters | |
97 | */ | |
6d0f6bcf | 98 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
2fef4020 JH |
99 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
100 | | CSCONFIG_AP \ | |
101 | | CSCONFIG_ODT_WR_CFG \ | |
102 | | CSCONFIG_ROW_BIT_13 \ | |
103 | | CSCONFIG_COL_BIT_10) | |
104 | /* 0x80840102 */ | |
105 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
106 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
107 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
108 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
109 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
110 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
111 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
112 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
113 | /* 0x00220802 */ | |
114 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | |
115 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
116 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
117 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
118 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
119 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
120 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
121 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
122 | /* 0x3935D322 */ | |
123 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ | |
124 | | (31 << TIMING_CFG2_CPO_SHIFT) \ | |
125 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
126 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
127 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
128 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
129 | | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
130 | /* 0x0F9048CA */ | |
989091ac | 131 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
2fef4020 JH |
132 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
133 | /* 0x02000000 */ | |
134 | #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ | |
135 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
136 | /* 0x44400232 */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 |
2fef4020 JH |
138 | #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
139 | | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
140 | /* 0x03200064 */ | |
989091ac | 141 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 |
2fef4020 JH |
142 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
143 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | |
144 | | SDRAM_CFG_32_BE) | |
145 | /* 0x43080000 */ | |
6d0f6bcf | 146 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
24c3aca3 DL |
147 | #endif |
148 | ||
149 | /* | |
150 | * Memory test | |
151 | */ | |
6d0f6bcf JCPV |
152 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
153 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
154 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
24c3aca3 DL |
155 | |
156 | /* | |
157 | * The reserved memory | |
158 | */ | |
14d0a02a | 159 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
24c3aca3 | 160 | |
6d0f6bcf JCPV |
161 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
162 | #define CONFIG_SYS_RAMBOOT | |
24c3aca3 | 163 | #else |
6d0f6bcf | 164 | #undef CONFIG_SYS_RAMBOOT |
24c3aca3 DL |
165 | #endif |
166 | ||
6d0f6bcf | 167 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
16c8c170 | 168 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
3b6b256c | 169 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
24c3aca3 DL |
170 | |
171 | /* | |
172 | * Initial RAM Base Address Setup | |
173 | */ | |
6d0f6bcf | 174 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
989091ac JH |
175 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ |
176 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ | |
177 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
178 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
24c3aca3 DL |
179 | |
180 | /* | |
181 | * Local Bus Configuration & Clock Setup | |
182 | */ | |
c7190f02 KP |
183 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
184 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
6d0f6bcf | 185 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
24c3aca3 DL |
186 | |
187 | /* | |
188 | * FLASH on the Local Bus | |
189 | */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
989091ac JH |
191 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
192 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
193 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ | |
194 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
24c3aca3 | 195 | |
989091ac JH |
196 | /* Window base at flash base */ |
197 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 198 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
24c3aca3 | 199 | |
989091ac | 200 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
201 | | BR_PS_16 /* 16 bit port */ \ |
202 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
203 | | BR_V) /* valid */ | |
204 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
205 | | OR_GPCM_XAM \ | |
206 | | OR_GPCM_CSNT \ | |
207 | | OR_GPCM_ACS_DIV2 \ | |
208 | | OR_GPCM_XACS \ | |
209 | | OR_GPCM_SCY_15 \ | |
210 | | OR_GPCM_TRLX_SET \ | |
211 | | OR_GPCM_EHTR_SET \ | |
212 | | OR_GPCM_EAD) | |
213 | /* 0xfe006ff7 */ | |
24c3aca3 | 214 | |
989091ac JH |
215 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
216 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
24c3aca3 | 217 | |
6d0f6bcf | 218 | #undef CONFIG_SYS_FLASH_CHECKSUM |
24c3aca3 DL |
219 | |
220 | /* | |
221 | * BCSR on the Local Bus | |
222 | */ | |
989091ac JH |
223 | #define CONFIG_SYS_BCSR 0xF8000000 |
224 | /* Access window base at BCSR base */ | |
225 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
226 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
227 | ||
228 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
229 | | BR_PS_8 \ | |
230 | | BR_MS_GPCM \ | |
231 | | BR_V) | |
232 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
233 | | OR_GPCM_XAM \ | |
234 | | OR_GPCM_CSNT \ | |
235 | | OR_GPCM_XACS \ | |
236 | | OR_GPCM_SCY_15 \ | |
237 | | OR_GPCM_TRLX_SET \ | |
238 | | OR_GPCM_EHTR_SET \ | |
239 | | OR_GPCM_EAD) | |
240 | /* 0xFFFFE9F7 */ | |
24c3aca3 DL |
241 | |
242 | /* | |
243 | * Windows to access PIB via local bus | |
244 | */ | |
7d6a0982 JH |
245 | /* PIB window base 0xF8008000 */ |
246 | #define CONFIG_SYS_PIB_BASE 0xF8008000 | |
247 | #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) | |
248 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE | |
249 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
24c3aca3 DL |
250 | |
251 | /* | |
252 | * CS2 on Local Bus, to PIB | |
253 | */ | |
7d6a0982 JH |
254 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ |
255 | | BR_PS_8 \ | |
256 | | BR_MS_GPCM \ | |
257 | | BR_V) | |
258 | /* 0xF8008801 */ | |
259 | #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ | |
260 | | OR_GPCM_XAM \ | |
261 | | OR_GPCM_CSNT \ | |
262 | | OR_GPCM_XACS \ | |
263 | | OR_GPCM_SCY_15 \ | |
264 | | OR_GPCM_TRLX_SET \ | |
265 | | OR_GPCM_EHTR_SET \ | |
266 | | OR_GPCM_EAD) | |
267 | /* 0xffffe9f7 */ | |
24c3aca3 DL |
268 | |
269 | /* | |
270 | * CS3 on Local Bus, to PIB | |
271 | */ | |
7d6a0982 JH |
272 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \ |
273 | CONFIG_SYS_PIB_WINDOW_SIZE) \ | |
274 | | BR_PS_8 \ | |
275 | | BR_MS_GPCM \ | |
276 | | BR_V) | |
277 | /* 0xF8010801 */ | |
278 | #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ | |
279 | | OR_GPCM_XAM \ | |
280 | | OR_GPCM_CSNT \ | |
281 | | OR_GPCM_XACS \ | |
282 | | OR_GPCM_SCY_15 \ | |
283 | | OR_GPCM_TRLX_SET \ | |
284 | | OR_GPCM_EHTR_SET \ | |
285 | | OR_GPCM_EAD) | |
286 | /* 0xffffe9f7 */ | |
24c3aca3 DL |
287 | |
288 | /* | |
289 | * Serial Port | |
290 | */ | |
291 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_NS16550_SERIAL |
293 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
294 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
24c3aca3 | 295 | |
6d0f6bcf | 296 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
989091ac | 297 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
24c3aca3 | 298 | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
300 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
24c3aca3 | 301 | |
22d71a71 | 302 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 303 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
24c3aca3 | 304 | |
24c3aca3 | 305 | /* I2C */ |
00f792e0 HS |
306 | #define CONFIG_SYS_I2C |
307 | #define CONFIG_SYS_I2C_FSL | |
308 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
309 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
310 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
311 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
24c3aca3 DL |
312 | |
313 | /* | |
314 | * Config on-board RTC | |
315 | */ | |
316 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 317 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
24c3aca3 DL |
318 | |
319 | /* | |
320 | * General PCI | |
321 | * Addresses are mapped 1-1. | |
322 | */ | |
9993e196 KP |
323 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
324 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
325 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
326 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
327 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
328 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
329 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
330 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 | |
331 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
24c3aca3 | 332 | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
334 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
335 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
24c3aca3 | 336 | |
24c3aca3 | 337 | #ifdef CONFIG_PCI |
842033e6 | 338 | #define CONFIG_PCI_INDIRECT_BRIDGE |
24c3aca3 | 339 | |
9993e196 | 340 | #define CONFIG_83XX_PCI_STREAMING |
24c3aca3 DL |
341 | |
342 | #undef CONFIG_EEPRO100 | |
343 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 344 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
24c3aca3 DL |
345 | |
346 | #endif /* CONFIG_PCI */ | |
347 | ||
24c3aca3 DL |
348 | /* |
349 | * QE UEC ethernet configuration | |
350 | */ | |
351 | #define CONFIG_UEC_ETH | |
78b7a8ef | 352 | #define CONFIG_ETHPRIME "UEC0" |
24c3aca3 DL |
353 | |
354 | #define CONFIG_UEC_ETH1 /* ETH3 */ | |
355 | ||
356 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
357 | #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ |
358 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 | |
359 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 | |
360 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
361 | #define CONFIG_SYS_UEC1_PHY_ADDR 3 | |
865ff856 | 362 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 363 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
24c3aca3 DL |
364 | #endif |
365 | ||
366 | #define CONFIG_UEC_ETH2 /* ETH4 */ | |
367 | ||
368 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
369 | #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ |
370 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 | |
371 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 | |
372 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
373 | #define CONFIG_SYS_UEC2_PHY_ADDR 4 | |
865ff856 | 374 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 375 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
24c3aca3 DL |
376 | #endif |
377 | ||
378 | /* | |
379 | * Environment | |
380 | */ | |
6d0f6bcf | 381 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 382 | #define CONFIG_ENV_IS_IN_FLASH 1 |
989091ac JH |
383 | #define CONFIG_ENV_ADDR \ |
384 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
385 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
386 | #define CONFIG_ENV_SIZE 0x2000 | |
24c3aca3 | 387 | #else |
93f6d725 | 388 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 389 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 390 | #define CONFIG_ENV_SIZE 0x2000 |
24c3aca3 DL |
391 | #endif |
392 | ||
393 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 394 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
24c3aca3 | 395 | |
079a136c JL |
396 | /* |
397 | * BOOTP options | |
398 | */ | |
399 | #define CONFIG_BOOTP_BOOTFILESIZE | |
400 | #define CONFIG_BOOTP_BOOTPATH | |
401 | #define CONFIG_BOOTP_GATEWAY | |
402 | #define CONFIG_BOOTP_HOSTNAME | |
403 | ||
8ea5499a JL |
404 | /* |
405 | * Command line configuration. | |
406 | */ | |
8ea5499a | 407 | |
24c3aca3 | 408 | #if defined(CONFIG_PCI) |
8ea5499a | 409 | #define CONFIG_CMD_PCI |
24c3aca3 | 410 | #endif |
8ea5499a | 411 | |
24c3aca3 DL |
412 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
413 | ||
414 | /* | |
415 | * Miscellaneous configurable options | |
416 | */ | |
989091ac JH |
417 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
418 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
24c3aca3 | 419 | |
8ea5499a | 420 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 421 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
24c3aca3 | 422 | #else |
6d0f6bcf | 423 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
24c3aca3 DL |
424 | #endif |
425 | ||
989091ac JH |
426 | /* Print Buffer Size */ |
427 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
428 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
429 | /* Boot Argument Buffer Size */ | |
430 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
24c3aca3 DL |
431 | |
432 | /* | |
433 | * For booting Linux, the board info and command line data | |
9f530d59 | 434 | * have to be in the first 256 MB of memory, since this is |
24c3aca3 DL |
435 | * the maximum mapped by the Linux kernel during initialization. |
436 | */ | |
989091ac JH |
437 | /* Initial Memory map for Linux */ |
438 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
63865278 | 439 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
24c3aca3 DL |
440 | |
441 | /* | |
442 | * Core HID Setup | |
443 | */ | |
1a2e203b KP |
444 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
445 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
446 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 447 | #define CONFIG_SYS_HID2 HID2_HBE |
24c3aca3 | 448 | |
24c3aca3 DL |
449 | /* |
450 | * MMU Setup | |
451 | */ | |
452 | ||
31d82672 BB |
453 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
454 | ||
24c3aca3 | 455 | /* DDR: cache cacheable */ |
989091ac | 456 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 457 | | BATL_PP_RW \ |
989091ac JH |
458 | | BATL_MEMCOHERENCE) |
459 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
460 | | BATU_BL_256M \ | |
461 | | BATU_VS \ | |
462 | | BATU_VP) | |
6d0f6bcf JCPV |
463 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
464 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
24c3aca3 DL |
465 | |
466 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
989091ac | 467 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 468 | | BATL_PP_RW \ |
989091ac JH |
469 | | BATL_CACHEINHIBIT \ |
470 | | BATL_GUARDEDSTORAGE) | |
471 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
472 | | BATU_BL_4M \ | |
473 | | BATU_VS \ | |
474 | | BATU_VP) | |
6d0f6bcf JCPV |
475 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
476 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
24c3aca3 DL |
477 | |
478 | /* BCSR: cache-inhibit and guarded */ | |
989091ac | 479 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ |
72cd4087 | 480 | | BATL_PP_RW \ |
989091ac JH |
481 | | BATL_CACHEINHIBIT \ |
482 | | BATL_GUARDEDSTORAGE) | |
483 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ | |
484 | | BATU_BL_128K \ | |
485 | | BATU_VS \ | |
486 | | BATU_VP) | |
6d0f6bcf JCPV |
487 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
488 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
24c3aca3 DL |
489 | |
490 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
989091ac | 491 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 492 | | BATL_PP_RW \ |
989091ac JH |
493 | | BATL_MEMCOHERENCE) |
494 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | |
495 | | BATU_BL_32M \ | |
496 | | BATU_VS \ | |
497 | | BATU_VP) | |
498 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 499 | | BATL_PP_RW \ |
989091ac JH |
500 | | BATL_CACHEINHIBIT \ |
501 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 502 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
24c3aca3 | 503 | |
6d0f6bcf JCPV |
504 | #define CONFIG_SYS_IBAT4L (0) |
505 | #define CONFIG_SYS_IBAT4U (0) | |
506 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
507 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
24c3aca3 DL |
508 | |
509 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 510 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
989091ac JH |
511 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
512 | | BATU_BL_128K \ | |
513 | | BATU_VS \ | |
514 | | BATU_VP) | |
6d0f6bcf JCPV |
515 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
516 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
24c3aca3 DL |
517 | |
518 | #ifdef CONFIG_PCI | |
519 | /* PCI MEM space: cacheable */ | |
989091ac | 520 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ |
72cd4087 | 521 | | BATL_PP_RW \ |
989091ac JH |
522 | | BATL_MEMCOHERENCE) |
523 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | |
524 | | BATU_BL_256M \ | |
525 | | BATU_VS \ | |
526 | | BATU_VP) | |
6d0f6bcf JCPV |
527 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
528 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
24c3aca3 | 529 | /* PCI MMIO space: cache-inhibit and guarded */ |
989091ac | 530 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
72cd4087 | 531 | | BATL_PP_RW \ |
989091ac JH |
532 | | BATL_CACHEINHIBIT \ |
533 | | BATL_GUARDEDSTORAGE) | |
534 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ | |
535 | | BATU_BL_256M \ | |
536 | | BATU_VS \ | |
537 | | BATU_VP) | |
6d0f6bcf JCPV |
538 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
539 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
24c3aca3 | 540 | #else |
6d0f6bcf JCPV |
541 | #define CONFIG_SYS_IBAT6L (0) |
542 | #define CONFIG_SYS_IBAT6U (0) | |
543 | #define CONFIG_SYS_IBAT7L (0) | |
544 | #define CONFIG_SYS_IBAT7U (0) | |
545 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
546 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
547 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
548 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
24c3aca3 DL |
549 | #endif |
550 | ||
8ea5499a | 551 | #if defined(CONFIG_CMD_KGDB) |
24c3aca3 | 552 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
24c3aca3 DL |
553 | #endif |
554 | ||
555 | /* | |
556 | * Environment Configuration | |
9993e196 | 557 | */ #define CONFIG_ENV_OVERWRITE |
24c3aca3 DL |
558 | |
559 | #if defined(CONFIG_UEC_ETH) | |
977b5758 | 560 | #define CONFIG_HAS_ETH0 |
24c3aca3 | 561 | #define CONFIG_HAS_ETH1 |
24c3aca3 DL |
562 | #endif |
563 | ||
79f516bc | 564 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
24c3aca3 | 565 | |
24c3aca3 DL |
566 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
567 | ||
568 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
989091ac JH |
569 | "netdev=eth0\0" \ |
570 | "consoledev=ttyS0\0" \ | |
571 | "ramdiskaddr=1000000\0" \ | |
572 | "ramdiskfile=ramfs.83xx\0" \ | |
573 | "fdtaddr=780000\0" \ | |
574 | "fdtfile=mpc832x_mds.dtb\0" \ | |
575 | "" | |
24c3aca3 DL |
576 | |
577 | #define CONFIG_NFSBOOTCOMMAND \ | |
989091ac JH |
578 | "setenv bootargs root=/dev/nfs rw " \ |
579 | "nfsroot=$serverip:$rootpath " \ | |
580 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
581 | "$netdev:off " \ | |
582 | "console=$consoledev,$baudrate $othbootargs;" \ | |
583 | "tftp $loadaddr $bootfile;" \ | |
584 | "tftp $fdtaddr $fdtfile;" \ | |
585 | "bootm $loadaddr - $fdtaddr" | |
24c3aca3 DL |
586 | |
587 | #define CONFIG_RAMBOOTCOMMAND \ | |
989091ac JH |
588 | "setenv bootargs root=/dev/ram rw " \ |
589 | "console=$consoledev,$baudrate $othbootargs;" \ | |
590 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
591 | "tftp $loadaddr $bootfile;" \ | |
592 | "tftp $fdtaddr $fdtfile;" \ | |
593 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
24c3aca3 | 594 | |
24c3aca3 DL |
595 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
596 | ||
597 | #endif /* __CONFIG_H */ |