[thirdparty/u-boot.git] / include / configs / MPC832XEMDS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 family */

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRL		0x00000000

/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* DDR is system memory */
#define CONFIG_SYS_DDRCDR	0x73000002	/* DDR II voltage is 1.8V */

#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
 */
#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
#else
/* Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE		128	/* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
					| CSCONFIG_AP \
					| CSCONFIG_ODT_WR_CFG \
					| CSCONFIG_ROW_BIT_13 \
					| CSCONFIG_COL_BIT_10)
					/* 0x80840102 */
#define CONFIG_SYS_DDR_TIMING_0		((0 << TIMING_CFG0_RWT_SHIFT) \
					| (0 << TIMING_CFG0_WRT_SHIFT) \
					| (0 << TIMING_CFG0_RRT_SHIFT) \
					| (0 << TIMING_CFG0_WWT_SHIFT) \
					| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
					| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
					| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
					| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
					/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1		((3 << TIMING_CFG1_PRETOACT_SHIFT) \
					| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
					| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
					| (5 << TIMING_CFG1_CASLAT_SHIFT) \
					| (13 << TIMING_CFG1_REFREC_SHIFT) \
					| (3 << TIMING_CFG1_WRREC_SHIFT) \
					| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
					| (2 << TIMING_CFG1_WRTORD_SHIFT))
					/* 0x3935D322 */
#define CONFIG_SYS_DDR_TIMING_2		((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (31 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x0F9048CA */
#define CONFIG_SYS_DDR_TIMING_3		0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
					/* 0x02000000 */
#define CONFIG_SYS_DDR_MODE		((0x4440 << SDRAM_MODE_ESD_SHIFT) \
					| (0x0232 << SDRAM_MODE_SD_SHIFT))
					/* 0x44400232 */
#define CONFIG_SYS_DDR_MODE2		0x8000c000
#define CONFIG_SYS_DDR_INTERVAL		((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
					| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
					/* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS		0x00000007
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
					| SDRAM_CFG_32_BE)
					/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#endif

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE	16	/* FLASH size is 16M */


#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

/*
 * BCSR on the Local Bus
 */
#define CONFIG_SYS_BCSR			0xF8000000
					/* Access window base at BCSR base */


/*
 * Windows to access PIB via local bus
 */
					/* PIB window base 0xF8008000 */
#define CONFIG_SYS_PIB_BASE		0xF8008000
#define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)

/*
 * CS2 on Local Bus, to PIB
 */


/*
 * CS3 on Local Bus, to PIB
 */


/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
#define CONFIG_SYS_PCI1_IO_SIZE		0x100000	/* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE

#define CONFIG_83XX_PCI_STREAMING

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#define CONFIG_UEC_ETH1		/* ETH3 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	3
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

#define CONFIG_UEC_ETH2		/* ETH4 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR	4
#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
					/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */ #define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=ramfs.83xx\0"					\
	"fdtaddr=780000\0"						\
	"fdtfile=mpc832x_mds.dtb\0"					\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
24c3aca3 DL	2	/*
24c3aca3 DL	3	* Copyright (C) 2006 Freescale Semiconductor, Inc.
24c3aca3 DL	4	*/
	5
	6	#ifndef __CONFIG_H
	7	#define __CONFIG_H
	8
24c3aca3 DL	9	/*
	10	* High Level Configuration Options
	11	*/
	12	#define CONFIG_E300 1 /* E300 family */
2ae18241	13
24c3aca3 DL	14	/*
	15	* System IO Config
	16	*/
6d0f6bcf	17	#define CONFIG_SYS_SICRL 0x00000000
24c3aca3	18
24c3aca3 DL	19	/*
	20	* DDR Setup
	21	*/
8a81bfd2	22	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
989091ac	23	#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
24c3aca3 DL	24
	25	#undef CONFIG_SPD_EEPROM
	26	#if defined(CONFIG_SPD_EEPROM)
	27	/* Determine DDR configuration from I2C interface
	28	*/
	29	#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
	30	#else
	31	/* Manually set up DDR parameters
	32	*/
6d0f6bcf	33	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
2fef4020 JH	34	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
	35	\| CSCONFIG_AP \
	36	\| CSCONFIG_ODT_WR_CFG \
	37	\| CSCONFIG_ROW_BIT_13 \
	38	\| CSCONFIG_COL_BIT_10)
	39	/* 0x80840102 */
	40	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	41	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	42	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	43	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	44	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	45	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	46	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	47	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	48	/* 0x00220802 */
	49	#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
	50	\| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	51	\| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
	52	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	53	\| (13 << TIMING_CFG1_REFREC_SHIFT) \
	54	\| (3 << TIMING_CFG1_WRREC_SHIFT) \
	55	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	56	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	57	/* 0x3935D322 */
	58	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
	59	\| (31 << TIMING_CFG2_CPO_SHIFT) \
	60	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	61	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	62	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	63	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	64	\| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
	65	/* 0x0F9048CA */
989091ac	66	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
2fef4020 JH	67	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	68	/* 0x02000000 */
	69	#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
	70	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
	71	/* 0x44400232 */
6d0f6bcf	72	#define CONFIG_SYS_DDR_MODE2 0x8000c000
2fef4020 JH	73	#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
	74	\| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	75	/* 0x03200064 */
989091ac	76	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
2fef4020 JH	77	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
	78	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
	79	\| SDRAM_CFG_32_BE)
	80	/* 0x43080000 */
6d0f6bcf	81	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
24c3aca3 DL	82	#endif
	83
	84	/*
	85	* Memory test
	86	*/
6d0f6bcf	87	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
24c3aca3 DL	88
	89	/*
	90	* The reserved memory
	91	*/
14d0a02a	92	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
24c3aca3	93
6d0f6bcf JCPV	94	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	95	#define CONFIG_SYS_RAMBOOT
24c3aca3	96	#else
6d0f6bcf	97	#undef CONFIG_SYS_RAMBOOT
24c3aca3 DL	98	#endif
24c3aca3 DL	99
6d0f6bcf	100	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170	101	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
3b6b256c	102	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
24c3aca3 DL	103
	104	/*
	105	* Initial RAM Base Address Setup
	106	*/
6d0f6bcf	107	#define CONFIG_SYS_INIT_RAM_LOCK 1
989091ac JH	108	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
	109	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
	110	#define CONFIG_SYS_GBL_DATA_OFFSET \
	111	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
24c3aca3	112
24c3aca3 DL	113	/*
	114	* FLASH on the Local Bus
	115	*/
989091ac JH	116	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
989091ac JH	117	#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
24c3aca3	118
24c3aca3	119
989091ac JH	120	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
989091ac JH	121	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
24c3aca3	122
6d0f6bcf	123	#undef CONFIG_SYS_FLASH_CHECKSUM
24c3aca3 DL	124
	125	/*
	126	* BCSR on the Local Bus
	127	*/
989091ac JH	128	#define CONFIG_SYS_BCSR 0xF8000000
989091ac JH	129	/* Access window base at BCSR base */
7d6a0982	130
24c3aca3 DL	131
	132	/*
	133	* Windows to access PIB via local bus
	134	*/
7d6a0982 JH	135	/* PIB window base 0xF8008000 */
	136	#define CONFIG_SYS_PIB_BASE 0xF8008000
	137	#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
24c3aca3 DL	138
	139	/*
	140	* CS2 on Local Bus, to PIB
	141	*/
a8f97539	142
24c3aca3 DL	143
	144	/*
	145	* CS3 on Local Bus, to PIB
	146	*/
a8f97539	147
24c3aca3 DL	148
	149	/*
	150	* Serial Port
	151	*/
6d0f6bcf JCPV	152	#define CONFIG_SYS_NS16550_SERIAL
	153	#define CONFIG_SYS_NS16550_REG_SIZE 1
	154	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
24c3aca3	155
6d0f6bcf	156	#define CONFIG_SYS_BAUDRATE_TABLE \
989091ac	157	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
24c3aca3	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	160	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
24c3aca3	161
24c3aca3	162	/* I2C */
00f792e0 HS	163	#define CONFIG_SYS_I2C
	164	#define CONFIG_SYS_I2C_FSL
	165	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	166	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	167	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	168	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
24c3aca3 DL	169
	170	/*
	171	* Config on-board RTC
	172	*/
	173	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
6d0f6bcf	174	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
24c3aca3 DL	175
	176	/*
	177	* General PCI
	178	* Addresses are mapped 1-1.
	179	*/
9993e196 KP	180	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	181	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	182	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	183	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	184	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	185	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	186	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	187	#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
	188	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
24c3aca3	189
6d0f6bcf JCPV	190	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
	191	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
	192	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
24c3aca3	193
24c3aca3	194	#ifdef CONFIG_PCI
842033e6	195	#define CONFIG_PCI_INDIRECT_BRIDGE
24c3aca3	196
9993e196	197	#define CONFIG_83XX_PCI_STREAMING
24c3aca3 DL	198
	199	#undef CONFIG_EEPRO100
	200	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	201	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
24c3aca3 DL	202
	203	#endif /* CONFIG_PCI */
	204
24c3aca3 DL	205	/*
	206	* QE UEC ethernet configuration
	207	*/
	208	#define CONFIG_UEC_ETH
78b7a8ef	209	#define CONFIG_ETHPRIME "UEC0"
24c3aca3 DL	210
	211	#define CONFIG_UEC_ETH1 /* ETH3 */
	212
	213	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	214	#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
	215	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
	216	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
	217	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	218	#define CONFIG_SYS_UEC1_PHY_ADDR 3
865ff856	219	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	220	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
24c3aca3 DL	221	#endif
	222
	223	#define CONFIG_UEC_ETH2 /* ETH4 */
	224
	225	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	226	#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
	227	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
	228	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
	229	#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
	230	#define CONFIG_SYS_UEC2_PHY_ADDR 4
865ff856	231	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	232	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
24c3aca3 DL	233	#endif
	234
	235	/*
	236	* Environment
	237	*/
24c3aca3 DL	238
24c3aca3 DL	239	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	240	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
24c3aca3	241
079a136c JL	242	/*
	243	* BOOTP options
	244	*/
	245	#define CONFIG_BOOTP_BOOTFILESIZE
079a136c	246
8ea5499a JL	247	/*
	248	* Command line configuration.
	249	*/
8ea5499a	250
24c3aca3 DL	251	#undef CONFIG_WATCHDOG /* watchdog disabled */
	252
	253	/*
	254	* Miscellaneous configurable options
	255	*/
989091ac	256	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
24c3aca3	257
24c3aca3 DL	258	/*
24c3aca3 DL	259	* For booting Linux, the board info and command line data
9f530d59	260	* have to be in the first 256 MB of memory, since this is
24c3aca3 DL	261	* the maximum mapped by the Linux kernel during initialization.
24c3aca3 DL	262	*/
989091ac JH	263	/* Initial Memory map for Linux */
989091ac JH	264	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	265	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
24c3aca3	266
8ea5499a	267	#if defined(CONFIG_CMD_KGDB)
24c3aca3	268	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
24c3aca3 DL	269	#endif
	270
	271	/*
	272	* Environment Configuration
9993e196	273	*/ #define CONFIG_ENV_OVERWRITE
24c3aca3 DL	274
24c3aca3 DL	275	#if defined(CONFIG_UEC_ETH)
977b5758	276	#define CONFIG_HAS_ETH0
24c3aca3	277	#define CONFIG_HAS_ETH1
24c3aca3 DL	278	#endif
24c3aca3 DL	279
79f516bc	280	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
24c3aca3	281
24c3aca3	282	#define CONFIG_EXTRA_ENV_SETTINGS \
989091ac JH	283	"netdev=eth0\0" \
	284	"consoledev=ttyS0\0" \
	285	"ramdiskaddr=1000000\0" \
	286	"ramdiskfile=ramfs.83xx\0" \
	287	"fdtaddr=780000\0" \
	288	"fdtfile=mpc832x_mds.dtb\0" \
	289	""
24c3aca3 DL	290
24c3aca3 DL	291	#define CONFIG_NFSBOOTCOMMAND \
989091ac JH	292	"setenv bootargs root=/dev/nfs rw " \
	293	"nfsroot=$serverip:$rootpath " \
	294	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	295	"$netdev:off " \
	296	"console=$consoledev,$baudrate $othbootargs;" \
	297	"tftp $loadaddr $bootfile;" \
	298	"tftp $fdtaddr $fdtfile;" \
	299	"bootm $loadaddr - $fdtaddr"
24c3aca3 DL	300
24c3aca3 DL	301	#define CONFIG_RAMBOOTCOMMAND \
989091ac JH	302	"setenv bootargs root=/dev/ram rw " \
	303	"console=$consoledev,$baudrate $othbootargs;" \
	304	"tftp $ramdiskaddr $ramdiskfile;" \
	305	"tftp $loadaddr $bootfile;" \
	306	"tftp $fdtaddr $fdtfile;" \
	307	"bootm $loadaddr $ramdiskaddr $fdtaddr"
24c3aca3	308
24c3aca3 DL	309	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	310
	311	#endif /* __CONFIG_H */