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Commit | Line | Data |
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991425fe | 1 | /* |
2ae18241 | 2 | * (C) Copyright 2006-2010 |
991425fe MB |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
991425fe MB |
6 | */ |
7 | ||
8 | /* | |
9 | * mpc8349emds board configuration file | |
10 | * | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
fdfaa29e KP |
16 | #define CONFIG_DISPLAY_BOARDINFO |
17 | ||
991425fe MB |
18 | /* |
19 | * High Level Configuration Options | |
20 | */ | |
21 | #define CONFIG_E300 1 /* E300 Family */ | |
2c7920af | 22 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
991425fe MB |
23 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
24 | #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ | |
25 | ||
2ae18241 WD |
26 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
27 | ||
28 | #define CONFIG_PCI_66M | |
29 | #ifdef CONFIG_PCI_66M | |
991425fe MB |
30 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
31 | #else | |
32 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
33 | #endif | |
34 | ||
447ad576 IS |
35 | #ifdef CONFIG_PCISLAVE |
36 | #define CONFIG_PCI | |
37 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ | |
38 | #endif /* CONFIG_PCISLAVE */ | |
39 | ||
991425fe | 40 | #ifndef CONFIG_SYS_CLK_FREQ |
2ae18241 | 41 | #ifdef CONFIG_PCI_66M |
991425fe | 42 | #define CONFIG_SYS_CLK_FREQ 66000000 |
8fe9bf61 | 43 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
991425fe MB |
44 | #else |
45 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
8fe9bf61 | 46 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
991425fe MB |
47 | #endif |
48 | #endif | |
49 | ||
50 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
51 | ||
6d0f6bcf | 52 | #define CONFIG_SYS_IMMR 0xE0000000 |
991425fe | 53 | |
32795eca | 54 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
56 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
991425fe MB |
57 | |
58 | /* | |
59 | * DDR Setup | |
60 | */ | |
8d172c0f | 61 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
d326f4a2 | 62 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
991425fe MB |
63 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
64 | ||
d4b91066 | 65 | /* |
5614e71b | 66 | * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver |
d4b91066 YS |
67 | * undefine it to use old spd_sdram.c |
68 | */ | |
5614e71b YS |
69 | #define CONFIG_SYS_FSL_DDR2 |
70 | #ifdef CONFIG_SYS_FSL_DDR2 | |
1df99080 | 71 | #define CONFIG_SYS_FSL_DDRC_GEN2 |
d4b91066 YS |
72 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
73 | #define SPD_EEPROM_ADDRESS1 0x52 | |
74 | #define SPD_EEPROM_ADDRESS2 0x51 | |
75 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
76 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
77 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
78 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
79 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
80 | #endif | |
81 | ||
dc9e499c RJ |
82 | /* |
83 | * 32-bit data path mode. | |
cf48eb9a | 84 | * |
dc9e499c RJ |
85 | * Please note that using this mode for devices with the real density of 64-bit |
86 | * effectively reduces the amount of available memory due to the effect of | |
87 | * wrapping around while translating address to row/columns, for example in the | |
88 | * 256MB module the upper 128MB get aliased with contents of the lower | |
89 | * 128MB); normally this define should be used for devices with real 32-bit | |
cf48eb9a | 90 | * data path. |
dc9e499c RJ |
91 | */ |
92 | #undef CONFIG_DDR_32BIT | |
93 | ||
32795eca JH |
94 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
95 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 96 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
32795eca JH |
97 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
98 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
991425fe MB |
99 | #undef CONFIG_DDR_2T_TIMING |
100 | ||
8d172c0f XX |
101 | /* |
102 | * DDRCDR - DDR Control Driver Register | |
103 | */ | |
6d0f6bcf | 104 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
8d172c0f | 105 | |
991425fe | 106 | #if defined(CONFIG_SPD_EEPROM) |
dc9e499c RJ |
107 | /* |
108 | * Determine DDR configuration from I2C interface. | |
109 | */ | |
110 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
991425fe | 111 | #else |
dc9e499c RJ |
112 | /* |
113 | * Manually set up DDR parameters | |
114 | */ | |
6d0f6bcf | 115 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
8d172c0f | 116 | #if defined(CONFIG_DDR_II) |
6d0f6bcf | 117 | #define CONFIG_SYS_DDRCDR 0x80080001 |
32795eca | 118 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f |
6d0f6bcf | 119 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 |
32795eca JH |
120 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
121 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
122 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
123 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
124 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
6d0f6bcf JCPV |
125 | #define CONFIG_SYS_DDR_MODE 0x47d00432 |
126 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
32795eca | 127 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
129 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
8d172c0f | 130 | #else |
2e651b24 | 131 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
32795eca JH |
132 | | CSCONFIG_ROW_BIT_13 \ |
133 | | CSCONFIG_COL_BIT_10) | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
135 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
32795eca | 136 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
6d0f6bcf | 137 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
dc9e499c RJ |
138 | |
139 | #if defined(CONFIG_DDR_32BIT) | |
140 | /* set burst length to 8 for 32-bit data path */ | |
32795eca JH |
141 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
142 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
dc9e499c RJ |
143 | #else |
144 | /* the default burst length is 4 - for 64-bit data path */ | |
32795eca JH |
145 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
146 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
dc9e499c | 147 | #endif |
991425fe | 148 | #endif |
8d172c0f | 149 | #endif |
991425fe MB |
150 | |
151 | /* | |
152 | * SDRAM on the Local Bus | |
153 | */ | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
155 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
991425fe MB |
156 | |
157 | /* | |
158 | * FLASH on the Local Bus | |
159 | */ | |
32795eca JH |
160 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
161 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf | 162 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
32795eca JH |
163 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ |
164 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
6d0f6bcf | 165 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
991425fe | 166 | |
7d6a0982 JH |
167 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
168 | | BR_PS_16 /* 16 bit port */ \ | |
169 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
170 | | BR_V) /* valid */ | |
171 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
32795eca JH |
172 | | OR_UPM_XAM \ |
173 | | OR_GPCM_CSNT \ | |
174 | | OR_GPCM_ACS_DIV2 \ | |
175 | | OR_GPCM_XACS \ | |
176 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
177 | | OR_GPCM_TRLX_SET \ |
178 | | OR_GPCM_EHTR_SET \ | |
32795eca | 179 | | OR_GPCM_EAD) |
7d6a0982 | 180 | |
32795eca JH |
181 | /* window base at flash base */ |
182 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 183 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
991425fe | 184 | |
32795eca JH |
185 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
186 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
991425fe | 187 | |
6d0f6bcf JCPV |
188 | #undef CONFIG_SYS_FLASH_CHECKSUM |
189 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
190 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
991425fe | 191 | |
14d0a02a | 192 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
991425fe | 193 | |
6d0f6bcf JCPV |
194 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
195 | #define CONFIG_SYS_RAMBOOT | |
991425fe | 196 | #else |
6d0f6bcf | 197 | #undef CONFIG_SYS_RAMBOOT |
991425fe MB |
198 | #endif |
199 | ||
200 | /* | |
201 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
202 | */ | |
32795eca JH |
203 | #define CONFIG_SYS_BCSR 0xE2400000 |
204 | /* Access window base at BCSR base */ | |
205 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
206 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
207 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
208 | | BR_PS_8 \ | |
209 | | BR_MS_GPCM \ | |
210 | | BR_V) | |
211 | /* 0x00000801 */ | |
212 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
213 | | OR_GPCM_XAM \ | |
214 | | OR_GPCM_CSNT \ | |
215 | | OR_GPCM_SCY_15 \ | |
216 | | OR_GPCM_TRLX_CLEAR \ | |
217 | | OR_GPCM_EHTR_CLEAR) | |
218 | /* 0xFFFFE8F0 */ | |
991425fe | 219 | |
6d0f6bcf | 220 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
32795eca JH |
221 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
222 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
991425fe | 223 | |
32795eca JH |
224 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
225 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 226 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
991425fe | 227 | |
32795eca | 228 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 229 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
991425fe MB |
230 | |
231 | /* | |
232 | * Local Bus LCRR and LBCR regs | |
233 | * LCRR: DLL bypass, Clock divider is 4 | |
234 | * External Local Bus rate is | |
235 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
236 | */ | |
32795eca JH |
237 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
238 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 239 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
991425fe | 240 | |
8d172c0f XX |
241 | /* |
242 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
6d0f6bcf | 243 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
8d172c0f | 244 | */ |
6d0f6bcf | 245 | #undef CONFIG_SYS_LB_SDRAM |
991425fe | 246 | |
6d0f6bcf | 247 | #ifdef CONFIG_SYS_LB_SDRAM |
991425fe MB |
248 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
249 | /* | |
250 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 251 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
991425fe MB |
252 | * |
253 | * For BR2, need: | |
254 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
255 | * port-size = 32-bits = BR2[19:20] = 11 | |
256 | * no parity checking = BR2[21:22] = 00 | |
257 | * SDRAM for MSEL = BR2[24:26] = 011 | |
258 | * Valid = BR[31] = 1 | |
259 | * | |
260 | * 0 4 8 12 16 20 24 28 | |
261 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
991425fe MB |
262 | */ |
263 | ||
7d6a0982 JH |
264 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
265 | | BR_PS_32 /* 32-bit port */ \ | |
266 | | BR_MS_SDRAM /* MSEL = SDRAM */ \ | |
267 | | BR_V) /* Valid */ | |
268 | /* 0xF0001861 */ | |
269 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
270 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
991425fe MB |
271 | |
272 | /* | |
6d0f6bcf | 273 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
991425fe MB |
274 | * |
275 | * For OR2, need: | |
276 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
277 | * XAM, OR2[17:18] = 11 | |
278 | * 9 columns OR2[19-21] = 010 | |
279 | * 13 rows OR2[23-25] = 100 | |
280 | * EAD set for extra time OR[31] = 1 | |
281 | * | |
282 | * 0 4 8 12 16 20 24 28 | |
283 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
284 | */ | |
285 | ||
7d6a0982 JH |
286 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ |
287 | | OR_SDRAM_XAM \ | |
288 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
289 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
290 | | OR_SDRAM_EAD) | |
291 | /* 0xFC006901 */ | |
991425fe | 292 | |
32795eca JH |
293 | /* LB sdram refresh timer, about 6us */ |
294 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
295 | /* LB refresh timer prescal, 266MHz/32 */ | |
296 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
991425fe | 297 | |
32795eca | 298 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
540dcf1c KG |
299 | | LSDMR_BSMA1516 \ |
300 | | LSDMR_RFCR8 \ | |
301 | | LSDMR_PRETOACT6 \ | |
302 | | LSDMR_ACTTORW3 \ | |
303 | | LSDMR_BL8 \ | |
304 | | LSDMR_WRC3 \ | |
32795eca | 305 | | LSDMR_CL3) |
991425fe MB |
306 | |
307 | /* | |
308 | * SDRAM Controller configuration sequence. | |
309 | */ | |
540dcf1c KG |
310 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
311 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
312 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
313 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
314 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
991425fe MB |
315 | #endif |
316 | ||
317 | /* | |
318 | * Serial Port | |
319 | */ | |
320 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
321 | #define CONFIG_SYS_NS16550_SERIAL |
322 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
323 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
991425fe | 324 | |
6d0f6bcf | 325 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
32795eca | 326 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
991425fe | 327 | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
329 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
991425fe | 330 | |
22d71a71 | 331 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 332 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
991425fe | 333 | /* Use the HUSH parser */ |
6d0f6bcf | 334 | #define CONFIG_SYS_HUSH_PARSER |
991425fe | 335 | |
bf0b542d | 336 | /* pass open firmware flat tree */ |
bf0b542d | 337 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 338 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
bf0b542d | 339 | |
991425fe | 340 | /* I2C */ |
00f792e0 HS |
341 | #define CONFIG_SYS_I2C |
342 | #define CONFIG_SYS_I2C_FSL | |
343 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
344 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
345 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
346 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
347 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
348 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
349 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
991425fe | 350 | |
80ddd226 | 351 | /* SPI */ |
8931ab17 | 352 | #define CONFIG_MPC8XXX_SPI |
80ddd226 | 353 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
80ddd226 BW |
354 | |
355 | /* GPIOs. Used as SPI chip selects */ | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_GPIO1_PRELIM |
357 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
358 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
80ddd226 | 359 | |
991425fe | 360 | /* TSEC */ |
6d0f6bcf | 361 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
32795eca | 362 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 363 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
32795eca | 364 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
991425fe | 365 | |
8fe9bf61 | 366 | /* USB */ |
6d0f6bcf | 367 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
991425fe MB |
368 | |
369 | /* | |
370 | * General PCI | |
371 | * Addresses are mapped 1-1. | |
372 | */ | |
6d0f6bcf JCPV |
373 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
374 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
375 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
376 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
377 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
378 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
379 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
380 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
381 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
6d0f6bcf JCPV |
382 | |
383 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
384 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
385 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
386 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
387 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
388 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
389 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
390 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
391 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
991425fe MB |
392 | |
393 | #if defined(CONFIG_PCI) | |
394 | ||
8fe9bf61 | 395 | #define PCI_ONE_PCI1 |
991425fe MB |
396 | #if defined(PCI_64BIT) |
397 | #undef PCI_ALL_PCI1 | |
398 | #undef PCI_TWO_PCI1 | |
399 | #undef PCI_ONE_PCI1 | |
400 | #endif | |
401 | ||
991425fe | 402 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
162338e1 | 403 | #define CONFIG_83XX_PCI_STREAMING |
991425fe MB |
404 | |
405 | #undef CONFIG_EEPRO100 | |
406 | #undef CONFIG_TULIP | |
407 | ||
408 | #if !defined(CONFIG_PCI_PNP) | |
409 | #define PCI_ENET0_IOADDR 0xFIXME | |
410 | #define PCI_ENET0_MEMADDR 0xFIXME | |
53677ef1 | 411 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
991425fe MB |
412 | #endif |
413 | ||
414 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 415 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
991425fe MB |
416 | |
417 | #endif /* CONFIG_PCI */ | |
418 | ||
419 | /* | |
420 | * TSEC configuration | |
421 | */ | |
32795eca | 422 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
991425fe MB |
423 | |
424 | #if defined(CONFIG_TSEC_ENET) | |
991425fe MB |
425 | |
426 | #define CONFIG_GMII 1 /* MII PHY management */ | |
32795eca | 427 | #define CONFIG_TSEC1 1 |
255a3577 | 428 | #define CONFIG_TSEC1_NAME "TSEC0" |
32795eca | 429 | #define CONFIG_TSEC2 1 |
255a3577 | 430 | #define CONFIG_TSEC2_NAME "TSEC1" |
991425fe MB |
431 | #define TSEC1_PHY_ADDR 0 |
432 | #define TSEC2_PHY_ADDR 1 | |
433 | #define TSEC1_PHYIDX 0 | |
434 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
435 | #define TSEC1_FLAGS TSEC_GIGABIT |
436 | #define TSEC2_FLAGS TSEC_GIGABIT | |
991425fe MB |
437 | |
438 | /* Options are: TSEC[0-1] */ | |
439 | #define CONFIG_ETHPRIME "TSEC0" | |
440 | ||
441 | #endif /* CONFIG_TSEC_ENET */ | |
442 | ||
443 | /* | |
444 | * Configure on-board RTC | |
445 | */ | |
32795eca JH |
446 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
447 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
991425fe MB |
448 | |
449 | /* | |
450 | * Environment | |
451 | */ | |
6d0f6bcf | 452 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 453 | #define CONFIG_ENV_IS_IN_FLASH 1 |
32795eca JH |
454 | #define CONFIG_ENV_ADDR \ |
455 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
456 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
457 | #define CONFIG_ENV_SIZE 0x2000 | |
991425fe MB |
458 | |
459 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
460 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
461 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
991425fe MB |
462 | |
463 | #else | |
32795eca | 464 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 465 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 466 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 467 | #define CONFIG_ENV_SIZE 0x2000 |
991425fe MB |
468 | #endif |
469 | ||
470 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 471 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
991425fe | 472 | |
8ea5499a | 473 | |
659e2f67 JL |
474 | /* |
475 | * BOOTP options | |
476 | */ | |
477 | #define CONFIG_BOOTP_BOOTFILESIZE | |
478 | #define CONFIG_BOOTP_BOOTPATH | |
479 | #define CONFIG_BOOTP_GATEWAY | |
480 | #define CONFIG_BOOTP_HOSTNAME | |
481 | ||
482 | ||
8ea5499a JL |
483 | /* |
484 | * Command line configuration. | |
485 | */ | |
8ea5499a JL |
486 | #define CONFIG_CMD_PING |
487 | #define CONFIG_CMD_I2C | |
488 | #define CONFIG_CMD_DATE | |
489 | #define CONFIG_CMD_MII | |
490 | ||
991425fe | 491 | #if defined(CONFIG_PCI) |
8ea5499a | 492 | #define CONFIG_CMD_PCI |
991425fe | 493 | #endif |
8ea5499a | 494 | |
991425fe MB |
495 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
496 | ||
497 | /* | |
498 | * Miscellaneous configurable options | |
499 | */ | |
6d0f6bcf JCPV |
500 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
501 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
991425fe | 502 | |
8ea5499a | 503 | #if defined(CONFIG_CMD_KGDB) |
32795eca | 504 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
991425fe | 505 | #else |
32795eca | 506 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
991425fe MB |
507 | #endif |
508 | ||
32795eca JH |
509 | /* Print Buffer Size */ |
510 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
511 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
512 | /* Boot Argument Buffer Size */ | |
513 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
991425fe MB |
514 | |
515 | /* | |
516 | * For booting Linux, the board info and command line data | |
9f530d59 | 517 | * have to be in the first 256 MB of memory, since this is |
991425fe MB |
518 | * the maximum mapped by the Linux kernel during initialization. |
519 | */ | |
32795eca JH |
520 | /* Initial Memory map for Linux*/ |
521 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
991425fe | 522 | |
6d0f6bcf | 523 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
991425fe MB |
524 | |
525 | #if 1 /*528/264*/ | |
6d0f6bcf | 526 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
527 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
528 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 529 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
530 | HRCWL_VCO_1X2 |\ |
531 | HRCWL_CORE_TO_CSB_2X1) | |
532 | #elif 0 /*396/132*/ | |
6d0f6bcf | 533 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
534 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
535 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 536 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
537 | HRCWL_VCO_1X4 |\ |
538 | HRCWL_CORE_TO_CSB_3X1) | |
539 | #elif 0 /*264/132*/ | |
6d0f6bcf | 540 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
541 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
542 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 543 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
544 | HRCWL_VCO_1X4 |\ |
545 | HRCWL_CORE_TO_CSB_2X1) | |
546 | #elif 0 /*132/132*/ | |
6d0f6bcf | 547 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
548 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
549 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 550 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
551 | HRCWL_VCO_1X4 |\ |
552 | HRCWL_CORE_TO_CSB_1X1) | |
553 | #elif 0 /*264/264 */ | |
6d0f6bcf | 554 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
555 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
556 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 557 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
558 | HRCWL_VCO_1X4 |\ |
559 | HRCWL_CORE_TO_CSB_1X1) | |
560 | #endif | |
561 | ||
447ad576 | 562 | #ifdef CONFIG_PCISLAVE |
6d0f6bcf | 563 | #define CONFIG_SYS_HRCW_HIGH (\ |
447ad576 IS |
564 | HRCWH_PCI_AGENT |\ |
565 | HRCWH_64_BIT_PCI |\ | |
566 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
567 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
568 | HRCWH_CORE_ENABLE |\ | |
569 | HRCWH_FROM_0X00000100 |\ | |
570 | HRCWH_BOOTSEQ_DISABLE |\ | |
571 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
572 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
573 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 574 | HRCWH_TSEC2M_IN_GMII) |
447ad576 | 575 | #else |
991425fe | 576 | #if defined(PCI_64BIT) |
6d0f6bcf | 577 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
578 | HRCWH_PCI_HOST |\ |
579 | HRCWH_64_BIT_PCI |\ | |
580 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
581 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
582 | HRCWH_CORE_ENABLE |\ | |
583 | HRCWH_FROM_0X00000100 |\ | |
584 | HRCWH_BOOTSEQ_DISABLE |\ | |
585 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
586 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
587 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 588 | HRCWH_TSEC2M_IN_GMII) |
991425fe | 589 | #else |
6d0f6bcf | 590 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
591 | HRCWH_PCI_HOST |\ |
592 | HRCWH_32_BIT_PCI |\ | |
593 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
594 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
595 | HRCWH_CORE_ENABLE |\ | |
596 | HRCWH_FROM_0X00000100 |\ | |
597 | HRCWH_BOOTSEQ_DISABLE |\ | |
598 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
599 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
600 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 601 | HRCWH_TSEC2M_IN_GMII) |
447ad576 IS |
602 | #endif /* PCI_64BIT */ |
603 | #endif /* CONFIG_PCISLAVE */ | |
991425fe | 604 | |
a5fe514e LN |
605 | /* |
606 | * System performance | |
607 | */ | |
6d0f6bcf | 608 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
32795eca | 609 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
610 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
611 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
612 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
613 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
a5fe514e | 614 | |
991425fe | 615 | /* System IO Config */ |
3c9b1ee1 | 616 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 617 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
991425fe | 618 | |
6d0f6bcf | 619 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
32795eca JH |
620 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
621 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
991425fe | 622 | |
32795eca | 623 | /* #define CONFIG_SYS_HID0_FINAL (\ |
991425fe MB |
624 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
625 | HID0_ENABLE_M_BIT |\ | |
32795eca | 626 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
991425fe MB |
627 | |
628 | ||
6d0f6bcf | 629 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 630 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
991425fe MB |
631 | |
632 | /* DDR @ 0x00000000 */ | |
32795eca | 633 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 634 | | BATL_PP_RW \ |
32795eca JH |
635 | | BATL_MEMCOHERENCE) |
636 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
637 | | BATU_BL_256M \ | |
638 | | BATU_VS \ | |
639 | | BATU_VP) | |
991425fe MB |
640 | |
641 | /* PCI @ 0x80000000 */ | |
642 | #ifdef CONFIG_PCI | |
842033e6 | 643 | #define CONFIG_PCI_INDIRECT_BRIDGE |
32795eca | 644 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 645 | | BATL_PP_RW \ |
32795eca JH |
646 | | BATL_MEMCOHERENCE) |
647 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
648 | | BATU_BL_256M \ | |
649 | | BATU_VS \ | |
650 | | BATU_VP) | |
651 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 652 | | BATL_PP_RW \ |
32795eca JH |
653 | | BATL_CACHEINHIBIT \ |
654 | | BATL_GUARDEDSTORAGE) | |
655 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
656 | | BATU_BL_256M \ | |
657 | | BATU_VS \ | |
658 | | BATU_VP) | |
991425fe | 659 | #else |
6d0f6bcf JCPV |
660 | #define CONFIG_SYS_IBAT1L (0) |
661 | #define CONFIG_SYS_IBAT1U (0) | |
662 | #define CONFIG_SYS_IBAT2L (0) | |
663 | #define CONFIG_SYS_IBAT2U (0) | |
991425fe MB |
664 | #endif |
665 | ||
8fe9bf61 | 666 | #ifdef CONFIG_MPC83XX_PCI2 |
32795eca | 667 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 668 | | BATL_PP_RW \ |
32795eca JH |
669 | | BATL_MEMCOHERENCE) |
670 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
671 | | BATU_BL_256M \ | |
672 | | BATU_VS \ | |
673 | | BATU_VP) | |
674 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 675 | | BATL_PP_RW \ |
32795eca JH |
676 | | BATL_CACHEINHIBIT \ |
677 | | BATL_GUARDEDSTORAGE) | |
678 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
679 | | BATU_BL_256M \ | |
680 | | BATU_VS \ | |
681 | | BATU_VP) | |
8fe9bf61 | 682 | #else |
6d0f6bcf JCPV |
683 | #define CONFIG_SYS_IBAT3L (0) |
684 | #define CONFIG_SYS_IBAT3U (0) | |
685 | #define CONFIG_SYS_IBAT4L (0) | |
686 | #define CONFIG_SYS_IBAT4U (0) | |
8fe9bf61 | 687 | #endif |
991425fe | 688 | |
8fe9bf61 | 689 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
32795eca | 690 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 691 | | BATL_PP_RW \ |
32795eca JH |
692 | | BATL_CACHEINHIBIT \ |
693 | | BATL_GUARDEDSTORAGE) | |
694 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
695 | | BATU_BL_256M \ | |
696 | | BATU_VS \ | |
697 | | BATU_VP) | |
991425fe | 698 | |
8fe9bf61 | 699 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
32795eca | 700 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 JH |
701 | | BATL_PP_RW \ |
702 | | BATL_MEMCOHERENCE \ | |
703 | | BATL_GUARDEDSTORAGE) | |
32795eca JH |
704 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ |
705 | | BATU_BL_256M \ | |
706 | | BATU_VS \ | |
707 | | BATU_VP) | |
6d0f6bcf JCPV |
708 | |
709 | #define CONFIG_SYS_IBAT7L (0) | |
710 | #define CONFIG_SYS_IBAT7U (0) | |
711 | ||
712 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
713 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
714 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
715 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
716 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
717 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
718 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
719 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
720 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
721 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
722 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
723 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
724 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
725 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
726 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
727 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
991425fe | 728 | |
8ea5499a | 729 | #if defined(CONFIG_CMD_KGDB) |
991425fe | 730 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
991425fe MB |
731 | #endif |
732 | ||
733 | /* | |
734 | * Environment Configuration | |
735 | */ | |
736 | #define CONFIG_ENV_OVERWRITE | |
737 | ||
738 | #if defined(CONFIG_TSEC_ENET) | |
991425fe | 739 | #define CONFIG_HAS_ETH1 |
10327dc5 | 740 | #define CONFIG_HAS_ETH0 |
991425fe MB |
741 | #endif |
742 | ||
991425fe | 743 | #define CONFIG_HOSTNAME mpc8349emds |
8b3637c6 | 744 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 745 | #define CONFIG_BOOTFILE "uImage" |
991425fe | 746 | |
32795eca | 747 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
991425fe MB |
748 | |
749 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
32795eca | 750 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
991425fe MB |
751 | |
752 | #define CONFIG_BAUDRATE 115200 | |
753 | ||
754 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 755 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
991425fe MB |
756 | "echo" |
757 | ||
758 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
759 | "netdev=eth0\0" \ | |
760 | "hostname=mpc8349emds\0" \ | |
761 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
762 | "nfsroot=${serverip}:${rootpath}\0" \ | |
763 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
764 | "addip=setenv bootargs ${bootargs} " \ | |
765 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
766 | ":${hostname}:${netdev}:off panic=1\0" \ | |
767 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
768 | "flash_nfs=run nfsargs addip addtty;" \ | |
769 | "bootm ${kernel_addr}\0" \ | |
770 | "flash_self=run ramargs addip addtty;" \ | |
771 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
772 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
773 | "bootm\0" \ | |
991425fe MB |
774 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
775 | "update=protect off fe000000 fe03ffff; " \ | |
32795eca | 776 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ |
d8ab58b2 | 777 | "upd=run load update\0" \ |
79f516bc | 778 | "fdtaddr=780000\0" \ |
cc861f71 | 779 | "fdtfile=mpc834x_mds.dtb\0" \ |
991425fe MB |
780 | "" |
781 | ||
32795eca JH |
782 | #define CONFIG_NFSBOOTCOMMAND \ |
783 | "setenv bootargs root=/dev/nfs rw " \ | |
784 | "nfsroot=$serverip:$rootpath " \ | |
785 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
786 | "$netdev:off " \ | |
787 | "console=$consoledev,$baudrate $othbootargs;" \ | |
788 | "tftp $loadaddr $bootfile;" \ | |
789 | "tftp $fdtaddr $fdtfile;" \ | |
790 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d KP |
791 | |
792 | #define CONFIG_RAMBOOTCOMMAND \ | |
32795eca JH |
793 | "setenv bootargs root=/dev/ram rw " \ |
794 | "console=$consoledev,$baudrate $othbootargs;" \ | |
795 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
796 | "tftp $loadaddr $bootfile;" \ | |
797 | "tftp $fdtaddr $fdtfile;" \ | |
798 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
bf0b542d | 799 | |
991425fe MB |
800 | #define CONFIG_BOOTCOMMAND "run flash_self" |
801 | ||
802 | #endif /* __CONFIG_H */ |