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Commit | Line | Data |
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2ad6b513 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
2ad6b513 | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
2ad6b513 TT |
5 | */ |
6 | ||
7 | /* | |
7a78f148 | 8 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
2ad6b513 TT |
9 | |
10 | Memory map: | |
11 | ||
12 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
13 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
14 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
15 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
16 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
17 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
7a78f148 | 18 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
2ad6b513 | 19 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
7a78f148 TT |
20 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
21 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
22 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
2ad6b513 TT |
23 | |
24 | I2C address list: | |
dd520bf3 WD |
25 | Align. Board |
26 | Bus Addr Part No. Description Length Location | |
2ad6b513 | 27 | ---------------------------------------------------------------- |
dd520bf3 | 28 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
2ad6b513 | 29 | |
dd520bf3 WD |
30 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
31 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
32 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
33 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
34 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
35 | I2C1 0x68 DS1339 RTC 1 U68 | |
2ad6b513 TT |
36 | |
37 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
38 | */ | |
39 | ||
40 | #ifndef __CONFIG_H | |
41 | #define __CONFIG_H | |
42 | ||
fdfaa29e KP |
43 | #define CONFIG_DISPLAY_BOARDINFO |
44 | ||
14d0a02a | 45 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) |
6d0f6bcf | 46 | #define CONFIG_SYS_LOWBOOT |
7a78f148 | 47 | #endif |
2ad6b513 TT |
48 | |
49 | /* | |
50 | * High Level Configuration Options | |
51 | */ | |
2c7920af | 52 | #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ |
2ad6b513 TT |
53 | #define CONFIG_MPC8349 /* MPC8349 specific */ |
54 | ||
2ae18241 WD |
55 | #ifndef CONFIG_SYS_TEXT_BASE |
56 | #define CONFIG_SYS_TEXT_BASE 0xFEF00000 | |
57 | #endif | |
58 | ||
396abba2 | 59 | #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
7a78f148 | 60 | |
89c7784e TT |
61 | #define CONFIG_MISC_INIT_F |
62 | #define CONFIG_MISC_INIT_R | |
7a78f148 | 63 | |
89c7784e TT |
64 | /* |
65 | * On-board devices | |
66 | */ | |
2ad6b513 | 67 | |
7a78f148 | 68 | #ifdef CONFIG_MPC8349ITX |
396abba2 JH |
69 | /* The CF card interface on the back of the board */ |
70 | #define CONFIG_COMPACT_FLASH | |
89c7784e | 71 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
c9e34fe2 | 72 | #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ |
c31e1326 | 73 | #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ |
7a78f148 | 74 | #endif |
2ad6b513 | 75 | |
7a78f148 TT |
76 | #define CONFIG_PCI |
77 | #define CONFIG_RTC_DS1337 | |
00f792e0 | 78 | #define CONFIG_SYS_I2C |
7a78f148 | 79 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
2ad6b513 | 80 | |
7a78f148 TT |
81 | /* |
82 | * Device configurations | |
83 | */ | |
84 | ||
85 | /* I2C */ | |
00f792e0 HS |
86 | #ifdef CONFIG_SYS_I2C |
87 | #define CONFIG_SYS_I2C_FSL | |
88 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
89 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
90 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
91 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
92 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
93 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
2ad6b513 | 94 | |
6d0f6bcf | 95 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
b7be63ab | 96 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
6d0f6bcf JCPV |
97 | |
98 | #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ | |
99 | #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
100 | #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
101 | #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
102 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ | |
396abba2 JH |
103 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
104 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ | |
2ad6b513 | 105 | |
2ad6b513 | 106 | /* Don't probe these addresses: */ |
396abba2 | 107 | #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ |
6d0f6bcf JCPV |
108 | {1, CONFIG_SYS_I2C_8574_ADDR2}, \ |
109 | {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ | |
396abba2 | 110 | {1, CONFIG_SYS_I2C_8574A_ADDR2} } |
2ad6b513 | 111 | /* Bit definitions for the 8574[A] I2C expander */ |
396abba2 JH |
112 | /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
113 | #define I2C_8574_REVISION 0x03 | |
2ad6b513 TT |
114 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
115 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
116 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
117 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
118 | ||
2ad6b513 TT |
119 | #endif |
120 | ||
7a78f148 TT |
121 | /* Compact Flash */ |
122 | #ifdef CONFIG_COMPACT_FLASH | |
2ad6b513 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_IDE_MAXBUS 1 |
125 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
2ad6b513 | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
128 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE | |
129 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 | |
130 | #define CONFIG_SYS_ATA_REG_OFFSET 0 | |
131 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 | |
132 | #define CONFIG_SYS_ATA_STRIDE 2 | |
2ad6b513 | 133 | |
396abba2 JH |
134 | /* If a CF card is not inserted, time out quickly */ |
135 | #define ATA_RESET_TIME 1 | |
2ad6b513 | 136 | |
c9e34fe2 VG |
137 | #endif |
138 | ||
139 | /* | |
140 | * SATA | |
141 | */ | |
142 | #ifdef CONFIG_SATA_SIL3114 | |
143 | ||
144 | #define CONFIG_SYS_SATA_MAX_DEVICE 4 | |
145 | #define CONFIG_LIBATA | |
146 | #define CONFIG_LBA48 | |
2ad6b513 | 147 | |
7a78f148 | 148 | #endif |
2ad6b513 | 149 | |
c31e1326 VG |
150 | #ifdef CONFIG_SYS_USB_HOST |
151 | /* | |
152 | * Support USB | |
153 | */ | |
154 | #define CONFIG_CMD_USB | |
155 | #define CONFIG_USB_STORAGE | |
156 | #define CONFIG_USB_EHCI | |
157 | #define CONFIG_USB_EHCI_FSL | |
158 | ||
159 | /* Current USB implementation supports the only USB controller, | |
160 | * so we have to choose between the MPH or the DR ones */ | |
161 | #if 1 | |
162 | #define CONFIG_HAS_FSL_MPH_USB | |
163 | #else | |
164 | #define CONFIG_HAS_FSL_DR_USB | |
165 | #endif | |
166 | ||
167 | #endif | |
168 | ||
2ad6b513 | 169 | /* |
7a78f148 | 170 | * DDR Setup |
2ad6b513 | 171 | */ |
396abba2 | 172 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
174 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
175 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
396abba2 | 176 | #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_MEMTEST_END 0x2000 |
178 | ||
396abba2 JH |
179 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
180 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
f64702b7 | 181 | |
b7be63ab VG |
182 | #define CONFIG_VERY_BIG_RAM |
183 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) | |
184 | ||
00f792e0 | 185 | #ifdef CONFIG_SYS_I2C |
7a78f148 TT |
186 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
187 | #endif | |
188 | ||
396abba2 JH |
189 | /* No SPD? Then manually set up DDR parameters */ |
190 | #ifndef CONFIG_SPD_EEPROM | |
191 | #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ | |
2e651b24 | 192 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
396abba2 JH |
193 | | CSCONFIG_ROW_BIT_13 \ |
194 | | CSCONFIG_COL_BIT_10) | |
2ad6b513 | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_DDR_TIMING_1 0x26242321 |
197 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
2ad6b513 TT |
198 | #endif |
199 | ||
7a78f148 TT |
200 | /* |
201 | *Flash on the Local Bus | |
202 | */ | |
203 | ||
396abba2 JH |
204 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
205 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
207 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
396abba2 JH |
208 | /* 127 64KB sectors + 8 8KB sectors per device */ |
209 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
211 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
212 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
7a78f148 TT |
213 | |
214 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
215 | boards, we say we have two, but don't display a message if we find only one. */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_FLASH_QUIET_TEST |
396abba2 JH |
217 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
218 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
219 | {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} | |
220 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ | |
396abba2 | 221 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
7a78f148 | 222 | |
89c7784e TT |
223 | /* Vitesse 7385 */ |
224 | ||
225 | #ifdef CONFIG_VSC7385_ENET | |
226 | ||
227 | #define CONFIG_TSEC2 | |
228 | ||
229 | /* The flash address and size of the VSC7385 firmware image */ | |
230 | #define CONFIG_VSC7385_IMAGE 0xFEFFE000 | |
231 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
232 | ||
233 | #endif | |
234 | ||
7a78f148 TT |
235 | /* |
236 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
237 | */ | |
238 | ||
239 | /* Flash */ | |
2ad6b513 | 240 | |
7d6a0982 JH |
241 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
242 | | BR_PS_16 \ | |
243 | | BR_MS_GPCM \ | |
244 | | BR_V) | |
245 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
396abba2 JH |
246 | | OR_UPM_XAM \ |
247 | | OR_GPCM_CSNT \ | |
248 | | OR_GPCM_ACS_DIV2 \ | |
249 | | OR_GPCM_XACS \ | |
250 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
251 | | OR_GPCM_TRLX_SET \ |
252 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 253 | | OR_GPCM_EAD) |
6d0f6bcf | 254 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 255 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) |
2ad6b513 | 256 | |
7a78f148 | 257 | /* Vitesse 7385 */ |
2ad6b513 | 258 | |
6d0f6bcf | 259 | #define CONFIG_SYS_VSC7385_BASE 0xF8000000 |
2ad6b513 | 260 | |
89c7784e TT |
261 | #ifdef CONFIG_VSC7385_ENET |
262 | ||
7d6a0982 JH |
263 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
264 | | BR_PS_8 \ | |
265 | | BR_MS_GPCM \ | |
266 | | BR_V) | |
396abba2 JH |
267 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ |
268 | | OR_GPCM_CSNT \ | |
269 | | OR_GPCM_XACS \ | |
270 | | OR_GPCM_SCY_15 \ | |
271 | | OR_GPCM_SETA \ | |
7d6a0982 JH |
272 | | OR_GPCM_TRLX_SET \ |
273 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 274 | | OR_GPCM_EAD) |
2ad6b513 | 275 | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE |
277 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
2ad6b513 | 278 | |
7a78f148 | 279 | #endif |
2ad6b513 | 280 | |
7a78f148 TT |
281 | /* LED */ |
282 | ||
396abba2 | 283 | #define CONFIG_SYS_LED_BASE 0xF9000000 |
7d6a0982 JH |
284 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ |
285 | | BR_PS_8 \ | |
286 | | BR_MS_GPCM \ | |
287 | | BR_V) | |
396abba2 JH |
288 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ |
289 | | OR_GPCM_CSNT \ | |
290 | | OR_GPCM_ACS_DIV2 \ | |
291 | | OR_GPCM_XACS \ | |
292 | | OR_GPCM_SCY_9 \ | |
7d6a0982 JH |
293 | | OR_GPCM_TRLX_SET \ |
294 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 295 | | OR_GPCM_EAD) |
7a78f148 TT |
296 | |
297 | /* Compact Flash */ | |
2ad6b513 TT |
298 | |
299 | #ifdef CONFIG_COMPACT_FLASH | |
300 | ||
396abba2 | 301 | #define CONFIG_SYS_CF_BASE 0xF0000000 |
2ad6b513 | 302 | |
396abba2 JH |
303 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ |
304 | | BR_PS_16 \ | |
305 | | BR_MS_UPMA \ | |
306 | | BR_V) | |
307 | #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
2ad6b513 | 308 | |
6d0f6bcf JCPV |
309 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE |
310 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
2ad6b513 TT |
311 | |
312 | #endif | |
313 | ||
7a78f148 TT |
314 | /* |
315 | * U-Boot memory configuration | |
316 | */ | |
14d0a02a | 317 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
2ad6b513 | 318 | |
6d0f6bcf JCPV |
319 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
320 | #define CONFIG_SYS_RAMBOOT | |
2ad6b513 | 321 | #else |
6d0f6bcf | 322 | #undef CONFIG_SYS_RAMBOOT |
2ad6b513 TT |
323 | #endif |
324 | ||
6d0f6bcf | 325 | #define CONFIG_SYS_INIT_RAM_LOCK |
396abba2 JH |
326 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
327 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
2ad6b513 | 328 | |
396abba2 JH |
329 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
330 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 331 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2ad6b513 | 332 | |
6d0f6bcf | 333 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
396abba2 | 334 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 335 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
2ad6b513 TT |
336 | |
337 | /* | |
338 | * Local Bus LCRR and LBCR regs | |
339 | * LCRR: DLL bypass, Clock divider is 4 | |
340 | * External Local Bus rate is | |
341 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
342 | */ | |
c7190f02 KP |
343 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
344 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 345 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
2ad6b513 | 346 | |
396abba2 JH |
347 | /* LB sdram refresh timer, about 6us */ |
348 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
349 | /* LB refresh timer prescal, 266MHz/32*/ | |
350 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
2ad6b513 | 351 | |
2ad6b513 TT |
352 | /* |
353 | * Serial Port | |
354 | */ | |
355 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_NS16550 |
357 | #define CONFIG_SYS_NS16550_SERIAL | |
358 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
359 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
2ad6b513 | 360 | |
6d0f6bcf | 361 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
396abba2 | 362 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
7a78f148 | 363 | |
8a364f09 | 364 | #define CONFIG_CONSOLE ttyS0 |
7a78f148 | 365 | #define CONFIG_BAUDRATE 115200 |
2ad6b513 | 366 | |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
368 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
2ad6b513 | 369 | |
bf0b542d | 370 | /* pass open firmware flat tree */ |
35cc4e48 | 371 | #define CONFIG_OF_LIBFDT 1 |
5b8bc606 KP |
372 | #define CONFIG_OF_BOARD_SETUP 1 |
373 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
2ad6b513 | 374 | |
7a78f148 TT |
375 | /* |
376 | * PCI | |
377 | */ | |
2ad6b513 | 378 | #ifdef CONFIG_PCI |
842033e6 | 379 | #define CONFIG_PCI_INDIRECT_BRIDGE |
2ad6b513 TT |
380 | |
381 | #define CONFIG_MPC83XX_PCI2 | |
382 | ||
383 | /* | |
384 | * General PCI | |
385 | * Addresses are mapped 1-1. | |
386 | */ | |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
388 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
389 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
390 | #define CONFIG_SYS_PCI1_MMIO_BASE \ |
391 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
393 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
394 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
395 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
396 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
397 | |
398 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 JH |
399 | #define CONFIG_SYS_PCI2_MEM_BASE \ |
400 | (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) | |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
402 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
403 | #define CONFIG_SYS_PCI2_MMIO_BASE \ |
404 | (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE |
406 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
407 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
408 | #define CONFIG_SYS_PCI2_IO_PHYS \ | |
409 | (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) | |
410 | #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
411 | #endif |
412 | ||
dd520bf3 | 413 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
2ad6b513 | 414 | |
2ad6b513 TT |
415 | #ifndef CONFIG_PCI_PNP |
416 | #define PCI_ENET0_IOADDR 0x00000000 | |
6d0f6bcf | 417 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE |
2ad6b513 TT |
418 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
419 | #endif | |
420 | ||
421 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
422 | ||
423 | #endif | |
424 | ||
2ae18241 WD |
425 | #define CONFIG_PCI_66M |
426 | #ifdef CONFIG_PCI_66M | |
7a78f148 TT |
427 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
428 | #else | |
429 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
430 | #endif | |
431 | ||
2ad6b513 TT |
432 | /* TSEC */ |
433 | ||
434 | #ifdef CONFIG_TSEC_ENET | |
435 | ||
2ad6b513 | 436 | #define CONFIG_MII |
659e2f67 | 437 | #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ |
2ad6b513 | 438 | |
255a3577 | 439 | #define CONFIG_TSEC1 |
2ad6b513 | 440 | |
255a3577 | 441 | #ifdef CONFIG_TSEC1 |
10327dc5 | 442 | #define CONFIG_HAS_ETH0 |
255a3577 | 443 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 444 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
dd520bf3 | 445 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
2ad6b513 | 446 | #define TSEC1_PHYIDX 0 |
3a79013e | 447 | #define TSEC1_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
448 | #endif |
449 | ||
255a3577 | 450 | #ifdef CONFIG_TSEC2 |
7a78f148 | 451 | #define CONFIG_HAS_ETH1 |
255a3577 | 452 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 453 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e | 454 | |
2ad6b513 TT |
455 | #define TSEC2_PHY_ADDR 4 |
456 | #define TSEC2_PHYIDX 0 | |
3a79013e | 457 | #define TSEC2_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
458 | #endif |
459 | ||
460 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
461 | ||
462 | #endif | |
463 | ||
2ad6b513 TT |
464 | /* |
465 | * Environment | |
466 | */ | |
7a78f148 TT |
467 | #define CONFIG_ENV_OVERWRITE |
468 | ||
6d0f6bcf | 469 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 470 | #define CONFIG_ENV_IS_IN_FLASH |
396abba2 JH |
471 | #define CONFIG_ENV_ADDR \ |
472 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 | 473 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
396abba2 | 474 | #define CONFIG_ENV_SIZE 0x2000 |
2ad6b513 | 475 | #else |
396abba2 | 476 | #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ |
00b1883a | 477 | #undef CONFIG_FLASH_CFI_DRIVER |
93f6d725 | 478 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
396abba2 JH |
479 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
480 | #define CONFIG_ENV_SIZE 0x2000 | |
2ad6b513 TT |
481 | #endif |
482 | ||
483 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
6d0f6bcf | 484 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
2ad6b513 | 485 | |
659e2f67 JL |
486 | /* |
487 | * BOOTP options | |
488 | */ | |
489 | #define CONFIG_BOOTP_BOOTFILESIZE | |
490 | #define CONFIG_BOOTP_BOOTPATH | |
491 | #define CONFIG_BOOTP_GATEWAY | |
492 | #define CONFIG_BOOTP_HOSTNAME | |
493 | ||
494 | ||
8ea5499a JL |
495 | /* |
496 | * Command line configuration. | |
497 | */ | |
8ea5499a JL |
498 | #define CONFIG_CMD_CACHE |
499 | #define CONFIG_CMD_DATE | |
500 | #define CONFIG_CMD_IRQ | |
8ea5499a | 501 | #define CONFIG_CMD_PING |
b7be63ab | 502 | #define CONFIG_CMD_DHCP |
8ea5499a | 503 | #define CONFIG_CMD_SDRAM |
2ad6b513 | 504 | |
c31e1326 | 505 | #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ |
396abba2 JH |
506 | || defined(CONFIG_USB_STORAGE) |
507 | #define CONFIG_DOS_PARTITION | |
508 | #define CONFIG_CMD_FAT | |
509 | #define CONFIG_SUPPORT_VFAT | |
c9e34fe2 VG |
510 | #endif |
511 | ||
2ad6b513 | 512 | #ifdef CONFIG_COMPACT_FLASH |
396abba2 | 513 | #define CONFIG_CMD_IDE |
c9e34fe2 VG |
514 | #endif |
515 | ||
516 | #ifdef CONFIG_SATA_SIL3114 | |
396abba2 | 517 | #define CONFIG_CMD_SATA |
c31e1326 VG |
518 | #endif |
519 | ||
520 | #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) | |
396abba2 | 521 | #define CONFIG_CMD_EXT2 |
2ad6b513 TT |
522 | #endif |
523 | ||
524 | #ifdef CONFIG_PCI | |
396abba2 | 525 | #define CONFIG_CMD_PCI |
2ad6b513 TT |
526 | #endif |
527 | ||
00f792e0 | 528 | #ifdef CONFIG_SYS_I2C |
396abba2 | 529 | #define CONFIG_CMD_I2C |
2ad6b513 TT |
530 | #endif |
531 | ||
2ad6b513 | 532 | /* Watchdog */ |
2ad6b513 | 533 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
2ad6b513 TT |
534 | |
535 | /* | |
536 | * Miscellaneous configurable options | |
537 | */ | |
396abba2 JH |
538 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
539 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
540 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
541 | #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ | |
7a78f148 | 542 | |
6d0f6bcf | 543 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
05f91a65 | 544 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
7a78f148 | 545 | |
8ea5499a | 546 | #if defined(CONFIG_CMD_KGDB) |
396abba2 | 547 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
2ad6b513 | 548 | #else |
396abba2 | 549 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
2ad6b513 TT |
550 | #endif |
551 | ||
396abba2 JH |
552 | /* Print Buffer Size */ |
553 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
554 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
555 | /* Boot Argument Buffer Size */ | |
556 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
2ad6b513 TT |
557 | |
558 | /* | |
559 | * For booting Linux, the board info and command line data | |
9f530d59 | 560 | * have to be in the first 256 MB of memory, since this is |
2ad6b513 TT |
561 | * the maximum mapped by the Linux kernel during initialization. |
562 | */ | |
396abba2 JH |
563 | /* Initial Memory map for Linux*/ |
564 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
2ad6b513 | 565 | |
6d0f6bcf | 566 | #define CONFIG_SYS_HRCW_LOW (\ |
2ad6b513 TT |
567 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
568 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
569 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
570 | HRCWL_VCO_1X2 |\ | |
571 | HRCWL_CORE_TO_CSB_2X1) | |
572 | ||
6d0f6bcf JCPV |
573 | #ifdef CONFIG_SYS_LOWBOOT |
574 | #define CONFIG_SYS_HRCW_HIGH (\ | |
2ad6b513 | 575 | HRCWH_PCI_HOST |\ |
7a78f148 | 576 | HRCWH_32_BIT_PCI |\ |
2ad6b513 | 577 | HRCWH_PCI1_ARBITER_ENABLE |\ |
7a78f148 | 578 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
579 | HRCWH_CORE_ENABLE |\ |
580 | HRCWH_FROM_0X00000100 |\ | |
581 | HRCWH_BOOTSEQ_DISABLE |\ | |
582 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
583 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
584 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 585 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 | 586 | #else |
6d0f6bcf | 587 | #define CONFIG_SYS_HRCW_HIGH (\ |
2ad6b513 TT |
588 | HRCWH_PCI_HOST |\ |
589 | HRCWH_32_BIT_PCI |\ | |
590 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
7a78f148 | 591 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
592 | HRCWH_CORE_ENABLE |\ |
593 | HRCWH_FROM_0XFFF00100 |\ | |
594 | HRCWH_BOOTSEQ_DISABLE |\ | |
595 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
596 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
597 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 598 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 TT |
599 | #endif |
600 | ||
7a78f148 TT |
601 | /* |
602 | * System performance | |
603 | */ | |
6d0f6bcf | 604 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
396abba2 | 605 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
606 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
607 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
608 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
609 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
c31e1326 VG |
610 | #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ |
611 | #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ | |
2ad6b513 | 612 | |
7a78f148 TT |
613 | /* |
614 | * System IO Config | |
615 | */ | |
396abba2 JH |
616 | /* Needed for gigabit to work on TSEC 1 */ |
617 | #define CONFIG_SYS_SICRH SICRH_TSOBI1 | |
618 | /* USB DR as device + USB MPH as host */ | |
619 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) | |
2ad6b513 | 620 | |
1a2e203b KP |
621 | #define CONFIG_SYS_HID0_INIT 0x00000000 |
622 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE | |
2ad6b513 | 623 | |
6d0f6bcf | 624 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 625 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
2ad6b513 | 626 | |
7a78f148 | 627 | /* DDR */ |
396abba2 | 628 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 629 | | BATL_PP_RW \ |
396abba2 JH |
630 | | BATL_MEMCOHERENCE) |
631 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
632 | | BATU_BL_256M \ | |
633 | | BATU_VS \ | |
634 | | BATU_VP) | |
2ad6b513 | 635 | |
7a78f148 | 636 | /* PCI */ |
2ad6b513 | 637 | #ifdef CONFIG_PCI |
396abba2 | 638 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 639 | | BATL_PP_RW \ |
396abba2 JH |
640 | | BATL_MEMCOHERENCE) |
641 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
642 | | BATU_BL_256M \ | |
643 | | BATU_VS \ | |
644 | | BATU_VP) | |
645 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 646 | | BATL_PP_RW \ |
396abba2 JH |
647 | | BATL_CACHEINHIBIT \ |
648 | | BATL_GUARDEDSTORAGE) | |
649 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
650 | | BATU_BL_256M \ | |
651 | | BATU_VS \ | |
652 | | BATU_VP) | |
2ad6b513 | 653 | #else |
6d0f6bcf JCPV |
654 | #define CONFIG_SYS_IBAT1L 0 |
655 | #define CONFIG_SYS_IBAT1U 0 | |
656 | #define CONFIG_SYS_IBAT2L 0 | |
657 | #define CONFIG_SYS_IBAT2U 0 | |
2ad6b513 TT |
658 | #endif |
659 | ||
660 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 | 661 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 662 | | BATL_PP_RW \ |
396abba2 JH |
663 | | BATL_MEMCOHERENCE) |
664 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
665 | | BATU_BL_256M \ | |
666 | | BATU_VS \ | |
667 | | BATU_VP) | |
668 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 669 | | BATL_PP_RW \ |
396abba2 JH |
670 | | BATL_CACHEINHIBIT \ |
671 | | BATL_GUARDEDSTORAGE) | |
672 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
673 | | BATU_BL_256M \ | |
674 | | BATU_VS \ | |
675 | | BATU_VP) | |
2ad6b513 | 676 | #else |
6d0f6bcf JCPV |
677 | #define CONFIG_SYS_IBAT3L 0 |
678 | #define CONFIG_SYS_IBAT3U 0 | |
679 | #define CONFIG_SYS_IBAT4L 0 | |
680 | #define CONFIG_SYS_IBAT4U 0 | |
2ad6b513 TT |
681 | #endif |
682 | ||
683 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
396abba2 | 684 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 685 | | BATL_PP_RW \ |
396abba2 JH |
686 | | BATL_CACHEINHIBIT \ |
687 | | BATL_GUARDEDSTORAGE) | |
688 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
689 | | BATU_BL_256M \ | |
690 | | BATU_VS \ | |
691 | | BATU_VP) | |
2ad6b513 TT |
692 | |
693 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
396abba2 | 694 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 | 695 | | BATL_PP_RW \ |
396abba2 JH |
696 | | BATL_MEMCOHERENCE \ |
697 | | BATL_GUARDEDSTORAGE) | |
698 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ | |
699 | | BATU_BL_256M \ | |
700 | | BATU_VS \ | |
701 | | BATU_VP) | |
6d0f6bcf JCPV |
702 | |
703 | #define CONFIG_SYS_IBAT7L 0 | |
704 | #define CONFIG_SYS_IBAT7U 0 | |
705 | ||
706 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
707 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
708 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
709 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
710 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
711 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
712 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
713 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
714 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
715 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
716 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
717 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
718 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
719 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
720 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
721 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2ad6b513 | 722 | |
8ea5499a | 723 | #if defined(CONFIG_CMD_KGDB) |
2ad6b513 | 724 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
2ad6b513 TT |
725 | #endif |
726 | ||
727 | ||
728 | /* | |
729 | * Environment Configuration | |
730 | */ | |
731 | #define CONFIG_ENV_OVERWRITE | |
732 | ||
396abba2 | 733 | #define CONFIG_NETDEV "eth0" |
2ad6b513 | 734 | |
7a78f148 | 735 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 736 | #define CONFIG_HOSTNAME "mpc8349emitx" |
7a78f148 | 737 | #else |
396abba2 | 738 | #define CONFIG_HOSTNAME "mpc8349emitxgp" |
be5e6181 TT |
739 | #endif |
740 | ||
7a78f148 | 741 | /* Default path and filenames */ |
8b3637c6 | 742 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 743 | #define CONFIG_BOOTFILE "uImage" |
396abba2 JH |
744 | /* U-Boot image on TFTP server */ |
745 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
2ad6b513 | 746 | |
7a78f148 | 747 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 748 | #define CONFIG_FDTFILE "mpc8349emitx.dtb" |
2ad6b513 | 749 | #else |
396abba2 | 750 | #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" |
2ad6b513 TT |
751 | #endif |
752 | ||
05f91a65 | 753 | #define CONFIG_BOOTDELAY 6 |
7a78f148 | 754 | |
98883332 TT |
755 | #define CONFIG_BOOTARGS \ |
756 | "root=/dev/nfs rw" \ | |
5368c55d MV |
757 | " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ |
758 | " ip=" __stringify(CONFIG_IPADDR) ":" \ | |
759 | __stringify(CONFIG_SERVERIP) ":" \ | |
760 | __stringify(CONFIG_GATEWAYIP) ":" \ | |
761 | __stringify(CONFIG_NETMASK) ":" \ | |
396abba2 | 762 | CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ |
5368c55d | 763 | " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) |
98883332 | 764 | |
dd520bf3 | 765 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 766 | "console=" __stringify(CONFIG_CONSOLE) "\0" \ |
396abba2 JH |
767 | "netdev=" CONFIG_NETDEV "\0" \ |
768 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
53677ef1 | 769 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
770 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
771 | " +$filesize; " \ | |
772 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
773 | " +$filesize; " \ | |
774 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
775 | " $filesize; " \ | |
776 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
777 | " +$filesize; " \ | |
778 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
779 | " $filesize\0" \ | |
05f91a65 | 780 | "fdtaddr=780000\0" \ |
396abba2 | 781 | "fdtfile=" CONFIG_FDTFILE "\0" |
bf0b542d | 782 | |
dd520bf3 | 783 | #define CONFIG_NFSBOOTCOMMAND \ |
7a78f148 | 784 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
396abba2 | 785 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ |
7a78f148 TT |
786 | " console=$console,$baudrate $othbootargs; " \ |
787 | "tftp $loadaddr $bootfile;" \ | |
788 | "tftp $fdtaddr $fdtfile;" \ | |
789 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d | 790 | |
dd520bf3 | 791 | #define CONFIG_RAMBOOTCOMMAND \ |
7a78f148 TT |
792 | "setenv bootargs root=/dev/ram rw" \ |
793 | " console=$console,$baudrate $othbootargs; " \ | |
794 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
795 | "tftp $loadaddr $bootfile;" \ | |
796 | "tftp $fdtaddr $fdtfile;" \ | |
797 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
2ad6b513 | 798 | |
2ad6b513 | 799 | #endif |