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Commit | Line | Data |
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5f820439 | 1 | /* |
d37be07e | 2 | * Copyright (C) 2006,2011 Freescale Semiconductor, Inc. |
5f820439 DL |
3 | * |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
5f820439 DL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
5f820439 DL |
12 | /* |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
16 | #define CONFIG_QE 1 /* Has QE */ | |
0f898604 | 17 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
5f820439 DL |
18 | #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
19 | #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ | |
2ae18241 WD |
20 | |
21 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
22 | ||
14778585 TL |
23 | #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ |
24 | #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ | |
5f820439 DL |
25 | |
26 | /* | |
27 | * System Clock Setup | |
28 | */ | |
6be55ee2 JH |
29 | #ifdef CONFIG_CLKIN_33MHZ |
30 | #ifdef CONFIG_PCISLAVE | |
31 | #define CONFIG_83XX_PCICLK 33330000 /* in HZ */ | |
32 | #else | |
33 | #define CONFIG_83XX_CLKIN 33330000 /* in Hz */ | |
34 | #endif | |
35 | ||
36 | #ifndef CONFIG_SYS_CLK_FREQ | |
37 | #define CONFIG_SYS_CLK_FREQ 33330000 | |
38 | #endif | |
39 | ||
40 | #elif defined(CONFIG_CLKIN_66MHZ) | |
5f820439 DL |
41 | #ifdef CONFIG_PCISLAVE |
42 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
43 | #else | |
44 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
45 | #endif | |
46 | ||
47 | #ifndef CONFIG_SYS_CLK_FREQ | |
48 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
49 | #endif | |
6be55ee2 JH |
50 | #else |
51 | #error Unknown oscillator frequency. | |
52 | #endif | |
5f820439 DL |
53 | |
54 | /* | |
55 | * Hardware Reset Configuration Word | |
56 | */ | |
6be55ee2 JH |
57 | #ifdef CONFIG_CLKIN_33MHZ |
58 | #define CONFIG_SYS_HRCW_LOW (\ | |
59 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
60 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
61 | HRCWL_CSB_TO_CLKIN_8X1 |\ | |
62 | HRCWL_VCO_1X2 |\ | |
63 | HRCWL_CE_PLL_VCO_DIV_4 |\ | |
64 | HRCWL_CE_PLL_DIV_1X1 |\ | |
65 | HRCWL_CE_TO_PLL_1X15 |\ | |
66 | HRCWL_CORE_TO_CSB_2X1) | |
67 | #elif defined(CONFIG_CLKIN_66MHZ) | |
6d0f6bcf | 68 | #define CONFIG_SYS_HRCW_LOW (\ |
5f820439 DL |
69 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
70 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
71 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
72 | HRCWL_VCO_1X2 |\ | |
73 | HRCWL_CE_PLL_VCO_DIV_4 |\ | |
74 | HRCWL_CE_PLL_DIV_1X1 |\ | |
75 | HRCWL_CE_TO_PLL_1X6 |\ | |
76 | HRCWL_CORE_TO_CSB_2X1) | |
6be55ee2 | 77 | #endif |
5f820439 DL |
78 | |
79 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 80 | #define CONFIG_SYS_HRCW_HIGH (\ |
5f820439 DL |
81 | HRCWH_PCI_AGENT |\ |
82 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
83 | HRCWH_PCICKDRV_DISABLE |\ | |
84 | HRCWH_CORE_ENABLE |\ | |
85 | HRCWH_FROM_0XFFF00100 |\ | |
86 | HRCWH_BOOTSEQ_DISABLE |\ | |
87 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
88 | HRCWH_ROM_LOC_LOCAL_16BIT) | |
89 | #else | |
6d0f6bcf | 90 | #define CONFIG_SYS_HRCW_HIGH (\ |
5f820439 DL |
91 | HRCWH_PCI_HOST |\ |
92 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
93 | HRCWH_PCICKDRV_ENABLE |\ | |
94 | HRCWH_CORE_ENABLE |\ | |
95 | HRCWH_FROM_0X00000100 |\ | |
96 | HRCWH_BOOTSEQ_DISABLE |\ | |
97 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
98 | HRCWH_ROM_LOC_LOCAL_16BIT) | |
99 | #endif | |
100 | ||
101 | /* | |
102 | * System IO Config | |
103 | */ | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_SICRH 0x00000000 |
105 | #define CONFIG_SYS_SICRL 0x40000000 | |
5f820439 DL |
106 | |
107 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
14778585 | 108 | #define CONFIG_BOARD_EARLY_INIT_R |
5f820439 DL |
109 | |
110 | /* | |
111 | * IMMR new address | |
112 | */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_IMMR 0xE0000000 |
5f820439 DL |
114 | |
115 | /* | |
116 | * DDR Setup | |
117 | */ | |
1f5cb793 JH |
118 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
119 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
120 | /* + 256M */ | |
121 | #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
6d0f6bcf | 122 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
1f5cb793 JH |
123 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
124 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
5f820439 | 125 | |
6d0f6bcf | 126 | #define CONFIG_SYS_83XX_DDR_USES_CS0 |
bf0b542d | 127 | |
b110f40b | 128 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
5f820439 DL |
129 | #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
130 | ||
b110f40b XX |
131 | /* |
132 | * DDRCDR - DDR Control Driver Register | |
133 | */ | |
6d0f6bcf | 134 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
b110f40b | 135 | |
5f820439 DL |
136 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
137 | #if defined(CONFIG_SPD_EEPROM) | |
138 | /* | |
139 | * Determine DDR configuration from I2C interface. | |
140 | */ | |
141 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ | |
142 | #else | |
143 | /* | |
144 | * Manually set up DDR parameters | |
145 | */ | |
6d0f6bcf | 146 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
b110f40b | 147 | #if defined(CONFIG_DDR_II) |
6d0f6bcf | 148 | #define CONFIG_SYS_DDRCDR 0x80080001 |
1f5cb793 | 149 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
6d0f6bcf | 150 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102 |
1f5cb793 JH |
151 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
152 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
153 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
154 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
155 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_DDR_MODE 0x47d00432 |
157 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
1f5cb793 | 158 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
160 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
b110f40b | 161 | #else |
2e651b24 JH |
162 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
163 | | CSCONFIG_ROW_BIT_13 \ | |
164 | | CSCONFIG_COL_BIT_9) | |
165 | #define CONFIG_SYS_DDR_CS1_CONFIG CONFIG_SYS_DDR_CS0_CONFIG | |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ |
167 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ | |
1f5cb793 JH |
168 | #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ |
169 | #define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ |
5f820439 | 171 | #endif |
b110f40b | 172 | #endif |
5f820439 DL |
173 | |
174 | /* | |
175 | * Memory test | |
176 | */ | |
6d0f6bcf JCPV |
177 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
178 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
179 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
5f820439 DL |
180 | |
181 | /* | |
182 | * The reserved memory | |
183 | */ | |
184 | ||
14d0a02a | 185 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5f820439 | 186 | |
6d0f6bcf JCPV |
187 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
188 | #define CONFIG_SYS_RAMBOOT | |
5f820439 | 189 | #else |
6d0f6bcf | 190 | #undef CONFIG_SYS_RAMBOOT |
5f820439 DL |
191 | #endif |
192 | ||
6d0f6bcf | 193 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
1f5cb793 | 194 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 195 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
5f820439 DL |
196 | |
197 | /* | |
198 | * Initial RAM Base Address Setup | |
199 | */ | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
201 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 202 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
1f5cb793 JH |
203 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
204 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
5f820439 DL |
205 | |
206 | /* | |
207 | * Local Bus Configuration & Clock Setup | |
208 | */ | |
c7190f02 KP |
209 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
210 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
1f5cb793 | 211 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
5f820439 DL |
212 | |
213 | /* | |
214 | * FLASH on the Local Bus | |
215 | */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
1f5cb793 | 217 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
219 | #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
1f5cb793 JH |
220 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
221 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
5f820439 | 222 | |
1f5cb793 JH |
223 | /* Window base at flash base */ |
224 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 225 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
5f820439 | 226 | |
1f5cb793 | 227 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
228 | | BR_PS_16 /* 16 bit port */ \ |
229 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
230 | | BR_V) /* valid */ | |
231 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
232 | | OR_GPCM_XAM \ | |
1f5cb793 JH |
233 | | OR_GPCM_CSNT \ |
234 | | OR_GPCM_ACS_DIV2 \ | |
235 | | OR_GPCM_XACS \ | |
236 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
237 | | OR_GPCM_TRLX_SET \ |
238 | | OR_GPCM_EHTR_SET \ | |
1f5cb793 | 239 | | OR_GPCM_EAD) |
5f820439 | 240 | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
242 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
5f820439 | 243 | |
6d0f6bcf | 244 | #undef CONFIG_SYS_FLASH_CHECKSUM |
5f820439 DL |
245 | |
246 | /* | |
247 | * BCSR on the Local Bus | |
248 | */ | |
1f5cb793 JH |
249 | #define CONFIG_SYS_BCSR 0xF8000000 |
250 | /* Access window base at BCSR base */ | |
251 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
252 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) |
253 | ||
254 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
255 | | BR_PS_8 \ | |
256 | | BR_MS_GPCM \ | |
257 | | BR_V) | |
258 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
259 | | OR_GPCM_XAM \ | |
260 | | OR_GPCM_CSNT \ | |
261 | | OR_GPCM_XACS \ | |
262 | | OR_GPCM_SCY_15 \ | |
263 | | OR_GPCM_TRLX_SET \ | |
264 | | OR_GPCM_EHTR_SET \ | |
265 | | OR_GPCM_EAD) | |
266 | /* 0xFFFFE9F7 */ | |
5f820439 DL |
267 | |
268 | /* | |
269 | * SDRAM on the Local Bus | |
270 | */ | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ |
272 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
5f820439 | 273 | |
6d0f6bcf | 274 | #define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */ |
5f820439 | 275 | |
6d0f6bcf | 276 | #ifdef CONFIG_SYS_LB_SDRAM |
5c2ff323 | 277 | #define CONFIG_SYS_LBLAWBAR2 0 |
7d6a0982 | 278 | #define CONFIG_SYS_LBLAWAR2 (LBLAWAR_EN | LBLAWAR_64MB) |
5f820439 DL |
279 | |
280 | /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ | |
281 | /* | |
282 | * Base Register 2 and Option Register 2 configure SDRAM. | |
5f820439 DL |
283 | * |
284 | * For BR2, need: | |
5c2ff323 | 285 | * Base address = BR[0:16] = dynamic |
5f820439 DL |
286 | * port size = 32-bits = BR2[19:20] = 11 |
287 | * no parity checking = BR2[21:22] = 00 | |
288 | * SDRAM for MSEL = BR2[24:26] = 011 | |
289 | * Valid = BR[31] = 1 | |
290 | * | |
dd520bf3 | 291 | * 0 4 8 12 16 20 24 28 |
5c2ff323 | 292 | * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 |
5f820439 DL |
293 | */ |
294 | ||
7d6a0982 JH |
295 | /* Port size=32bit, MSEL=DRAM */ |
296 | #define CONFIG_SYS_BR2 (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */ | |
5f820439 DL |
297 | |
298 | /* | |
6d0f6bcf | 299 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
5f820439 DL |
300 | * |
301 | * For OR2, need: | |
302 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
303 | * XAM, OR2[17:18] = 11 | |
304 | * 9 columns OR2[19-21] = 010 | |
dd520bf3 | 305 | * 13 rows OR2[23-25] = 100 |
5f820439 DL |
306 | * EAD set for extra time OR[31] = 1 |
307 | * | |
dd520bf3 | 308 | * 0 4 8 12 16 20 24 28 |
5f820439 DL |
309 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
310 | */ | |
311 | ||
7d6a0982 JH |
312 | #define CONFIG_SYS_OR2 (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ |
313 | | OR_SDRAM_XAM \ | |
314 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
315 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
316 | | OR_SDRAM_EAD) | |
317 | /* 0xFC006901 */ | |
5f820439 | 318 | |
1f5cb793 JH |
319 | /* LB sdram refresh timer, about 6us */ |
320 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
321 | /* LB refresh timer prescal, 266MHz/32 */ | |
322 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
5f820439 | 323 | |
6d0f6bcf | 324 | #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 |
5f820439 DL |
325 | |
326 | /* | |
327 | * SDRAM Controller configuration sequence. | |
328 | */ | |
540dcf1c KG |
329 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
330 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
331 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
332 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
333 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
5f820439 DL |
334 | |
335 | #endif | |
336 | ||
337 | /* | |
7d6a0982 | 338 | * Windows to access Platform I/O Boards (PIB) via local bus |
5f820439 | 339 | */ |
7d6a0982 JH |
340 | #define CONFIG_SYS_PIB_BASE 0xF8008000 |
341 | #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) | |
342 | ||
343 | /* [RFC] This LBLAW only covers the 2nd window (CS5) */ | |
344 | #define CONFIG_SYS_LBLAWBAR3_PRELIM \ | |
345 | CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE | |
346 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) | |
5f820439 DL |
347 | |
348 | /* | |
349 | * CS4 on Local Bus, to PIB | |
350 | */ | |
7d6a0982 JH |
351 | /* CS4 base address at 0xf8008000 */ |
352 | #define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \ | |
353 | | BR_PS_8 \ | |
354 | | BR_MS_GPCM \ | |
355 | | BR_V) | |
356 | /* 0xF8008801 */ | |
357 | #define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \ | |
358 | | OR_GPCM_XAM \ | |
359 | | OR_GPCM_CSNT \ | |
360 | | OR_GPCM_XACS \ | |
361 | | OR_GPCM_SCY_15 \ | |
362 | | OR_GPCM_TRLX_SET \ | |
363 | | OR_GPCM_EHTR_SET \ | |
364 | | OR_GPCM_EAD) | |
365 | /* 0xffffe9f7 */ | |
5f820439 DL |
366 | |
367 | /* | |
368 | * CS5 on Local Bus, to PIB | |
369 | */ | |
7d6a0982 JH |
370 | /* CS5 base address at 0xf8010000 */ |
371 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + \ | |
372 | CONFIG_SYS_PIB_WINDOW_SIZE) \ | |
373 | | BR_PS_8 \ | |
374 | | BR_MS_GPCM \ | |
375 | | BR_V) | |
376 | /* 0xF8010801 */ | |
377 | #define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \ | |
378 | | OR_GPCM_XAM \ | |
379 | | OR_GPCM_CSNT \ | |
380 | | OR_GPCM_XACS \ | |
381 | | OR_GPCM_SCY_15 \ | |
382 | | OR_GPCM_TRLX_SET \ | |
383 | | OR_GPCM_EHTR_SET \ | |
384 | | OR_GPCM_EAD) | |
385 | /* 0xffffe9f7 */ | |
5f820439 DL |
386 | |
387 | /* | |
388 | * Serial Port | |
389 | */ | |
390 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_NS16550 |
392 | #define CONFIG_SYS_NS16550_SERIAL | |
393 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
394 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5f820439 | 395 | |
6d0f6bcf | 396 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
1f5cb793 | 397 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
5f820439 | 398 | |
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
400 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
5f820439 | 401 | |
22d71a71 | 402 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 403 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
5f820439 | 404 | /* Use the HUSH parser */ |
6d0f6bcf | 405 | #define CONFIG_SYS_HUSH_PARSER |
5f820439 | 406 | |
bf0b542d | 407 | /* pass open firmware flat tree */ |
213bf8c8 | 408 | #define CONFIG_OF_LIBFDT 1 |
bf0b542d | 409 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 410 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
bf0b542d | 411 | |
5f820439 | 412 | /* I2C */ |
00f792e0 HS |
413 | #define CONFIG_SYS_I2C |
414 | #define CONFIG_SYS_I2C_FSL | |
415 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
416 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
417 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
418 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } | |
5f820439 DL |
419 | |
420 | /* | |
421 | * Config on-board RTC | |
422 | */ | |
423 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 424 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
5f820439 DL |
425 | |
426 | /* | |
427 | * General PCI | |
428 | * Addresses are mapped 1-1. | |
429 | */ | |
9993e196 KP |
430 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
431 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
432 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
433 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
434 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
435 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
436 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
437 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 | |
438 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
5f820439 | 439 | |
6d0f6bcf JCPV |
440 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
441 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
442 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
5f820439 DL |
443 | |
444 | ||
445 | #ifdef CONFIG_PCI | |
842033e6 | 446 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5f820439 | 447 | |
5f820439 | 448 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
9993e196 | 449 | #define CONFIG_83XX_PCI_STREAMING |
5f820439 DL |
450 | |
451 | #undef CONFIG_EEPRO100 | |
452 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 453 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
5f820439 DL |
454 | |
455 | #endif /* CONFIG_PCI */ | |
456 | ||
457 | ||
da6eea0f AV |
458 | #define CONFIG_HWCONFIG 1 |
459 | ||
7737d5c6 DL |
460 | /* |
461 | * QE UEC ethernet configuration | |
462 | */ | |
463 | #define CONFIG_UEC_ETH | |
78b7a8ef | 464 | #define CONFIG_ETHPRIME "UEC0" |
7737d5c6 DL |
465 | #define CONFIG_PHY_MODE_NEED_CHANGE |
466 | ||
467 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
468 | ||
469 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
470 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
471 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
472 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 | |
473 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
474 | #define CONFIG_SYS_UEC1_PHY_ADDR 0 | |
865ff856 | 475 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 476 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
7737d5c6 DL |
477 | #endif |
478 | ||
479 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
480 | ||
481 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
483 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
484 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 | |
485 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
486 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
865ff856 | 487 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 488 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
7737d5c6 DL |
489 | #endif |
490 | ||
5f820439 DL |
491 | /* |
492 | * Environment | |
493 | */ | |
494 | ||
6d0f6bcf | 495 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 496 | #define CONFIG_ENV_IS_IN_FLASH 1 |
1f5cb793 JH |
497 | #define CONFIG_ENV_ADDR \ |
498 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
499 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
500 | #define CONFIG_ENV_SIZE 0x2000 | |
5f820439 | 501 | #else |
1f5cb793 | 502 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 503 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 504 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 505 | #define CONFIG_ENV_SIZE 0x2000 |
5f820439 DL |
506 | #endif |
507 | ||
508 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 509 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5f820439 | 510 | |
659e2f67 JL |
511 | /* |
512 | * BOOTP options | |
513 | */ | |
514 | #define CONFIG_BOOTP_BOOTFILESIZE | |
515 | #define CONFIG_BOOTP_BOOTPATH | |
516 | #define CONFIG_BOOTP_GATEWAY | |
517 | #define CONFIG_BOOTP_HOSTNAME | |
518 | ||
519 | ||
8ea5499a JL |
520 | /* |
521 | * Command line configuration. | |
522 | */ | |
523 | #include <config_cmd_default.h> | |
524 | ||
525 | #define CONFIG_CMD_PING | |
526 | #define CONFIG_CMD_I2C | |
527 | #define CONFIG_CMD_ASKENV | |
b5cdd7df | 528 | #define CONFIG_CMD_SDRAM |
8ea5499a | 529 | |
5f820439 | 530 | #if defined(CONFIG_PCI) |
8ea5499a | 531 | #define CONFIG_CMD_PCI |
5f820439 | 532 | #endif |
8ea5499a | 533 | |
6d0f6bcf | 534 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 535 | #undef CONFIG_CMD_SAVEENV |
8ea5499a | 536 | #undef CONFIG_CMD_LOADS |
5f820439 DL |
537 | #endif |
538 | ||
5f820439 DL |
539 | |
540 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
541 | ||
542 | /* | |
543 | * Miscellaneous configurable options | |
544 | */ | |
6d0f6bcf JCPV |
545 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
546 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
547 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
5f820439 | 548 | |
8ea5499a | 549 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 550 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5f820439 | 551 | #else |
6d0f6bcf | 552 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5f820439 DL |
553 | #endif |
554 | ||
1f5cb793 JH |
555 | /* Print Buffer Size */ |
556 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
557 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
558 | /* Boot Argument Buffer Size */ | |
559 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
560 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
5f820439 DL |
561 | |
562 | /* | |
563 | * For booting Linux, the board info and command line data | |
9f530d59 | 564 | * have to be in the first 256 MB of memory, since this is |
5f820439 DL |
565 | * the maximum mapped by the Linux kernel during initialization. |
566 | */ | |
1f5cb793 | 567 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
5f820439 DL |
568 | |
569 | /* | |
570 | * Core HID Setup | |
571 | */ | |
1a2e203b KP |
572 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
573 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
574 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 575 | #define CONFIG_SYS_HID2 HID2_HBE |
5f820439 | 576 | |
5f820439 DL |
577 | /* |
578 | * MMU Setup | |
579 | */ | |
580 | ||
31d82672 | 581 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
d37be07e | 582 | #define CONFIG_BAT_RW |
31d82672 | 583 | |
5c2ff323 | 584 | /* DDR/LBC SDRAM: cacheable */ |
1f5cb793 | 585 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 586 | | BATL_PP_RW \ |
1f5cb793 JH |
587 | | BATL_MEMCOHERENCE) |
588 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
589 | | BATU_BL_256M \ | |
590 | | BATU_VS \ | |
591 | | BATU_VP) | |
6d0f6bcf JCPV |
592 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
593 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
5f820439 DL |
594 | |
595 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
1f5cb793 | 596 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 597 | | BATL_PP_RW \ |
1f5cb793 JH |
598 | | BATL_CACHEINHIBIT \ |
599 | | BATL_GUARDEDSTORAGE) | |
600 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
601 | | BATU_BL_4M \ | |
602 | | BATU_VS \ | |
603 | | BATU_VP) | |
6d0f6bcf JCPV |
604 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
605 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
5f820439 DL |
606 | |
607 | /* BCSR: cache-inhibit and guarded */ | |
1f5cb793 | 608 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \ |
72cd4087 | 609 | | BATL_PP_RW \ |
1f5cb793 JH |
610 | | BATL_CACHEINHIBIT \ |
611 | | BATL_GUARDEDSTORAGE) | |
612 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \ | |
613 | | BATU_BL_128K \ | |
614 | | BATU_VS \ | |
615 | | BATU_VP) | |
6d0f6bcf JCPV |
616 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
617 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
5f820439 DL |
618 | |
619 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
1f5cb793 | 620 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 621 | | BATL_PP_RW \ |
1f5cb793 JH |
622 | | BATL_MEMCOHERENCE) |
623 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | |
624 | | BATU_BL_32M \ | |
625 | | BATU_VS \ | |
626 | | BATU_VP) | |
627 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 628 | | BATL_PP_RW \ |
1f5cb793 JH |
629 | | BATL_CACHEINHIBIT \ |
630 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 631 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
5f820439 | 632 | |
5c2ff323 | 633 | /* DDR/LBC SDRAM next 256M: cacheable */ |
1f5cb793 | 634 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 \ |
72cd4087 | 635 | | BATL_PP_RW \ |
1f5cb793 JH |
636 | | BATL_MEMCOHERENCE) |
637 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 \ | |
638 | | BATU_BL_256M \ | |
639 | | BATU_VS \ | |
640 | | BATU_VP) | |
6d0f6bcf JCPV |
641 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
642 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
5f820439 DL |
643 | |
644 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 645 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
1f5cb793 JH |
646 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
647 | | BATU_BL_128K \ | |
648 | | BATU_VS \ | |
649 | | BATU_VP) | |
6d0f6bcf JCPV |
650 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
651 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
5f820439 DL |
652 | |
653 | #ifdef CONFIG_PCI | |
654 | /* PCI MEM space: cacheable */ | |
1f5cb793 | 655 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ |
72cd4087 | 656 | | BATL_PP_RW \ |
1f5cb793 JH |
657 | | BATL_MEMCOHERENCE) |
658 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | |
659 | | BATU_BL_256M \ | |
660 | | BATU_VS \ | |
661 | | BATU_VP) | |
6d0f6bcf JCPV |
662 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
663 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
5f820439 | 664 | /* PCI MMIO space: cache-inhibit and guarded */ |
1f5cb793 | 665 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
72cd4087 | 666 | | BATL_PP_RW \ |
1f5cb793 JH |
667 | | BATL_CACHEINHIBIT \ |
668 | | BATL_GUARDEDSTORAGE) | |
669 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ | |
670 | | BATU_BL_256M \ | |
671 | | BATU_VS \ | |
672 | | BATU_VP) | |
6d0f6bcf JCPV |
673 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
674 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5f820439 | 675 | #else |
6d0f6bcf JCPV |
676 | #define CONFIG_SYS_IBAT6L (0) |
677 | #define CONFIG_SYS_IBAT6U (0) | |
678 | #define CONFIG_SYS_IBAT7L (0) | |
679 | #define CONFIG_SYS_IBAT7U (0) | |
680 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
681 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
682 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
683 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5f820439 DL |
684 | #endif |
685 | ||
8ea5499a | 686 | #if defined(CONFIG_CMD_KGDB) |
5f820439 DL |
687 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
688 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
689 | #endif | |
690 | ||
691 | /* | |
692 | * Environment Configuration | |
693 | */ | |
694 | ||
695 | #define CONFIG_ENV_OVERWRITE | |
696 | ||
697 | #if defined(CONFIG_UEC_ETH) | |
977b5758 | 698 | #define CONFIG_HAS_ETH0 |
5f820439 | 699 | #define CONFIG_HAS_ETH1 |
5f820439 DL |
700 | #endif |
701 | ||
dd520bf3 | 702 | #define CONFIG_BAUDRATE 115200 |
5f820439 | 703 | |
79f516bc | 704 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
5f820439 | 705 | |
dd520bf3 WD |
706 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
707 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
5f820439 | 708 | |
dd520bf3 | 709 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
1f5cb793 JH |
710 | "netdev=eth0\0" \ |
711 | "consoledev=ttyS0\0" \ | |
712 | "ramdiskaddr=1000000\0" \ | |
713 | "ramdiskfile=ramfs.83xx\0" \ | |
714 | "fdtaddr=780000\0" \ | |
715 | "fdtfile=mpc836x_mds.dtb\0" \ | |
716 | "" | |
5f820439 | 717 | |
dd520bf3 | 718 | #define CONFIG_NFSBOOTCOMMAND \ |
1f5cb793 JH |
719 | "setenv bootargs root=/dev/nfs rw " \ |
720 | "nfsroot=$serverip:$rootpath " \ | |
721 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
722 | "$netdev:off " \ | |
723 | "console=$consoledev,$baudrate $othbootargs;" \ | |
724 | "tftp $loadaddr $bootfile;" \ | |
725 | "tftp $fdtaddr $fdtfile;" \ | |
726 | "bootm $loadaddr - $fdtaddr" | |
5f820439 | 727 | |
bf0b542d | 728 | #define CONFIG_RAMBOOTCOMMAND \ |
1f5cb793 JH |
729 | "setenv bootargs root=/dev/ram rw " \ |
730 | "console=$consoledev,$baudrate $othbootargs;" \ | |
731 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
732 | "tftp $loadaddr $bootfile;" \ | |
733 | "tftp $fdtaddr $fdtfile;" \ | |
734 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
bf0b542d | 735 | |
5f820439 DL |
736 | |
737 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
738 | ||
739 | #endif /* __CONFIG_H */ |