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5f820439 DL |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
dd520bf3 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
5f820439 DL |
14 | * GNU General Public License for more details. |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #ifndef __CONFIG_H | |
23 | #define __CONFIG_H | |
24 | ||
5f820439 DL |
25 | /* |
26 | * High Level Configuration Options | |
27 | */ | |
28 | #define CONFIG_E300 1 /* E300 family */ | |
29 | #define CONFIG_QE 1 /* Has QE */ | |
0f898604 | 30 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
5f820439 DL |
31 | #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
32 | #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ | |
14778585 TL |
33 | #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ |
34 | #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ | |
5f820439 DL |
35 | |
36 | /* | |
37 | * System Clock Setup | |
38 | */ | |
39 | #ifdef CONFIG_PCISLAVE | |
40 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
41 | #else | |
42 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
43 | #endif | |
44 | ||
45 | #ifndef CONFIG_SYS_CLK_FREQ | |
46 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
47 | #endif | |
48 | ||
49 | /* | |
50 | * Hardware Reset Configuration Word | |
51 | */ | |
6d0f6bcf | 52 | #define CONFIG_SYS_HRCW_LOW (\ |
5f820439 DL |
53 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
54 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
55 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
56 | HRCWL_VCO_1X2 |\ | |
57 | HRCWL_CE_PLL_VCO_DIV_4 |\ | |
58 | HRCWL_CE_PLL_DIV_1X1 |\ | |
59 | HRCWL_CE_TO_PLL_1X6 |\ | |
60 | HRCWL_CORE_TO_CSB_2X1) | |
61 | ||
62 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 63 | #define CONFIG_SYS_HRCW_HIGH (\ |
5f820439 DL |
64 | HRCWH_PCI_AGENT |\ |
65 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
66 | HRCWH_PCICKDRV_DISABLE |\ | |
67 | HRCWH_CORE_ENABLE |\ | |
68 | HRCWH_FROM_0XFFF00100 |\ | |
69 | HRCWH_BOOTSEQ_DISABLE |\ | |
70 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
71 | HRCWH_ROM_LOC_LOCAL_16BIT) | |
72 | #else | |
6d0f6bcf | 73 | #define CONFIG_SYS_HRCW_HIGH (\ |
5f820439 DL |
74 | HRCWH_PCI_HOST |\ |
75 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
76 | HRCWH_PCICKDRV_ENABLE |\ | |
77 | HRCWH_CORE_ENABLE |\ | |
78 | HRCWH_FROM_0X00000100 |\ | |
79 | HRCWH_BOOTSEQ_DISABLE |\ | |
80 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
81 | HRCWH_ROM_LOC_LOCAL_16BIT) | |
82 | #endif | |
83 | ||
84 | /* | |
85 | * System IO Config | |
86 | */ | |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_SICRH 0x00000000 |
88 | #define CONFIG_SYS_SICRL 0x40000000 | |
5f820439 DL |
89 | |
90 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
14778585 | 91 | #define CONFIG_BOARD_EARLY_INIT_R |
5f820439 DL |
92 | |
93 | /* | |
94 | * IMMR new address | |
95 | */ | |
6d0f6bcf | 96 | #define CONFIG_SYS_IMMR 0xE0000000 |
5f820439 DL |
97 | |
98 | /* | |
99 | * DDR Setup | |
100 | */ | |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
102 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
5c2ff323 | 103 | #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */ |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
105 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
b110f40b | 106 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
5f820439 | 107 | |
6d0f6bcf | 108 | #define CONFIG_SYS_83XX_DDR_USES_CS0 |
bf0b542d | 109 | |
b110f40b | 110 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
5f820439 DL |
111 | #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
112 | ||
b110f40b XX |
113 | /* |
114 | * DDRCDR - DDR Control Driver Register | |
115 | */ | |
6d0f6bcf | 116 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
b110f40b | 117 | |
5f820439 DL |
118 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
119 | #if defined(CONFIG_SPD_EEPROM) | |
120 | /* | |
121 | * Determine DDR configuration from I2C interface. | |
122 | */ | |
123 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ | |
124 | #else | |
125 | /* | |
126 | * Manually set up DDR parameters | |
127 | */ | |
6d0f6bcf | 128 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
b110f40b | 129 | #if defined(CONFIG_DDR_II) |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_DDRCDR 0x80080001 |
131 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f | |
132 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102 | |
133 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 | |
134 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
135 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
136 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
137 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
138 | #define CONFIG_SYS_DDR_MODE 0x47d00432 | |
139 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
140 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 | |
141 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 | |
142 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
b110f40b | 143 | #else |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) |
145 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ | |
146 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ | |
147 | #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ | |
148 | #define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ | |
149 | #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ | |
5f820439 | 150 | #endif |
b110f40b | 151 | #endif |
5f820439 DL |
152 | |
153 | /* | |
154 | * Memory test | |
155 | */ | |
6d0f6bcf JCPV |
156 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
157 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
158 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
5f820439 DL |
159 | |
160 | /* | |
161 | * The reserved memory | |
162 | */ | |
163 | ||
6d0f6bcf | 164 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
5f820439 | 165 | |
6d0f6bcf JCPV |
166 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
167 | #define CONFIG_SYS_RAMBOOT | |
5f820439 | 168 | #else |
6d0f6bcf | 169 | #undef CONFIG_SYS_RAMBOOT |
5f820439 DL |
170 | #endif |
171 | ||
6d0f6bcf | 172 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
4a9932a4 | 173 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
6d0f6bcf | 174 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
5f820439 DL |
175 | |
176 | /* | |
177 | * Initial RAM Base Address Setup | |
178 | */ | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
180 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
181 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
182 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
183 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
5f820439 DL |
184 | |
185 | /* | |
186 | * Local Bus Configuration & Clock Setup | |
187 | */ | |
c7190f02 KP |
188 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
189 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 190 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
5f820439 DL |
191 | |
192 | /* | |
193 | * FLASH on the Local Bus | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 196 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
198 | #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
199 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
82e45a20 | 200 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
5f820439 | 201 | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ |
203 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
5f820439 | 204 | |
6d0f6bcf | 205 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ |
5f820439 DL |
206 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ |
207 | BR_V) /* valid */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
f9023afb | 209 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ |
b110f40b | 210 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
5f820439 | 211 | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
213 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
5f820439 | 214 | |
6d0f6bcf | 215 | #undef CONFIG_SYS_FLASH_CHECKSUM |
5f820439 DL |
216 | |
217 | /* | |
218 | * BCSR on the Local Bus | |
219 | */ | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_BCSR 0xF8000000 |
221 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ | |
222 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */ | |
5f820439 | 223 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ |
225 | #define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ | |
5f820439 DL |
226 | |
227 | /* | |
228 | * SDRAM on the Local Bus | |
229 | */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ |
231 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
5f820439 | 232 | |
6d0f6bcf | 233 | #define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */ |
5f820439 | 234 | |
6d0f6bcf | 235 | #ifdef CONFIG_SYS_LB_SDRAM |
5c2ff323 AV |
236 | #define CONFIG_SYS_LBLAWBAR2 0 |
237 | #define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */ | |
5f820439 DL |
238 | |
239 | /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ | |
240 | /* | |
241 | * Base Register 2 and Option Register 2 configure SDRAM. | |
5f820439 DL |
242 | * |
243 | * For BR2, need: | |
5c2ff323 | 244 | * Base address = BR[0:16] = dynamic |
5f820439 DL |
245 | * port size = 32-bits = BR2[19:20] = 11 |
246 | * no parity checking = BR2[21:22] = 00 | |
247 | * SDRAM for MSEL = BR2[24:26] = 011 | |
248 | * Valid = BR[31] = 1 | |
249 | * | |
dd520bf3 | 250 | * 0 4 8 12 16 20 24 28 |
5c2ff323 | 251 | * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 |
5f820439 DL |
252 | */ |
253 | ||
5c2ff323 | 254 | #define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */ |
5f820439 DL |
255 | |
256 | /* | |
6d0f6bcf | 257 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
5f820439 DL |
258 | * |
259 | * For OR2, need: | |
260 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
261 | * XAM, OR2[17:18] = 11 | |
262 | * 9 columns OR2[19-21] = 010 | |
dd520bf3 | 263 | * 13 rows OR2[23-25] = 100 |
5f820439 DL |
264 | * EAD set for extra time OR[31] = 1 |
265 | * | |
dd520bf3 | 266 | * 0 4 8 12 16 20 24 28 |
5f820439 DL |
267 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
268 | */ | |
269 | ||
5c2ff323 | 270 | #define CONFIG_SYS_OR2 0xfc006901 |
5f820439 | 271 | |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
273 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
5f820439 | 274 | |
6d0f6bcf | 275 | #define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 |
5f820439 DL |
276 | |
277 | /* | |
278 | * SDRAM Controller configuration sequence. | |
279 | */ | |
540dcf1c KG |
280 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
281 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
282 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
283 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
284 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
5f820439 DL |
285 | |
286 | #endif | |
287 | ||
288 | /* | |
289 | * Windows to access PIB via local bus | |
290 | */ | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */ |
292 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */ | |
5f820439 DL |
293 | |
294 | /* | |
295 | * CS4 on Local Bus, to PIB | |
296 | */ | |
6d0f6bcf JCPV |
297 | #define CONFIG_SYS_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */ |
298 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ | |
5f820439 DL |
299 | |
300 | /* | |
301 | * CS5 on Local Bus, to PIB | |
302 | */ | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */ |
304 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ | |
5f820439 DL |
305 | |
306 | /* | |
307 | * Serial Port | |
308 | */ | |
309 | #define CONFIG_CONS_INDEX 1 | |
310 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_NS16550 |
312 | #define CONFIG_SYS_NS16550_SERIAL | |
313 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
314 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5f820439 | 315 | |
6d0f6bcf | 316 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5f820439 DL |
317 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
318 | ||
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
320 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
5f820439 | 321 | |
22d71a71 | 322 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5f820439 | 323 | /* Use the HUSH parser */ |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_HUSH_PARSER |
325 | #ifdef CONFIG_SYS_HUSH_PARSER | |
326 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
5f820439 DL |
327 | #endif |
328 | ||
bf0b542d | 329 | /* pass open firmware flat tree */ |
213bf8c8 | 330 | #define CONFIG_OF_LIBFDT 1 |
bf0b542d | 331 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 332 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
bf0b542d | 333 | |
5f820439 DL |
334 | /* I2C */ |
335 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
336 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
be5e6181 | 337 | #define CONFIG_FSL_I2C |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
339 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
340 | #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */ | |
341 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
342 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
5f820439 DL |
343 | |
344 | /* | |
345 | * Config on-board RTC | |
346 | */ | |
347 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 348 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
5f820439 DL |
349 | |
350 | /* | |
351 | * General PCI | |
352 | * Addresses are mapped 1-1. | |
353 | */ | |
9993e196 KP |
354 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
355 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
356 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
357 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
358 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
359 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
360 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
361 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 | |
362 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
5f820439 | 363 | |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
365 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
366 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
5f820439 DL |
367 | |
368 | ||
369 | #ifdef CONFIG_PCI | |
370 | ||
371 | #define CONFIG_NET_MULTI | |
372 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
9993e196 | 373 | #define CONFIG_83XX_PCI_STREAMING |
5f820439 DL |
374 | |
375 | #undef CONFIG_EEPRO100 | |
376 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 377 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
5f820439 DL |
378 | |
379 | #endif /* CONFIG_PCI */ | |
380 | ||
381 | ||
382 | #ifndef CONFIG_NET_MULTI | |
383 | #define CONFIG_NET_MULTI 1 | |
384 | #endif | |
385 | ||
da6eea0f AV |
386 | #define CONFIG_HWCONFIG 1 |
387 | ||
7737d5c6 DL |
388 | /* |
389 | * QE UEC ethernet configuration | |
390 | */ | |
391 | #define CONFIG_UEC_ETH | |
711a7946 | 392 | #define CONFIG_ETHPRIME "FSL UEC0" |
7737d5c6 DL |
393 | #define CONFIG_PHY_MODE_NEED_CHANGE |
394 | ||
395 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
396 | ||
397 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
399 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
400 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 | |
401 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
402 | #define CONFIG_SYS_UEC1_PHY_ADDR 0 | |
582c55a0 HS |
403 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID |
404 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 | |
7737d5c6 DL |
405 | #endif |
406 | ||
407 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
408 | ||
409 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
410 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
411 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
412 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 | |
413 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
414 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
582c55a0 HS |
415 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID |
416 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 | |
7737d5c6 DL |
417 | #endif |
418 | ||
5f820439 DL |
419 | /* |
420 | * Environment | |
421 | */ | |
422 | ||
6d0f6bcf | 423 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 424 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 425 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
426 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
427 | #define CONFIG_ENV_SIZE 0x2000 | |
5f820439 | 428 | #else |
6d0f6bcf | 429 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 430 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 431 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 432 | #define CONFIG_ENV_SIZE 0x2000 |
5f820439 DL |
433 | #endif |
434 | ||
435 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 436 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5f820439 | 437 | |
659e2f67 JL |
438 | /* |
439 | * BOOTP options | |
440 | */ | |
441 | #define CONFIG_BOOTP_BOOTFILESIZE | |
442 | #define CONFIG_BOOTP_BOOTPATH | |
443 | #define CONFIG_BOOTP_GATEWAY | |
444 | #define CONFIG_BOOTP_HOSTNAME | |
445 | ||
446 | ||
8ea5499a JL |
447 | /* |
448 | * Command line configuration. | |
449 | */ | |
450 | #include <config_cmd_default.h> | |
451 | ||
452 | #define CONFIG_CMD_PING | |
453 | #define CONFIG_CMD_I2C | |
454 | #define CONFIG_CMD_ASKENV | |
b5cdd7df | 455 | #define CONFIG_CMD_SDRAM |
8ea5499a | 456 | |
5f820439 | 457 | #if defined(CONFIG_PCI) |
8ea5499a | 458 | #define CONFIG_CMD_PCI |
5f820439 | 459 | #endif |
8ea5499a | 460 | |
6d0f6bcf | 461 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 462 | #undef CONFIG_CMD_SAVEENV |
8ea5499a | 463 | #undef CONFIG_CMD_LOADS |
5f820439 DL |
464 | #endif |
465 | ||
5f820439 DL |
466 | |
467 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
468 | ||
469 | /* | |
470 | * Miscellaneous configurable options | |
471 | */ | |
6d0f6bcf JCPV |
472 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
473 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
474 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
5f820439 | 475 | |
8ea5499a | 476 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 477 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5f820439 | 478 | #else |
6d0f6bcf | 479 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5f820439 DL |
480 | #endif |
481 | ||
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
483 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
484 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
485 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
5f820439 DL |
486 | |
487 | /* | |
488 | * For booting Linux, the board info and command line data | |
489 | * have to be in the first 8 MB of memory, since this is | |
490 | * the maximum mapped by the Linux kernel during initialization. | |
491 | */ | |
6d0f6bcf | 492 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
5f820439 DL |
493 | |
494 | /* | |
495 | * Core HID Setup | |
496 | */ | |
6d0f6bcf JCPV |
497 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
498 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
499 | #define CONFIG_SYS_HID2 HID2_HBE | |
5f820439 | 500 | |
5f820439 DL |
501 | /* |
502 | * MMU Setup | |
503 | */ | |
504 | ||
31d82672 BB |
505 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
506 | ||
5c2ff323 | 507 | /* DDR/LBC SDRAM: cacheable */ |
6d0f6bcf JCPV |
508 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
509 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
510 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
511 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
5f820439 DL |
512 | |
513 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
6d0f6bcf | 514 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ |
5f820439 | 515 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
516 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
517 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
518 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
5f820439 DL |
519 | |
520 | /* BCSR: cache-inhibit and guarded */ | |
6d0f6bcf | 521 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \ |
5f820439 | 522 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
523 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) |
524 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
525 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
5f820439 DL |
526 | |
527 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
6d0f6bcf JCPV |
528 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
529 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
530 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ | |
5f820439 | 531 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf | 532 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
5f820439 | 533 | |
5c2ff323 AV |
534 | /* DDR/LBC SDRAM next 256M: cacheable */ |
535 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE) | |
536 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP) | |
6d0f6bcf JCPV |
537 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
538 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
5f820439 DL |
539 | |
540 | /* Stack in dcache: cacheable, no memory coherence */ | |
6d0f6bcf JCPV |
541 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) |
542 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
543 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
544 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
5f820439 DL |
545 | |
546 | #ifdef CONFIG_PCI | |
547 | /* PCI MEM space: cacheable */ | |
9993e196 KP |
548 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
549 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
6d0f6bcf JCPV |
550 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
551 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
5f820439 | 552 | /* PCI MMIO space: cache-inhibit and guarded */ |
9993e196 | 553 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ |
5f820439 | 554 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
9993e196 | 555 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
6d0f6bcf JCPV |
556 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
557 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5f820439 | 558 | #else |
6d0f6bcf JCPV |
559 | #define CONFIG_SYS_IBAT6L (0) |
560 | #define CONFIG_SYS_IBAT6U (0) | |
561 | #define CONFIG_SYS_IBAT7L (0) | |
562 | #define CONFIG_SYS_IBAT7U (0) | |
563 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
564 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
565 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
566 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5f820439 DL |
567 | #endif |
568 | ||
569 | /* | |
570 | * Internal Definitions | |
571 | * | |
572 | * Boot Flags | |
573 | */ | |
574 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
575 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
576 | ||
8ea5499a | 577 | #if defined(CONFIG_CMD_KGDB) |
5f820439 DL |
578 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
579 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
580 | #endif | |
581 | ||
582 | /* | |
583 | * Environment Configuration | |
584 | */ | |
585 | ||
586 | #define CONFIG_ENV_OVERWRITE | |
587 | ||
588 | #if defined(CONFIG_UEC_ETH) | |
977b5758 | 589 | #define CONFIG_HAS_ETH0 |
5f820439 | 590 | #define CONFIG_HAS_ETH1 |
5f820439 DL |
591 | #endif |
592 | ||
dd520bf3 | 593 | #define CONFIG_BAUDRATE 115200 |
5f820439 | 594 | |
79f516bc | 595 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
5f820439 | 596 | |
dd520bf3 WD |
597 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
598 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
5f820439 | 599 | |
dd520bf3 WD |
600 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
601 | "netdev=eth0\0" \ | |
602 | "consoledev=ttyS0\0" \ | |
603 | "ramdiskaddr=1000000\0" \ | |
5f820439 | 604 | "ramdiskfile=ramfs.83xx\0" \ |
79f516bc | 605 | "fdtaddr=780000\0" \ |
270fe261 | 606 | "fdtfile=mpc836x_mds.dtb\0" \ |
bf0b542d | 607 | "" |
5f820439 | 608 | |
dd520bf3 WD |
609 | #define CONFIG_NFSBOOTCOMMAND \ |
610 | "setenv bootargs root=/dev/nfs rw " \ | |
611 | "nfsroot=$serverip:$rootpath " \ | |
bf0b542d | 612 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
dd520bf3 WD |
613 | "console=$consoledev,$baudrate $othbootargs;" \ |
614 | "tftp $loadaddr $bootfile;" \ | |
bf0b542d KP |
615 | "tftp $fdtaddr $fdtfile;" \ |
616 | "bootm $loadaddr - $fdtaddr" | |
5f820439 | 617 | |
bf0b542d | 618 | #define CONFIG_RAMBOOTCOMMAND \ |
dd520bf3 WD |
619 | "setenv bootargs root=/dev/ram rw " \ |
620 | "console=$consoledev,$baudrate $othbootargs;" \ | |
621 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
622 | "tftp $loadaddr $bootfile;" \ | |
bf0b542d KP |
623 | "tftp $fdtaddr $fdtfile;" \ |
624 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
625 | ||
5f820439 DL |
626 | |
627 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
628 | ||
629 | #endif /* __CONFIG_H */ |