projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5f820439 DL |
1 | /* |
| 2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * Dave Liu <daveliu@freescale.com> | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation; either version 2 of | |
| 9 | * the License, or (at your option) any later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| dd520bf3 | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 5f820439 DL |
14 | * GNU General Public License for more details. |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License | |
| 17 | * along with this program; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 19 | * MA 02111-1307 USA | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __CONFIG_H | |
| 23 | #define __CONFIG_H | |
| 24 | ||
| 25 | #undef DEBUG | |
| 26 | ||
| 27 | /* | |
| 28 | * High Level Configuration Options | |
| 29 | */ | |
| 30 | #define CONFIG_E300 1 /* E300 family */ | |
| 31 | #define CONFIG_QE 1 /* Has QE */ | |
| 32 | #define CONFIG_MPC83XX 1 /* MPC83XX family */ | |
| 33 | #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ | |
| 34 | #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ | |
| 14778585 TL |
35 | #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ |
| 36 | #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ | |
| 5f820439 DL |
37 | |
| 38 | /* | |
| 39 | * System Clock Setup | |
| 40 | */ | |
| 41 | #ifdef CONFIG_PCISLAVE | |
| 42 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
| 43 | #else | |
| 44 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
| 45 | #endif | |
| 46 | ||
| 47 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 48 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
| 49 | #endif | |
| 50 | ||
| 51 | /* | |
| 52 | * Hardware Reset Configuration Word | |
| 53 | */ | |
| 54 | #define CFG_HRCW_LOW (\ | |
| 55 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
| 56 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 57 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
| 58 | HRCWL_VCO_1X2 |\ | |
| 59 | HRCWL_CE_PLL_VCO_DIV_4 |\ | |
| 60 | HRCWL_CE_PLL_DIV_1X1 |\ | |
| 61 | HRCWL_CE_TO_PLL_1X6 |\ | |
| 62 | HRCWL_CORE_TO_CSB_2X1) | |
| 63 | ||
| 64 | #ifdef CONFIG_PCISLAVE | |
| 65 | #define CFG_HRCW_HIGH (\ | |
| 66 | HRCWH_PCI_AGENT |\ | |
| 67 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
| 68 | HRCWH_PCICKDRV_DISABLE |\ | |
| 69 | HRCWH_CORE_ENABLE |\ | |
| 70 | HRCWH_FROM_0XFFF00100 |\ | |
| 71 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 72 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 73 | HRCWH_ROM_LOC_LOCAL_16BIT) | |
| 74 | #else | |
| 75 | #define CFG_HRCW_HIGH (\ | |
| 76 | HRCWH_PCI_HOST |\ | |
| 77 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 78 | HRCWH_PCICKDRV_ENABLE |\ | |
| 79 | HRCWH_CORE_ENABLE |\ | |
| 80 | HRCWH_FROM_0X00000100 |\ | |
| 81 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 82 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 83 | HRCWH_ROM_LOC_LOCAL_16BIT) | |
| 84 | #endif | |
| 85 | ||
| 86 | /* | |
| 87 | * System IO Config | |
| 88 | */ | |
| 89 | #define CFG_SICRH 0x00000000 | |
| 90 | #define CFG_SICRL 0x40000000 | |
| 91 | ||
| 92 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
| 14778585 | 93 | #define CONFIG_BOARD_EARLY_INIT_R |
| 5f820439 DL |
94 | |
| 95 | /* | |
| 96 | * IMMR new address | |
| 97 | */ | |
| d239d74b | 98 | #define CFG_IMMR 0xE0000000 |
| 5f820439 DL |
99 | |
| 100 | /* | |
| 101 | * DDR Setup | |
| 102 | */ | |
| 103 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ | |
| 104 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
| 105 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
| b110f40b XX |
106 | #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
| 107 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
| 5f820439 | 108 | |
| bf0b542d KP |
109 | #define CFG_83XX_DDR_USES_CS0 |
| 110 | ||
| b110f40b | 111 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
| 5f820439 DL |
112 | #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ |
| 113 | ||
| b110f40b XX |
114 | /* |
| 115 | * DDRCDR - DDR Control Driver Register | |
| 116 | */ | |
| 117 | #define CFG_DDRCDR_VALUE 0x80080001 | |
| 118 | ||
| 5f820439 DL |
119 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 120 | #if defined(CONFIG_SPD_EEPROM) | |
| 121 | /* | |
| 122 | * Determine DDR configuration from I2C interface. | |
| 123 | */ | |
| 124 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ | |
| 125 | #else | |
| 126 | /* | |
| 127 | * Manually set up DDR parameters | |
| 128 | */ | |
| 129 | #define CFG_DDR_SIZE 256 /* MB */ | |
| b110f40b XX |
130 | #if defined(CONFIG_DDR_II) |
| 131 | #define CFG_DDRCDR 0x80080001 | |
| 132 | #define CFG_DDR_CS0_BNDS 0x0000000f | |
| 133 | #define CFG_DDR_CS0_CONFIG 0x80330102 | |
| 134 | #define CFG_DDR_TIMING_0 0x00220802 | |
| 135 | #define CFG_DDR_TIMING_1 0x38357322 | |
| 136 | #define CFG_DDR_TIMING_2 0x2f9048c8 | |
| 137 | #define CFG_DDR_TIMING_3 0x00000000 | |
| 138 | #define CFG_DDR_CLK_CNTL 0x02000000 | |
| 139 | #define CFG_DDR_MODE 0x47d00432 | |
| 140 | #define CFG_DDR_MODE2 0x8000c000 | |
| 141 | #define CFG_DDR_INTERVAL 0x03cf0080 | |
| 142 | #define CFG_DDR_SDRAM_CFG 0x43000000 | |
| 143 | #define CFG_DDR_SDRAM_CFG2 0x00401000 | |
| 144 | #else | |
| 5f820439 DL |
145 | #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) |
| 146 | #define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ | |
| 147 | #define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ | |
| dd520bf3 | 148 | #define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ |
| 5f820439 DL |
149 | #define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ |
| 150 | #define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ | |
| 151 | #endif | |
| b110f40b | 152 | #endif |
| 5f820439 DL |
153 | |
| 154 | /* | |
| 155 | * Memory test | |
| 156 | */ | |
| 157 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
| 158 | #define CFG_MEMTEST_START 0x00000000 /* memtest region */ | |
| 159 | #define CFG_MEMTEST_END 0x00100000 | |
| 160 | ||
| 161 | /* | |
| 162 | * The reserved memory | |
| 163 | */ | |
| 164 | ||
| 165 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 166 | ||
| 167 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 168 | #define CFG_RAMBOOT | |
| 169 | #else | |
| dd520bf3 | 170 | #undef CFG_RAMBOOT |
| 5f820439 DL |
171 | #endif |
| 172 | ||
| b2893e1f | 173 | /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
| 5f820439 DL |
174 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 175 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 176 | ||
| 177 | /* | |
| 178 | * Initial RAM Base Address Setup | |
| 179 | */ | |
| 180 | #define CFG_INIT_RAM_LOCK 1 | |
| 181 | #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
| 182 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
| 183 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
| 184 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 185 | ||
| 186 | /* | |
| 187 | * Local Bus Configuration & Clock Setup | |
| 188 | */ | |
| 189 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) | |
| 190 | #define CFG_LBC_LBCR 0x00000000 | |
| 191 | ||
| 192 | /* | |
| 193 | * FLASH on the Local Bus | |
| 194 | */ | |
| 195 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
| 196 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 197 | #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
| b110f40b | 198 | #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ |
| 5f820439 DL |
199 | |
| 200 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ | |
| 201 | #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
| 202 | ||
| 203 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ | |
| 204 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | |
| 205 | BR_V) /* valid */ | |
| b110f40b XX |
206 | #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
| 207 | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ | |
| 208 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
| 5f820439 DL |
209 | |
| 210 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
| b110f40b | 211 | #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ |
| 5f820439 DL |
212 | |
| 213 | #undef CFG_FLASH_CHECKSUM | |
| 214 | ||
| 215 | /* | |
| 216 | * BCSR on the Local Bus | |
| 217 | */ | |
| 218 | #define CFG_BCSR 0xF8000000 | |
| 219 | #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ | |
| a87c856e | 220 | #define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */ |
| 5f820439 DL |
221 | |
| 222 | #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ | |
| 223 | #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ | |
| 224 | ||
| 225 | /* | |
| 226 | * SDRAM on the Local Bus | |
| 227 | */ | |
| 228 | #define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ | |
| 229 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
| 230 | ||
| 231 | #define CFG_LB_SDRAM /* if board has SRDAM on local bus */ | |
| 232 | ||
| 233 | #ifdef CFG_LB_SDRAM | |
| 234 | #define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE | |
| 235 | #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ | |
| 236 | ||
| 237 | /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ | |
| 238 | /* | |
| 239 | * Base Register 2 and Option Register 2 configure SDRAM. | |
| 240 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. | |
| 241 | * | |
| 242 | * For BR2, need: | |
| 243 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 244 | * port size = 32-bits = BR2[19:20] = 11 | |
| 245 | * no parity checking = BR2[21:22] = 00 | |
| 246 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 247 | * Valid = BR[31] = 1 | |
| 248 | * | |
| dd520bf3 | 249 | * 0 4 8 12 16 20 24 28 |
| 5f820439 DL |
250 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
| 251 | * | |
| 252 | * CFG_LBC_SDRAM_BASE should be masked and OR'ed into | |
| 253 | * the top 17 bits of BR2. | |
| 254 | */ | |
| 255 | ||
| 256 | #define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ | |
| 257 | ||
| 258 | /* | |
| 259 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. | |
| 260 | * | |
| 261 | * For OR2, need: | |
| 262 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
| 263 | * XAM, OR2[17:18] = 11 | |
| 264 | * 9 columns OR2[19-21] = 010 | |
| dd520bf3 | 265 | * 13 rows OR2[23-25] = 100 |
| 5f820439 DL |
266 | * EAD set for extra time OR[31] = 1 |
| 267 | * | |
| dd520bf3 | 268 | * 0 4 8 12 16 20 24 28 |
| 5f820439 DL |
269 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
| 270 | */ | |
| 271 | ||
| 272 | #define CFG_OR2_PRELIM 0xfc006901 | |
| 273 | ||
| 274 | #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ | |
| 275 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
| 276 | ||
| 277 | /* | |
| 278 | * LSDMR masks | |
| 279 | */ | |
| dd520bf3 WD |
280 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
| 281 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
| 282 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
| 5f820439 DL |
283 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
| 284 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
| dd520bf3 WD |
285 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
| 286 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
| 5f820439 DL |
287 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
| 288 | ||
| 289 | #define CFG_LBC_LSDMR_COMMON 0x0063b723 | |
| 290 | ||
| 291 | /* | |
| 292 | * SDRAM Controller configuration sequence. | |
| 293 | */ | |
| 294 | #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ | |
| 295 | | CFG_LBC_LSDMR_OP_PCHALL) | |
| 296 | #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ | |
| 297 | | CFG_LBC_LSDMR_OP_ARFRSH) | |
| 298 | #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ | |
| 299 | | CFG_LBC_LSDMR_OP_ARFRSH) | |
| 300 | #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ | |
| 301 | | CFG_LBC_LSDMR_OP_MRW) | |
| 302 | #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ | |
| 303 | | CFG_LBC_LSDMR_OP_NORMAL) | |
| 304 | ||
| 305 | #endif | |
| 306 | ||
| 307 | /* | |
| 308 | * Windows to access PIB via local bus | |
| 309 | */ | |
| a87c856e DL |
310 | #define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */ |
| 311 | #define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */ | |
| 5f820439 DL |
312 | |
| 313 | /* | |
| 314 | * CS4 on Local Bus, to PIB | |
| 315 | */ | |
| 14778585 | 316 | #define CFG_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */ |
| 5f820439 DL |
317 | #define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
| 318 | ||
| 319 | /* | |
| 320 | * CS5 on Local Bus, to PIB | |
| 321 | */ | |
| 14778585 | 322 | #define CFG_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */ |
| 5f820439 DL |
323 | #define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ |
| 324 | ||
| 325 | /* | |
| 326 | * Serial Port | |
| 327 | */ | |
| 328 | #define CONFIG_CONS_INDEX 1 | |
| 329 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 330 | #define CFG_NS16550 | |
| 331 | #define CFG_NS16550_SERIAL | |
| 332 | #define CFG_NS16550_REG_SIZE 1 | |
| 333 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 334 | ||
| 335 | #define CFG_BAUDRATE_TABLE \ | |
| 336 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 337 | ||
| d239d74b TT |
338 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
| 339 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
| 5f820439 | 340 | |
| 22d71a71 | 341 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 5f820439 DL |
342 | /* Use the HUSH parser */ |
| 343 | #define CFG_HUSH_PARSER | |
| dd520bf3 | 344 | #ifdef CFG_HUSH_PARSER |
| 5f820439 DL |
345 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 346 | #endif | |
| 347 | ||
| bf0b542d | 348 | /* pass open firmware flat tree */ |
| 213bf8c8 | 349 | #define CONFIG_OF_LIBFDT 1 |
| bf0b542d | 350 | #define CONFIG_OF_BOARD_SETUP 1 |
| 5b8bc606 | 351 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| bf0b542d | 352 | |
| 5f820439 DL |
353 | /* I2C */ |
| 354 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 355 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| be5e6181 TT |
356 | #define CONFIG_FSL_I2C |
| 357 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 5f820439 DL |
358 | #define CFG_I2C_SLAVE 0x7F |
| 359 | #define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ | |
| 360 | #define CFG_I2C_OFFSET 0x3000 | |
| dd520bf3 | 361 | #define CFG_I2C2_OFFSET 0x3100 |
| 5f820439 DL |
362 | |
| 363 | /* | |
| 364 | * Config on-board RTC | |
| 365 | */ | |
| 366 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
| 367 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
| 368 | ||
| 369 | /* | |
| 370 | * General PCI | |
| 371 | * Addresses are mapped 1-1. | |
| 372 | */ | |
| 373 | #define CFG_PCI_MEM_BASE 0x80000000 | |
| 374 | #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE | |
| 375 | #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
| 376 | #define CFG_PCI_MMIO_BASE 0x90000000 | |
| 377 | #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE | |
| 378 | #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
| 379 | #define CFG_PCI_IO_BASE 0xE0300000 | |
| 380 | #define CFG_PCI_IO_PHYS 0xE0300000 | |
| 381 | #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ | |
| 382 | ||
| 383 | #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE | |
| 384 | #define CFG_PCI_SLV_MEM_BUS 0x00000000 | |
| 385 | #define CFG_PCI_SLV_MEM_SIZE 0x80000000 | |
| 386 | ||
| 387 | ||
| 388 | #ifdef CONFIG_PCI | |
| 389 | ||
| 390 | #define CONFIG_NET_MULTI | |
| 391 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 392 | ||
| 393 | #undef CONFIG_EEPRO100 | |
| 394 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| dd520bf3 | 395 | #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
| 5f820439 DL |
396 | |
| 397 | #endif /* CONFIG_PCI */ | |
| 398 | ||
| 399 | ||
| 400 | #ifndef CONFIG_NET_MULTI | |
| 401 | #define CONFIG_NET_MULTI 1 | |
| 402 | #endif | |
| 403 | ||
| 7737d5c6 DL |
404 | /* |
| 405 | * QE UEC ethernet configuration | |
| 406 | */ | |
| 407 | #define CONFIG_UEC_ETH | |
| 408 | #define CONFIG_ETHPRIME "Freescale GETH" | |
| 409 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
| 410 | ||
| 411 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
| 412 | ||
| 413 | #ifdef CONFIG_UEC_ETH1 | |
| 414 | #define CFG_UEC1_UCC_NUM 0 /* UCC1 */ | |
| 415 | #define CFG_UEC1_RX_CLK QE_CLK_NONE | |
| 416 | #define CFG_UEC1_TX_CLK QE_CLK9 | |
| 417 | #define CFG_UEC1_ETH_TYPE GIGA_ETH | |
| 418 | #define CFG_UEC1_PHY_ADDR 0 | |
| dd520bf3 | 419 | #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII |
| 7737d5c6 DL |
420 | #endif |
| 421 | ||
| 422 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
| 423 | ||
| 424 | #ifdef CONFIG_UEC_ETH2 | |
| 425 | #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ | |
| 426 | #define CFG_UEC2_RX_CLK QE_CLK_NONE | |
| 427 | #define CFG_UEC2_TX_CLK QE_CLK4 | |
| 428 | #define CFG_UEC2_ETH_TYPE GIGA_ETH | |
| 429 | #define CFG_UEC2_PHY_ADDR 1 | |
| dd520bf3 | 430 | #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII |
| 7737d5c6 DL |
431 | #endif |
| 432 | ||
| 5f820439 DL |
433 | /* |
| 434 | * Environment | |
| 435 | */ | |
| 436 | ||
| 437 | #ifndef CFG_RAMBOOT | |
| 438 | #define CFG_ENV_IS_IN_FLASH 1 | |
| b2893e1f TT |
439 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
| 440 | #define CFG_ENV_SECT_SIZE 0x20000 | |
| 5f820439 DL |
441 | #define CFG_ENV_SIZE 0x2000 |
| 442 | #else | |
| 443 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
| 444 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 445 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
| 446 | #define CFG_ENV_SIZE 0x2000 | |
| 447 | #endif | |
| 448 | ||
| 449 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 450 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 451 | ||
| 659e2f67 JL |
452 | /* |
| 453 | * BOOTP options | |
| 454 | */ | |
| 455 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 456 | #define CONFIG_BOOTP_BOOTPATH | |
| 457 | #define CONFIG_BOOTP_GATEWAY | |
| 458 | #define CONFIG_BOOTP_HOSTNAME | |
| 459 | ||
| 460 | ||
| 8ea5499a JL |
461 | /* |
| 462 | * Command line configuration. | |
| 463 | */ | |
| 464 | #include <config_cmd_default.h> | |
| 465 | ||
| 466 | #define CONFIG_CMD_PING | |
| 467 | #define CONFIG_CMD_I2C | |
| 468 | #define CONFIG_CMD_ASKENV | |
| 469 | ||
| 5f820439 | 470 | #if defined(CONFIG_PCI) |
| 8ea5499a | 471 | #define CONFIG_CMD_PCI |
| 5f820439 | 472 | #endif |
| 8ea5499a JL |
473 | |
| 474 | #if defined(CFG_RAMBOOT) | |
| 475 | #undef CONFIG_CMD_ENV | |
| 476 | #undef CONFIG_CMD_LOADS | |
| 5f820439 DL |
477 | #endif |
| 478 | ||
| 5f820439 DL |
479 | |
| 480 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 481 | ||
| 482 | /* | |
| 483 | * Miscellaneous configurable options | |
| 484 | */ | |
| 485 | #define CFG_LONGHELP /* undef to save memory */ | |
| 486 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
| 487 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 488 | ||
| 8ea5499a | 489 | #if defined(CONFIG_CMD_KGDB) |
| 5f820439 DL |
490 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 491 | #else | |
| 492 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 493 | #endif | |
| 494 | ||
| 495 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 496 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 497 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 498 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 499 | ||
| 500 | /* | |
| 501 | * For booting Linux, the board info and command line data | |
| 502 | * have to be in the first 8 MB of memory, since this is | |
| 503 | * the maximum mapped by the Linux kernel during initialization. | |
| 504 | */ | |
| 505 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 506 | ||
| 507 | /* | |
| 508 | * Core HID Setup | |
| 509 | */ | |
| 510 | #define CFG_HID0_INIT 0x000000000 | |
| 511 | #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
| 512 | #define CFG_HID2 HID2_HBE | |
| 513 | ||
| 5f820439 DL |
514 | /* |
| 515 | * MMU Setup | |
| 516 | */ | |
| 517 | ||
| 518 | /* DDR: cache cacheable */ | |
| 519 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 520 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 521 | #define CFG_DBAT0L CFG_IBAT0L | |
| 522 | #define CFG_DBAT0U CFG_IBAT0U | |
| 523 | ||
| 524 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
| d239d74b | 525 | #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ |
| 5f820439 | 526 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| d239d74b | 527 | #define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) |
| 5f820439 DL |
528 | #define CFG_DBAT1L CFG_IBAT1L |
| 529 | #define CFG_DBAT1U CFG_IBAT1U | |
| 530 | ||
| 531 | /* BCSR: cache-inhibit and guarded */ | |
| 532 | #define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ | |
| 533 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 534 | #define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 535 | #define CFG_DBAT2L CFG_IBAT2L | |
| 536 | #define CFG_DBAT2U CFG_IBAT2U | |
| 537 | ||
| 538 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
| 539 | #define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 540 | #define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 541 | #define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ | |
| 542 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 543 | #define CFG_DBAT3U CFG_IBAT3U | |
| 544 | ||
| 545 | /* Local bus SDRAM: cacheable */ | |
| 546 | #define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 547 | #define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) | |
| 548 | #define CFG_DBAT4L CFG_IBAT4L | |
| 549 | #define CFG_DBAT4U CFG_IBAT4U | |
| 550 | ||
| 551 | /* Stack in dcache: cacheable, no memory coherence */ | |
| 552 | #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) | |
| 553 | #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 554 | #define CFG_DBAT5L CFG_IBAT5L | |
| 555 | #define CFG_DBAT5U CFG_IBAT5U | |
| 556 | ||
| 557 | #ifdef CONFIG_PCI | |
| 558 | /* PCI MEM space: cacheable */ | |
| 559 | #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 560 | #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 561 | #define CFG_DBAT6L CFG_IBAT6L | |
| 562 | #define CFG_DBAT6U CFG_IBAT6U | |
| 563 | /* PCI MMIO space: cache-inhibit and guarded */ | |
| 564 | #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ | |
| 565 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 566 | #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 567 | #define CFG_DBAT7L CFG_IBAT7L | |
| 568 | #define CFG_DBAT7U CFG_IBAT7U | |
| 569 | #else | |
| 570 | #define CFG_IBAT6L (0) | |
| 571 | #define CFG_IBAT6U (0) | |
| 572 | #define CFG_IBAT7L (0) | |
| 573 | #define CFG_IBAT7U (0) | |
| 574 | #define CFG_DBAT6L CFG_IBAT6L | |
| 575 | #define CFG_DBAT6U CFG_IBAT6U | |
| 576 | #define CFG_DBAT7L CFG_IBAT7L | |
| 577 | #define CFG_DBAT7U CFG_IBAT7U | |
| 578 | #endif | |
| 579 | ||
| 580 | /* | |
| 581 | * Internal Definitions | |
| 582 | * | |
| 583 | * Boot Flags | |
| 584 | */ | |
| 585 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 586 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 587 | ||
| 8ea5499a | 588 | #if defined(CONFIG_CMD_KGDB) |
| 5f820439 DL |
589 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 590 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 591 | #endif | |
| 592 | ||
| 593 | /* | |
| 594 | * Environment Configuration | |
| 595 | */ | |
| 596 | ||
| 597 | #define CONFIG_ENV_OVERWRITE | |
| 598 | ||
| 599 | #if defined(CONFIG_UEC_ETH) | |
| 977b5758 | 600 | #define CONFIG_HAS_ETH0 |
| 5f820439 DL |
601 | #define CONFIG_ETHADDR 00:04:9f:ef:01:01 |
| 602 | #define CONFIG_HAS_ETH1 | |
| dd520bf3 | 603 | #define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 |
| 5f820439 DL |
604 | #endif |
| 605 | ||
| dd520bf3 | 606 | #define CONFIG_BAUDRATE 115200 |
| 5f820439 | 607 | |
| dd520bf3 | 608 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
| 5f820439 | 609 | |
| dd520bf3 WD |
610 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
| 611 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 5f820439 | 612 | |
| dd520bf3 WD |
613 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 614 | "netdev=eth0\0" \ | |
| 615 | "consoledev=ttyS0\0" \ | |
| 616 | "ramdiskaddr=1000000\0" \ | |
| 5f820439 | 617 | "ramdiskfile=ramfs.83xx\0" \ |
| bf0b542d | 618 | "fdtaddr=400000\0" \ |
| 6752ed08 | 619 | "fdtfile=mpc8360emds.dtb\0" \ |
| bf0b542d | 620 | "" |
| 5f820439 | 621 | |
| dd520bf3 WD |
622 | #define CONFIG_NFSBOOTCOMMAND \ |
| 623 | "setenv bootargs root=/dev/nfs rw " \ | |
| 624 | "nfsroot=$serverip:$rootpath " \ | |
| bf0b542d | 625 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| dd520bf3 WD |
626 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 627 | "tftp $loadaddr $bootfile;" \ | |
| bf0b542d KP |
628 | "tftp $fdtaddr $fdtfile;" \ |
| 629 | "bootm $loadaddr - $fdtaddr" | |
| 5f820439 | 630 | |
| bf0b542d | 631 | #define CONFIG_RAMBOOTCOMMAND \ |
| dd520bf3 WD |
632 | "setenv bootargs root=/dev/ram rw " \ |
| 633 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 634 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 635 | "tftp $loadaddr $bootfile;" \ | |
| bf0b542d KP |
636 | "tftp $fdtaddr $fdtfile;" \ |
| 637 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 638 | ||
| 5f820439 DL |
639 | |
| 640 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 641 | ||
| 642 | #endif /* __CONFIG_H */ |