[people/ms/u-boot.git] / include / configs / MPC8360EMDS.h

/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *
 * Dave Liu <daveliu@freescale.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#undef DEBUG

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_QE		1 /* Has QE */
#define CONFIG_MPC83XX		1 /* MPC83XX family */
#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS	1 /* MPC8360EMDS board specific */

/*
 * System Clock Setup
 */
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
#else
#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
#endif

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66000000
#endif

/*
 * Hardware Reset Configuration Word
 */
#define CFG_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CE_PLL_VCO_DIV_4 |\
	HRCWL_CE_PLL_DIV_1X1 |\
	HRCWL_CE_TO_PLL_1X6 |\
	HRCWL_CORE_TO_CSB_2X1)

#ifdef CONFIG_PCISLAVE
#define CFG_HRCW_HIGH (\
	HRCWH_PCI_AGENT |\
	HRCWH_PCI1_ARBITER_DISABLE |\
	HRCWH_PCICKDRV_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0XFFF00100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT)
#else
#define CFG_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCICKDRV_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT)
#endif

/*
 * System IO Config
 */
#define CFG_SICRH		0x00000000
#define CFG_SICRL		0x40000000

#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */

/*
 * IMMR new address
 */
#define CFG_IMMR		0xE0000000

/*
 * DDR Setup
 */
#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE		CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE

#define CFG_83XX_DDR_USES_CS0

#undef	CONFIG_DDR_ECC		/* only for ECC DDR module */
#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */

#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
#if defined(CONFIG_SPD_EEPROM)
/*
 * Determine DDR configuration from I2C interface.
 */
#define SPD_EEPROM_ADDRESS	0x52 /* DDR SODIMM */
#else
/*
 * Manually set up DDR parameters
 */
#define CFG_DDR_SIZE		256 /* MB */
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CFG_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CFG_DDR_TIMING_2	0x00000800 /* may need tuning */
#define CFG_DDR_CONTROL		0x42008000 /* Self refresh,2T timing */
#define CFG_DDR_MODE		0x20000162 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL	0x045b0100 /* page mode */
#endif

/*
 * Memory test
 */
#undef CFG_DRAM_TEST		/* memory test, takes time */
#define CFG_MEMTEST_START	0x00000000 /* memtest region */
#define CFG_MEMTEST_END		0x00100000

/*
 * The reserved memory
 */

#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef	CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR		0x00000000

/*
 * FLASH on the Local Bus
 */
#define CFG_FLASH_CFI		/* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE		16 /* FLASH size is 16M */

#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */

#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | /* Flash Base address */ \
			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
			BR_V)	/* valid */
#define CFG_OR0_PRELIM		0xfe006ff7 /* 16MB Flash size */

#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
#define CFG_MAX_FLASH_SECT	128 /* sectors per device */

#undef	CFG_FLASH_CHECKSUM

/*
 * BCSR on the Local Bus
 */
#define CFG_BCSR		0xF8000000
#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR /* Access window base at BCSR base */
#define CFG_LBLAWAR1_PRELIM	0x8000000E /* Access window size 32K */

#define CFG_BR1_PRELIM		(CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM		0xFFFFE9f7 /* length 32K */

/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CFG_LB_SDRAM		/* if board has SRDAM on local bus */

#ifdef CFG_LB_SDRAM
#define CFG_LBLAWBAR2_PRELIM	CFG_LBC_SDRAM_BASE
#define CFG_LBLAWAR2_PRELIM	0x80000019 /* 64MB */

/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 * the top 17 bits of BR2.
 */

#define CFG_BR2_PRELIM	0xf0001861 /*Port size=32bit, MSEL=SDRAM */

/*
 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows	OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CFG_OR2_PRELIM	0xfc006901

#define CFG_LBC_LSRT	0x32000000 /* LB sdram refresh timer, about 6us */
#define CFG_LBC_MRTPR	0x20000000 /* LB refresh timer prescal, 266MHz/32 */

/*
 * LSDMR masks
 */
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))

#define CFG_LBC_LSDMR_COMMON	0x0063b723

/*
 * SDRAM Controller configuration sequence.
 */
#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_NORMAL)

#endif

/*
 * Windows to access PIB via local bus
 */
#define CFG_LBLAWBAR3_PRELIM	0xf8008000 /* windows base 0xf8008000 */
#define CFG_LBLAWAR3_PRELIM	0x8000000f /* windows size 64KB */

/*
 * CS4 on Local Bus, to PIB
 */
#define CFG_BR4_PRELIM	0xf8008801 /* CS4 base address at 0xf8008000 */
#define CFG_OR4_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */

/*
 * CS5 on Local Bus, to PIB
 */
#define CFG_BR5_PRELIM	0xf8010801 /* CS5 base address at 0xf8010000 */
#define CFG_OR5_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE	1
#define CONFIG_OF_BOARD_SETUP	1

/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE	8192

#define OF_CPU			"PowerPC,8360@0"
#define OF_SOC			"soc8360@e0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc8360@e0000000/serial@4500"

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE	0x7F
#define CFG_I2C_NOPROBES	{0x52} /* Don't probe these addrs */
#define CFG_I2C_OFFSET	0x3000
#define CFG_I2C2_OFFSET 0x3100

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI_MEM_BASE	0x80000000
#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
#define CFG_PCI_MMIO_BASE	0x90000000
#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
#define CFG_PCI_IO_BASE		0xE0300000
#define CFG_PCI_IO_PHYS		0xE0300000
#define CFG_PCI_IO_SIZE		0x100000 /* 1M */

#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
#define CFG_PCI_SLV_MEM_BUS	0x00000000
#define CFG_PCI_SLV_MEM_SIZE	0x80000000


#ifdef CONFIG_PCI

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */

#endif	/* CONFIG_PCI */


#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"Freescale GETH"
#define CONFIG_PHY_MODE_NEED_CHANGE

#define CONFIG_UEC_ETH1		/* GETH1 */

#ifdef CONFIG_UEC_ETH1
#define CFG_UEC1_UCC_NUM	0	/* UCC1 */
#define CFG_UEC1_RX_CLK		QE_CLK_NONE
#define CFG_UEC1_TX_CLK		QE_CLK9
#define CFG_UEC1_ETH_TYPE	GIGA_ETH
#define CFG_UEC1_PHY_ADDR	0
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
#endif

#define CONFIG_UEC_ETH2		/* GETH2 */

#ifdef CONFIG_UEC_ETH2
#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
#define CFG_UEC2_RX_CLK		QE_CLK_NONE
#define CFG_UEC2_TX_CLK		QE_CLK4
#define CFG_UEC2_ETH_TYPE	GIGA_ETH
#define CFG_UEC2_PHY_ADDR	1
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
#endif

/*
 * Environment
 */

#ifndef CFG_RAMBOOT
	#define CFG_ENV_IS_IN_FLASH	1
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
	#define CFG_ENV_SECT_SIZE	0x40000 /* 256K(one sector) for env */
	#define CFG_ENV_SIZE		0x2000
#else
	#define CFG_NO_FLASH		1	/* Flash is not usable now */
	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
	#define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define	 CONFIG_COMMANDS	((CONFIG_CMD_DFL \
				| CFG_CMD_PING \
				| CFG_CMD_ASKENV \
				| CFG_CMD_PCI \
				| CFG_CMD_I2C) \
				& \
				~(CFG_CMD_ENV \
				| CFG_CMD_LOADS))
#else
#define	 CONFIG_COMMANDS	((CONFIG_CMD_DFL \
				| CFG_CMD_PING \
				| CFG_CMD_ASKENV \
				| CFG_CMD_I2C) \
				& \
				~(CFG_CMD_ENV \
				| CFG_CMD_LOADS))
#endif
#else
#if defined(CONFIG_PCI)
#define	 CONFIG_COMMANDS	(CONFIG_CMD_DFL \
				| CFG_CMD_PCI \
				| CFG_CMD_PING \
				| CFG_CMD_ASKENV \
				| CFG_CMD_I2C)
#else
#define	 CONFIG_COMMANDS	(CONFIG_CMD_DFL \
				| CFG_CMD_PING \
				| CFG_CMD_ASKENV \
				| CFG_CMD_I2C  )
#endif
#endif

#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		/* undef to save memory */
#define CFG_LOAD_ADDR		0x2000000 /* default load address */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CFG_HID0_INIT		0x000000000
#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2		HID2_HBE

/*
 * Cache Config
 */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5 /*log base 2 of the above value */
#endif

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U

/* BCSR: cache-inhibit and guarded */
#define CFG_IBAT2L	(CFG_BCSR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT2U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U	CFG_IBAT3U

/* Local bus SDRAM: cacheable */
#define CFG_IBAT4L	(CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT4U	(CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT4L	CFG_IBAT4L
#define CFG_DBAT4U	CFG_IBAT4U

/* Stack in dcache: cacheable, no memory coherence */
#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT5L	CFG_IBAT5L
#define CFG_DBAT5U	CFG_IBAT5U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U
#else
#define CFG_IBAT6L	(0)
#define CFG_IBAT6U	(0)
#define CFG_IBAT7L	(0)
#define CFG_IBAT7U	(0)
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02 /* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_UEC_ETH)
#define CONFIG_ETHADDR	00:04:9f:ef:01:01
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
#endif

#define CONFIG_BAUDRATE 115200

#define CONFIG_LOADADDR 200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_EXTRA_ENV_SETTINGS					\
   "netdev=eth0\0"							\
   "consoledev=ttyS0\0"							\
   "ramdiskaddr=1000000\0"						\
   "ramdiskfile=ramfs.83xx\0"						\
   "fdtaddr=400000\0"							\
   "fdtfile=mpc8349emds.dtb\0"						\
   ""

#define CONFIG_NFSBOOTCOMMAND						\
   "setenv bootargs root=/dev/nfs rw "					\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
   "setenv bootargs root=/dev/ram rw "					\
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $ramdiskaddr $ramdiskfile;"					\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"


#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
5f820439 DL	1	/*
	2	* Copyright (C) 2006 Freescale Semiconductor, Inc.
	3	*
	4	* Dave Liu <daveliu@freescale.com>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
dd520bf3	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5f820439 DL	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#ifndef __CONFIG_H
	23	#define __CONFIG_H
	24
	25	#undef DEBUG
	26
	27	/*
	28	* High Level Configuration Options
	29	*/
	30	#define CONFIG_E300 1 /* E300 family */
	31	#define CONFIG_QE 1 /* Has QE */
	32	#define CONFIG_MPC83XX 1 /* MPC83XX family */
	33	#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
	34	#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
	35
	36	/*
	37	* System Clock Setup
	38	*/
	39	#ifdef CONFIG_PCISLAVE
	40	#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
	41	#else
	42	#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
	43	#endif
	44
	45	#ifndef CONFIG_SYS_CLK_FREQ
	46	#define CONFIG_SYS_CLK_FREQ 66000000
	47	#endif
	48
	49	/*
	50	* Hardware Reset Configuration Word
	51	*/
	52	#define CFG_HRCW_LOW (\
	53	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	54	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	55	HRCWL_CSB_TO_CLKIN_4X1 \|\
	56	HRCWL_VCO_1X2 \|\
	57	HRCWL_CE_PLL_VCO_DIV_4 \|\
	58	HRCWL_CE_PLL_DIV_1X1 \|\
	59	HRCWL_CE_TO_PLL_1X6 \|\
	60	HRCWL_CORE_TO_CSB_2X1)
	61
	62	#ifdef CONFIG_PCISLAVE
	63	#define CFG_HRCW_HIGH (\
	64	HRCWH_PCI_AGENT \|\
	65	HRCWH_PCI1_ARBITER_DISABLE \|\
	66	HRCWH_PCICKDRV_DISABLE \|\
	67	HRCWH_CORE_ENABLE \|\
	68	HRCWH_FROM_0XFFF00100 \|\
	69	HRCWH_BOOTSEQ_DISABLE \|\
	70	HRCWH_SW_WATCHDOG_DISABLE \|\
	71	HRCWH_ROM_LOC_LOCAL_16BIT)
	72	#else
	73	#define CFG_HRCW_HIGH (\
	74	HRCWH_PCI_HOST \|\
	75	HRCWH_PCI1_ARBITER_ENABLE \|\
	76	HRCWH_PCICKDRV_ENABLE \|\
	77	HRCWH_CORE_ENABLE \|\
78	HRCWH_FROM_0X00000100 \|\
79	HRCWH_BOOTSEQ_DISABLE \|\
80	HRCWH_SW_WATCHDOG_DISABLE \|\
81	HRCWH_ROM_LOC_LOCAL_16BIT)
82	#endif
83
84	/*
85	* System IO Config
86	*/
87	#define CFG_SICRH 0x00000000
88	#define CFG_SICRL 0x40000000
89
90	#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
91
92	/*
93	* IMMR new address
94	*/
d239d74b	95	#define CFG_IMMR 0xE0000000
5f820439 DL	96
	97	/*
	98	* DDR Setup
	99	*/
	100	#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
	101	#define CFG_SDRAM_BASE CFG_DDR_BASE
	102	#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
	103
bf0b542d KP	104	#define CFG_83XX_DDR_USES_CS0
bf0b542d KP	105
5f820439 DL	106	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	107	#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
	108
	109	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	110	#if defined(CONFIG_SPD_EEPROM)
	111	/*
	112	* Determine DDR configuration from I2C interface.
	113	*/
	114	#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
	115	#else
	116	/*
	117	* Manually set up DDR parameters
	118	*/
	119	#define CFG_DDR_SIZE 256 /* MB */
	120	#define CFG_DDR_CONFIG (CSCONFIG_EN \| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_9)
	121	#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
	122	#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
dd520bf3	123	#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
5f820439 DL	124	#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
	125	#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
	126	#endif
	127
	128	/*
	129	* Memory test
	130	*/
	131	#undef CFG_DRAM_TEST /* memory test, takes time */
	132	#define CFG_MEMTEST_START 0x00000000 /* memtest region */
	133	#define CFG_MEMTEST_END 0x00100000
	134
	135	/*
	136	* The reserved memory
	137	*/
	138
	139	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	140
	141	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	142	#define CFG_RAMBOOT
	143	#else
dd520bf3	144	#undef CFG_RAMBOOT
5f820439 DL	145	#endif
	146
	147	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	148	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
	149
	150	/*
	151	* Initial RAM Base Address Setup
	152	*/
	153	#define CFG_INIT_RAM_LOCK 1
	154	#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	155	#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
	156	#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	157	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	158
	159	/*
	160	* Local Bus Configuration & Clock Setup
	161	*/
	162	#define CFG_LCRR (LCRR_DBYP \| LCRR_CLKDIV_4)
	163	#define CFG_LBC_LBCR 0x00000000
	164
	165	/*
	166	* FLASH on the Local Bus
	167	*/
	168	#define CFG_FLASH_CFI /* use the Common Flash Interface */
	169	#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
	170	#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
	171	#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
	172
	173	#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
	174	#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
	175
	176	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| /* Flash Base address */ \
	177	(2 << BR_PS_SHIFT) \| /* 16 bit port size */ \
	178	BR_V) /* valid */
	179	#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
	180
	181	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	182	#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
	183
	184	#undef CFG_FLASH_CHECKSUM
	185
	186	/*
	187	* BCSR on the Local Bus
	188	*/
	189	#define CFG_BCSR 0xF8000000
	190	#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
	191	#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
	192
	193	#define CFG_BR1_PRELIM (CFG_BCSR\|0x00000801) /* Port size=8bit, MSEL=GPCM */
	194	#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
	195
	196	/*
	197	* SDRAM on the Local Bus
	198	*/
	199	#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
	200	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
	201
	202	#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
	203
	204	#ifdef CFG_LB_SDRAM
	205	#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
	206	#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
	207
	208	/local bus BR2, OR2 definition for SDRAM if soldered on the EPB board /
209	/*
210	* Base Register 2 and Option Register 2 configure SDRAM.
211	* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
212	*
213	* For BR2, need:
214	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
215	* port size = 32-bits = BR2[19:20] = 11
216	* no parity checking = BR2[21:22] = 00
217	* SDRAM for MSEL = BR2[24:26] = 011
218	* Valid = BR[31] = 1
219	*
dd520bf3	220	* 0 4 8 12 16 20 24 28
5f820439 DL	221	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	222	*
	223	* CFG_LBC_SDRAM_BASE should be masked and OR'ed into
	224	* the top 17 bits of BR2.
	225	*/
	226
	227	#define CFG_BR2_PRELIM 0xf0001861 /Port size=32bit, MSEL=SDRAM /
	228
	229	/*
	230	* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
	231	*
	232	* For OR2, need:
	233	* 64MB mask for AM, OR2[0:7] = 1111 1100
	234	* XAM, OR2[17:18] = 11
	235	* 9 columns OR2[19-21] = 010
dd520bf3	236	* 13 rows OR2[23-25] = 100
5f820439 DL	237	* EAD set for extra time OR[31] = 1
5f820439 DL	238	*
dd520bf3	239	* 0 4 8 12 16 20 24 28
5f820439 DL	240	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	241	*/
	242
	243	#define CFG_OR2_PRELIM 0xfc006901
	244
	245	#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
	246	#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
	247
	248	/*
	249	* LSDMR masks
	250	*/
dd520bf3 WD	251	#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
	252	#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
	253	#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
5f820439 DL	254	#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
5f820439 DL	255	#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
dd520bf3 WD	256	#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
dd520bf3 WD	257	#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
5f820439 DL	258	#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
	259
	260	#define CFG_LBC_LSDMR_COMMON 0x0063b723
	261
	262	/*
	263	* SDRAM Controller configuration sequence.
	264	*/
	265	#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
	266	\| CFG_LBC_LSDMR_OP_PCHALL)
	267	#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
	268	\| CFG_LBC_LSDMR_OP_ARFRSH)
	269	#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
	270	\| CFG_LBC_LSDMR_OP_ARFRSH)
	271	#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
	272	\| CFG_LBC_LSDMR_OP_MRW)
	273	#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
	274	\| CFG_LBC_LSDMR_OP_NORMAL)
	275
	276	#endif
	277
	278	/*
	279	* Windows to access PIB via local bus
	280	*/
	281	#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
	282	#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
	283
	284	/*
	285	* CS4 on Local Bus, to PIB
	286	*/
	287	#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */
	288	#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
	289
	290	/*
	291	* CS5 on Local Bus, to PIB
	292	*/
	293	#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */
	294	#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
	295
	296	/*
	297	* Serial Port
	298	*/
	299	#define CONFIG_CONS_INDEX 1
	300	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	301	#define CFG_NS16550
	302	#define CFG_NS16550_SERIAL
	303	#define CFG_NS16550_REG_SIZE 1
	304	#define CFG_NS16550_CLK get_bus_freq(0)
	305
	306	#define CFG_BAUDRATE_TABLE \
	307	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	308
d239d74b TT	309	#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
d239d74b TT	310	#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
5f820439 DL	311
	312	/* Use the HUSH parser */
	313	#define CFG_HUSH_PARSER
dd520bf3	314	#ifdef CFG_HUSH_PARSER
5f820439 DL	315	#define CFG_PROMPT_HUSH_PS2 "> "
	316	#endif
	317
bf0b542d KP	318	/* pass open firmware flat tree */
	319	#define CONFIG_OF_FLAT_TREE 1
	320	#define CONFIG_OF_BOARD_SETUP 1
	321
	322	/* maximum size of the flat tree (8K) */
	323	#define OF_FLAT_TREE_MAX_SIZE 8192
	324
	325	#define OF_CPU "PowerPC,8360@0"
	326	#define OF_SOC "soc8360@e0000000"
	327	#define OF_TBCLK (bd->bi_busfreq / 4)
	328	#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500"
	329
5f820439 DL	330	/* I2C */
	331	#define CONFIG_HARD_I2C /* I2C with hardware support */
	332	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
be5e6181 TT	333	#define CONFIG_FSL_I2C
be5e6181 TT	334	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
5f820439 DL	335	#define CFG_I2C_SLAVE 0x7F
	336	#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */
	337	#define CFG_I2C_OFFSET 0x3000
dd520bf3	338	#define CFG_I2C2_OFFSET 0x3100
5f820439 DL	339
	340	/*
	341	* Config on-board RTC
	342	*/
	343	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
	344	#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	345
	346	/*
	347	* General PCI
	348	* Addresses are mapped 1-1.
	349	*/
	350	#define CFG_PCI_MEM_BASE 0x80000000
	351	#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
	352	#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
	353	#define CFG_PCI_MMIO_BASE 0x90000000
	354	#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
	355	#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
	356	#define CFG_PCI_IO_BASE 0xE0300000
	357	#define CFG_PCI_IO_PHYS 0xE0300000
	358	#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
	359
	360	#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
	361	#define CFG_PCI_SLV_MEM_BUS 0x00000000
	362	#define CFG_PCI_SLV_MEM_SIZE 0x80000000
	363
	364
	365	#ifdef CONFIG_PCI
	366
	367	#define CONFIG_NET_MULTI
	368	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	369
	370	#undef CONFIG_EEPRO100
	371	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
dd520bf3	372	#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
5f820439 DL	373
	374	#endif /* CONFIG_PCI */
	375
	376
	377	#ifndef CONFIG_NET_MULTI
	378	#define CONFIG_NET_MULTI 1
	379	#endif
	380
7737d5c6 DL	381	/*
	382	* QE UEC ethernet configuration
	383	*/
	384	#define CONFIG_UEC_ETH
	385	#define CONFIG_ETHPRIME "Freescale GETH"
	386	#define CONFIG_PHY_MODE_NEED_CHANGE
	387
	388	#define CONFIG_UEC_ETH1 /* GETH1 */
	389
	390	#ifdef CONFIG_UEC_ETH1
	391	#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
	392	#define CFG_UEC1_RX_CLK QE_CLK_NONE
	393	#define CFG_UEC1_TX_CLK QE_CLK9
	394	#define CFG_UEC1_ETH_TYPE GIGA_ETH
	395	#define CFG_UEC1_PHY_ADDR 0
dd520bf3	396	#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
7737d5c6 DL	397	#endif
	398
	399	#define CONFIG_UEC_ETH2 /* GETH2 */
	400
	401	#ifdef CONFIG_UEC_ETH2
	402	#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
	403	#define CFG_UEC2_RX_CLK QE_CLK_NONE
	404	#define CFG_UEC2_TX_CLK QE_CLK4
	405	#define CFG_UEC2_ETH_TYPE GIGA_ETH
	406	#define CFG_UEC2_PHY_ADDR 1
dd520bf3	407	#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
7737d5c6 DL	408	#endif
7737d5c6 DL	409
5f820439 DL	410	/*
	411	* Environment
	412	*/
	413
	414	#ifndef CFG_RAMBOOT
	415	#define CFG_ENV_IS_IN_FLASH 1
	416	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
dd520bf3	417	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
5f820439 DL	418	#define CFG_ENV_SIZE 0x2000
	419	#else
	420	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	421	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	422	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	423	#define CFG_ENV_SIZE 0x2000
	424	#endif
	425
	426	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	427	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	428
	429	#if defined(CFG_RAMBOOT)
	430	#if defined(CONFIG_PCI)
dd520bf3	431	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
5f820439 DL	432	\| CFG_CMD_PING \
5f820439 DL	433	\| CFG_CMD_ASKENV \
dd520bf3 WD	434	\| CFG_CMD_PCI \
dd520bf3 WD	435	\| CFG_CMD_I2C) \
5f820439 DL	436	& \
	437	~(CFG_CMD_ENV \
	438	\| CFG_CMD_LOADS))
	439	#else
dd520bf3	440	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
5f820439 DL	441	\| CFG_CMD_PING \
	442	\| CFG_CMD_ASKENV \
	443	\| CFG_CMD_I2C) \
	444	& \
	445	~(CFG_CMD_ENV \
	446	\| CFG_CMD_LOADS))
	447	#endif
	448	#else
	449	#if defined(CONFIG_PCI)
dd520bf3	450	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
5f820439 DL	451	\| CFG_CMD_PCI \
	452	\| CFG_CMD_PING \
	453	\| CFG_CMD_ASKENV \
	454	\| CFG_CMD_I2C)
	455	#else
dd520bf3	456	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
5f820439 DL	457	\| CFG_CMD_PING \
	458	\| CFG_CMD_ASKENV \
	459	\| CFG_CMD_I2C )
	460	#endif
	461	#endif
	462
	463	#include <cmd_confdefs.h>
	464
	465	#undef CONFIG_WATCHDOG /* watchdog disabled */
	466
	467	/*
	468	* Miscellaneous configurable options
	469	*/
	470	#define CFG_LONGHELP /* undef to save memory */
	471	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	472	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	473
	474	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	475	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	476	#else
	477	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	478	#endif
	479
	480	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	481	#define CFG_MAXARGS 16 /* max number of command args */
	482	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	483	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	484
	485	/*
	486	* For booting Linux, the board info and command line data
	487	* have to be in the first 8 MB of memory, since this is
	488	* the maximum mapped by the Linux kernel during initialization.
	489	*/
	490	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	491
	492	/*
	493	* Core HID Setup
	494	*/
	495	#define CFG_HID0_INIT 0x000000000
	496	#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
	497	#define CFG_HID2 HID2_HBE
	498
	499	/*
	500	* Cache Config
	501	*/
	502	#define CFG_DCACHE_SIZE 32768
	503	#define CFG_CACHELINE_SIZE 32
	504	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	505	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value /
	506	#endif
	507
	508	/*
	509	* MMU Setup
	510	*/
	511
	512	/* DDR: cache cacheable */
	513	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	514	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	515	#define CFG_DBAT0L CFG_IBAT0L
	516	#define CFG_DBAT0U CFG_IBAT0U
	517
	518	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
d239d74b	519	#define CFG_IBAT1L (CFG_IMMR \| BATL_PP_10 \| \
5f820439	520	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
d239d74b	521	#define CFG_IBAT1U (CFG_IMMR \| BATU_BL_4M \| BATU_VS \| BATU_VP)
5f820439 DL	522	#define CFG_DBAT1L CFG_IBAT1L
	523	#define CFG_DBAT1U CFG_IBAT1U
	524
	525	/* BCSR: cache-inhibit and guarded */
	526	#define CFG_IBAT2L (CFG_BCSR \| BATL_PP_10 \| \
	527	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	528	#define CFG_IBAT2U (CFG_BCSR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	529	#define CFG_DBAT2L CFG_IBAT2L
	530	#define CFG_DBAT2U CFG_IBAT2U
	531
	532	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
	533	#define CFG_IBAT3L (CFG_FLASH_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	534	#define CFG_IBAT3U (CFG_FLASH_BASE \| BATU_BL_32M \| BATU_VS \| BATU_VP)
	535	#define CFG_DBAT3L (CFG_FLASH_BASE \| BATL_PP_10 \| \
	536	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	537	#define CFG_DBAT3U CFG_IBAT3U
	538
	539	/* Local bus SDRAM: cacheable */
	540	#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	541	#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	542	#define CFG_DBAT4L CFG_IBAT4L
	543	#define CFG_DBAT4U CFG_IBAT4U
	544
	545	/* Stack in dcache: cacheable, no memory coherence */
	546	#define CFG_IBAT5L (CFG_INIT_RAM_ADDR \| BATL_PP_10)
	547	#define CFG_IBAT5U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	548	#define CFG_DBAT5L CFG_IBAT5L
	549	#define CFG_DBAT5U CFG_IBAT5U
	550
	551	#ifdef CONFIG_PCI
	552	/* PCI MEM space: cacheable */
	553	#define CFG_IBAT6L (CFG_PCI_MEM_PHYS \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	554	#define CFG_IBAT6U (CFG_PCI_MEM_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	555	#define CFG_DBAT6L CFG_IBAT6L
	556	#define CFG_DBAT6U CFG_IBAT6U
	557	/* PCI MMIO space: cache-inhibit and guarded */
	558	#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS \| BATL_PP_10 \| \
	559	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	560	#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	561	#define CFG_DBAT7L CFG_IBAT7L
	562	#define CFG_DBAT7U CFG_IBAT7U
	563	#else
	564	#define CFG_IBAT6L (0)
	565	#define CFG_IBAT6U (0)
	566	#define CFG_IBAT7L (0)
	567	#define CFG_IBAT7U (0)
	568	#define CFG_DBAT6L CFG_IBAT6L
	569	#define CFG_DBAT6U CFG_IBAT6U
	570	#define CFG_DBAT7L CFG_IBAT7L
	571	#define CFG_DBAT7U CFG_IBAT7U
	572	#endif
	573
	574	/*
	575	* Internal Definitions
	576	*
	577	* Boot Flags
	578	*/
	579	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	580	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	581
	582	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	583	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
	584	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	585	#endif
586
587	/*
588	* Environment Configuration
589	*/
590
591	#define CONFIG_ENV_OVERWRITE
592
593	#if defined(CONFIG_UEC_ETH)
594	#define CONFIG_ETHADDR 00:04:9f:ef:01:01
595	#define CONFIG_HAS_ETH1
dd520bf3	596	#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
5f820439 DL	597	#endif
5f820439 DL	598
dd520bf3	599	#define CONFIG_BAUDRATE 115200
5f820439	600
dd520bf3	601	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
5f820439	602
dd520bf3 WD	603	#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
dd520bf3 WD	604	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
5f820439	605
dd520bf3 WD	606	#define CONFIG_EXTRA_ENV_SETTINGS \
	607	"netdev=eth0\0" \
	608	"consoledev=ttyS0\0" \
	609	"ramdiskaddr=1000000\0" \
5f820439	610	"ramdiskfile=ramfs.83xx\0" \
bf0b542d KP	611	"fdtaddr=400000\0" \
	612	"fdtfile=mpc8349emds.dtb\0" \
	613	""
5f820439	614
dd520bf3 WD	615	#define CONFIG_NFSBOOTCOMMAND \
	616	"setenv bootargs root=/dev/nfs rw " \
	617	"nfsroot=$serverip:$rootpath " \
bf0b542d	618	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
dd520bf3 WD	619	"console=$consoledev,$baudrate $othbootargs;" \
dd520bf3 WD	620	"tftp $loadaddr $bootfile;" \
bf0b542d KP	621	"tftp $fdtaddr $fdtfile;" \
bf0b542d KP	622	"bootm $loadaddr - $fdtaddr"
5f820439	623
bf0b542d	624	#define CONFIG_RAMBOOTCOMMAND \
dd520bf3 WD	625	"setenv bootargs root=/dev/ram rw " \
	626	"console=$consoledev,$baudrate $othbootargs;" \
	627	"tftp $ramdiskaddr $ramdiskfile;" \
	628	"tftp $loadaddr $bootfile;" \
bf0b542d KP	629	"tftp $fdtaddr $fdtfile;" \
	630	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	631
5f820439 DL	632
	633	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	634
	635	#endif /* __CONFIG_H */