[people/ms/u-boot.git] / include / configs / MPC8360ERDK.h

/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *                    Dave Liu <daveliu@freescale.com>
 *
 * Copyright (C) 2007 Logic Product Development, Inc.
 *                    Peter Barada <peterb@logicpd.com>
 *
 * Copyright (C) 2007 MontaVista Software, Inc.
 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_QE		1 /* Has QE */
#define CONFIG_MPC83XX		1 /* MPC83XX family */
#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360ERDK	1 /* MPC8360ERDK board specific */

/*
 * System Clock Setup
 */
#ifdef CONFIG_CLKIN_33MHZ
#define CONFIG_83XX_CLKIN		33000000
#define CONFIG_SYS_CLK_FREQ		33000000
#define PCI_33M				1
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_10X1
#else
#define CONFIG_83XX_CLKIN		66000000
#define CONFIG_SYS_CLK_FREQ		66000000
#define PCI_66M				1
#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_5X1
#endif /* CONFIG_CLKIN_33MHZ */

/*
 * Hardware Reset Configuration Word
 */
#define CFG_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
	HRCWL_CORE_TO_CSB_2X1 |\
	HRCWL_CE_TO_PLL_1X15)

#define CFG_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCICKDRV_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_SECONDARY_DDR_DISABLE |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_EARLY)

/*
 * System IO Config
 */
#define CFG_SICRH		0x00000000
#define CFG_SICRL		0x40000000

#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * IMMR new address
 */
#define CFG_IMMR		0xE0000000

/*
 * DDR Setup
 */
#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE		CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)

#define CFG_83XX_DDR_USES_CS0

#undef CONFIG_DDR_ECC		/* support DDR ECC function */
#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */

/*
 * DDRCDR - DDR Control Driver Register
 */
#define CFG_DDRCDR_VALUE	0x80080001

#undef CONFIG_SPD_EEPROM	/* Do not use SPD EEPROM for DDR setup */

/*
 * Manually set up DDR parameters
 */
#define CONFIG_DDR_II
#define CFG_DDR_SIZE		256 /* MB */
#define CFG_DDRCDR		0x80080001
#define CFG_DDR_CS0_BNDS	0x0000000f
#define CFG_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \
				 CSCONFIG_COL_BIT_10)
#define CFG_DDR_TIMING_0	0x00330903
#define CFG_DDR_TIMING_1	0x3835a322
#define CFG_DDR_TIMING_2	0x00104909
#define CFG_DDR_TIMING_3	0x00000000
#define CFG_DDR_CLK_CNTL	0x02000000
#define CFG_DDR_MODE		0x47800432
#define CFG_DDR_MODE2		0x8000c000
#define CFG_DDR_INTERVAL	0x045b0100
#define CFG_DDR_SDRAM_CFG	0x03000000
#define CFG_DDR_SDRAM_CFG2	0x00001000

/*
 * Memory test
 */
#undef CFG_DRAM_TEST		/* memory test, takes time */
#define CFG_MEMTEST_START	0x00000000 /* memtest region */
#define CFG_MEMTEST_END		0x00100000

/*
 * The reserved memory
 */
#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */
#define CFG_FLASH_BASE		0xFF800000 /* FLASH base address */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef	CFG_RAMBOOT
#endif

#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR		0x00000000

/*
 * FLASH on the Local Bus
 */
#define CFG_FLASH_CFI		/* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER	/* use the CFI driver */
#define CFG_FLASH_SIZE		8 /* max FLASH size is 32M */
#define CFG_FLASH_PROTECTION	1 /* Use intel Flash protection. */

#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */

#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | /* Flash Base address */ \
			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
			BR_V)	/* valid */
#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
				OR_GPCM_XACS | OR_GPCM_SCY_15 | \
				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)

#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */

#undef	CFG_FLASH_CHECKSUM

/*
 * NAND flash on the local bus
 */
#define CFG_NAND_BASE		0x60000000

#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
#define CFG_LBLAWAR1_PRELIM	0x8000001b /* Access window size 4K */

/* Port size 8 bit, UPMA */
#define CFG_BR1_PRELIM		(CFG_NAND_BASE | 0x00000881)
#define CFG_OR1_PRELIM		0xfc000001

/*
 * Fujitsu MB86277 (MINT) graphics controller
 */
#define CFG_VIDEO_BASE		0x70000000

#define CFG_LBLAWBAR2_PRELIM	CFG_VIDEO_BASE
#define CFG_LBLAWAR2_PRELIM	0x80000019 /* Access window size 64MB */

/* Port size 32 bit, UPMB */
#define CFG_BR2_PRELIM		(CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */
#define CFG_OR2_PRELIM		0xfc000001 /* (64MB, EAD=1) */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}

#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED	400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE	0x7F
#define CFG_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET	0x3000
#define CFG_I2C2_OFFSET 0x3100

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI	1

#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x10000000 /* 256M */
#define CFG_PCI1_MMIO_BASE	0x90000000
#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
#define CFG_PCI1_MMIO_SIZE	0x10000000 /* 256M */
#define CFG_PCI1_IO_BASE	0xE0300000
#define CFG_PCI1_IO_PHYS	0xE0300000
#define CFG_PCI1_IO_SIZE	0x100000 /* 1M */

#ifdef CONFIG_PCI

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */

#endif	/* CONFIG_PCI */


#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"FSL UEC0"

#define CONFIG_UEC_ETH1		/* GETH1 */

#ifdef CONFIG_UEC_ETH1
#define CFG_UEC1_UCC_NUM	0	/* UCC1 */
#define CFG_UEC1_RX_CLK		QE_CLK_NONE
#define CFG_UEC1_TX_CLK		QE_CLK9
#define CFG_UEC1_ETH_TYPE	GIGA_ETH
#define CFG_UEC1_PHY_ADDR	2
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
#endif

#define CONFIG_UEC_ETH2		/* GETH2 */

#ifdef CONFIG_UEC_ETH2
#define CFG_UEC2_UCC_NUM	1	/* UCC2 */
#define CFG_UEC2_RX_CLK		QE_CLK_NONE
#define CFG_UEC2_TX_CLK		QE_CLK4
#define CFG_UEC2_ETH_TYPE	GIGA_ETH
#define CFG_UEC2_PHY_ADDR	4
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
#endif

/*
 * Environment
 */

#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE		0x20000
#else /* CFG_RAMBOOT */
#define CFG_NO_FLASH		1	/* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE		0x2000
#endif /* CFG_RAMBOOT */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ASKENV

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif

#if defined(CFG_RAMBOOT)
#undef CONFIG_CMD_ENV
#undef CONFIG_CMD_LOADS
#endif

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		/* undef to save memory */
#define CFG_LOAD_ADDR		0x2000000 /* default load address */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CFG_HID0_INIT		0x000000000
#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2		HID2_HBE

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CFG_IBAT1L	(CFG_IMMR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT1U	(CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U

/* NAND: cache-inhibit and guarded */
#define CFG_IBAT2L	(CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
			 BATL_GUARDEDSTORAGE)
#define CFG_IBAT2U	(CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CFG_IBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_DBAT3L	(CFG_FLASH_BASE | BATL_PP_10 | \
			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U	CFG_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */
#define CFG_IBAT4L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
#define CFG_IBAT4U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT4L	CFG_IBAT4L
#define CFG_DBAT4U	CFG_IBAT4U

#define CFG_IBAT5L	(CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
			 BATL_GUARDEDSTORAGE)
#define CFG_IBAT5U	(CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT5L	CFG_IBAT5L
#define CFG_DBAT5U	CFG_IBAT5U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U
#else /* CONFIG_PCI */
#define CFG_IBAT6L	(0)
#define CFG_IBAT6U	(0)
#define CFG_IBAT7L	(0)
#define CFG_IBAT7U	(0)
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U
#endif /* CONFIG_PCI */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02 /* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_ETHADDR	00:04:9f:ef:01:01
#define CONFIG_ETH1ADDR	00:04:9f:ef:01:02
#define CONFIG_ETH2ADDR	00:04:9f:ef:01:03
#define CONFIG_ETH3ADDR	00:04:9f:ef:01:04
#endif

#define CONFIG_BAUDRATE 115200

#define CONFIG_LOADADDR	a00000
#define CONFIG_HOSTNAME	mpc8360erdk
#define CONFIG_BOOTFILE	uImage

#define CONFIG_IPADDR		10.0.0.99
#define CONFIG_SERVERIP		10.0.0.2
#define CONFIG_GATEWAYIP	10.0.0.2
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_ROOTPATH		/nfsroot/

#define	CONFIG_BOOTDELAY 2	/* -1 disables auto-boot */
#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_EXTRA_ENV_SETTINGS \
   "netdev=eth0\0"\
   "consoledev=ttyS0\0"\
   "loadaddr=a00000\0"\
   "fdtaddr=900000\0"\
   "bootfile=uImage\0"\
   "fdtfile=dtb\0"\
   "fsfile=fs\0"\
   "ubootfile=u-boot.bin\0"\
   "setbootargs=setenv bootargs console=$consoledev,$baudrate "\
   		"$mtdparts panic=1\0"\
   "adddhcpargs=setenv bootargs $bootargs ip=on\0"\
   "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
   		"$gatewayip:$netmask:$hostname:$netdev:off "\
   		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
   "tftp_get_uboot=tftp 100000 $ubootfile\0"\
   "tftp_get_kernel=tftp $loadaddr $bootfile\0"\
   "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
   "tftp_get_fs=tftp c00000 $fsfile\0"\
   "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
   		"cp.b 100000 ff800000 $filesize\0"\
   "boot_m=bootm $loadaddr - $fdtaddr\0"\
   "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
   		"boot_m\0"\
   "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
   		"boot_m\0"\
   ""

#define CONFIG_BOOTCOMMAND "run dhcpboot"

#endif /* __CONFIG_H */
Commit	Line	Data
fab6f556 AV	1	/*
	2	* Copyright (C) 2006 Freescale Semiconductor, Inc.
	3	* Dave Liu <daveliu@freescale.com>
	4	*
	5	* Copyright (C) 2007 Logic Product Development, Inc.
	6	* Peter Barada <peterb@logicpd.com>
	7	*
	8	* Copyright (C) 2007 MontaVista Software, Inc.
	9	* Anton Vorontsov <avorontsov@ru.mvista.com>
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
fab6f556 AV	20	/*
	21	* High Level Configuration Options
	22	*/
	23	#define CONFIG_E300 1 /* E300 family */
	24	#define CONFIG_QE 1 /* Has QE */
	25	#define CONFIG_MPC83XX 1 /* MPC83XX family */
	26	#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
	27	#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
	28
	29	/*
	30	* System Clock Setup
	31	*/
	32	#ifdef CONFIG_CLKIN_33MHZ
	33	#define CONFIG_83XX_CLKIN 33000000
	34	#define CONFIG_SYS_CLK_FREQ 33000000
	35	#define PCI_33M 1
	36	#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
	37	#else
	38	#define CONFIG_83XX_CLKIN 66000000
	39	#define CONFIG_SYS_CLK_FREQ 66000000
	40	#define PCI_66M 1
	41	#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
	42	#endif /* CONFIG_CLKIN_33MHZ */
	43
	44	/*
	45	* Hardware Reset Configuration Word
	46	*/
	47	#define CFG_HRCW_LOW (\
	48	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	49	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	50	HRCWL_CSB_TO_CLKIN_MPC8360ERDK \|\
	51	HRCWL_CORE_TO_CSB_2X1 \|\
	52	HRCWL_CE_TO_PLL_1X15)
	53
	54	#define CFG_HRCW_HIGH (\
	55	HRCWH_PCI_HOST \|\
	56	HRCWH_PCI1_ARBITER_ENABLE \|\
	57	HRCWH_PCICKDRV_ENABLE \|\
	58	HRCWH_CORE_ENABLE \|\
	59	HRCWH_FROM_0X00000100 \|\
	60	HRCWH_BOOTSEQ_DISABLE \|\
	61	HRCWH_SW_WATCHDOG_DISABLE \|\
	62	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	63	HRCWH_SECONDARY_DDR_DISABLE \|\
	64	HRCWH_BIG_ENDIAN \|\
	65	HRCWH_LALE_EARLY)
	66
	67	/*
	68	* System IO Config
	69	*/
	70	#define CFG_SICRH 0x00000000
	71	#define CFG_SICRL 0x40000000
	72
	73	#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
	74	#define CONFIG_BOARD_EARLY_INIT_R
	75
	76	/*
	77	* IMMR new address
	78	*/
	79	#define CFG_IMMR 0xE0000000
	80
	81	/*
	82	* DDR Setup
	83	*/
84	#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
85	#define CFG_SDRAM_BASE CFG_DDR_BASE
86	#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
87	#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \| \
88	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
89
90	#define CFG_83XX_DDR_USES_CS0
91
92	#undef CONFIG_DDR_ECC /* support DDR ECC function */
93	#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
94
95	/*
96	* DDRCDR - DDR Control Driver Register
97	*/
98	#define CFG_DDRCDR_VALUE 0x80080001
99
100	#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
101
102	/*
103	* Manually set up DDR parameters
104	*/
105	#define CONFIG_DDR_II
106	#define CFG_DDR_SIZE 256 /* MB */
107	#define CFG_DDRCDR 0x80080001
108	#define CFG_DDR_CS0_BNDS 0x0000000f
109	#define CFG_DDR_CS0_CONFIG (CSCONFIG_EN \| CSCONFIG_ROW_BIT_13 \| \
110	CSCONFIG_COL_BIT_10)
111	#define CFG_DDR_TIMING_0 0x00330903
112	#define CFG_DDR_TIMING_1 0x3835a322
113	#define CFG_DDR_TIMING_2 0x00104909
114	#define CFG_DDR_TIMING_3 0x00000000
115	#define CFG_DDR_CLK_CNTL 0x02000000
116	#define CFG_DDR_MODE 0x47800432
117	#define CFG_DDR_MODE2 0x8000c000
118	#define CFG_DDR_INTERVAL 0x045b0100
119	#define CFG_DDR_SDRAM_CFG 0x03000000
120	#define CFG_DDR_SDRAM_CFG2 0x00001000
121
122	/*
123	* Memory test
124	*/
125	#undef CFG_DRAM_TEST /* memory test, takes time */
126	#define CFG_MEMTEST_START 0x00000000 /* memtest region */
127	#define CFG_MEMTEST_END 0x00100000
128
129	/*
130	* The reserved memory
131	*/
132	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
133	#define CFG_FLASH_BASE 0xFF800000 /* FLASH base address */
134
135	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
136	#define CFG_RAMBOOT
137	#else
138	#undef CFG_RAMBOOT
139	#endif
140
141	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
142	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
143
144	/*
145	* Initial RAM Base Address Setup
146	*/
147	#define CFG_INIT_RAM_LOCK 1
148	#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
149	#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
150	#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
151	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
152
153	/*
154	* Local Bus Configuration & Clock Setup
155	*/
156	#define CFG_LCRR (LCRR_DBYP \| LCRR_CLKDIV_4)
157	#define CFG_LBC_LBCR 0x00000000
158
159	/*
160	* FLASH on the Local Bus
161	*/
162	#define CFG_FLASH_CFI /* use the Common Flash Interface */
163	#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
164	#define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */
165	#define CFG_FLASH_PROTECTION 1 /* Use intel Flash protection. */
166
167	#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
168	#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
169
170	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| /* Flash Base address */ \
171	(2 << BR_PS_SHIFT) \| /* 16 bit port size */ \
172	BR_V) /* valid */
173	#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) \| OR_UPM_XAM \| \
174	OR_GPCM_CSNT \| OR_GPCM_ACS_0b11 \| \
175	OR_GPCM_XACS \| OR_GPCM_SCY_15 \| \
176	OR_GPCM_TRLX \| OR_GPCM_EHTR \| OR_GPCM_EAD)
177
178	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
179	#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
180
181	#undef CFG_FLASH_CHECKSUM
182
183	/*
184	* NAND flash on the local bus
185	*/
186	#define CFG_NAND_BASE 0x60000000
187
188	#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
189	#define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */
190
191	/* Port size 8 bit, UPMA */
192	#define CFG_BR1_PRELIM (CFG_NAND_BASE \| 0x00000881)
193	#define CFG_OR1_PRELIM 0xfc000001
194
195	/*
196	* Fujitsu MB86277 (MINT) graphics controller
197	*/
198	#define CFG_VIDEO_BASE 0x70000000
199
200	#define CFG_LBLAWBAR2_PRELIM CFG_VIDEO_BASE
201	#define CFG_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */
202
203	/* Port size 32 bit, UPMB */
204	#define CFG_BR2_PRELIM (CFG_VIDEO_BASE \| 0x000018a1) /* PS=11, UPMB */
205	#define CFG_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */
206
207	/*
208	* Serial Port
209	*/
210	#define CONFIG_CONS_INDEX 1
211	#undef CONFIG_SERIAL_SOFTWARE_FIFO
212	#define CFG_NS16550
213	#define CFG_NS16550_SERIAL
214	#define CFG_NS16550_REG_SIZE 1
215	#define CFG_NS16550_CLK get_bus_freq(0)
216
217	#define CFG_BAUDRATE_TABLE \
218	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,}
219
220	#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
221	#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
222
223	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
224	/* Use the HUSH parser */
225	#define CFG_HUSH_PARSER
226	#ifdef CFG_HUSH_PARSER
227	#define CFG_PROMPT_HUSH_PS2 "> "
228	#endif
229
230	/* Pass open firmware flat tree */
231	#define CONFIG_OF_LIBFDT 1
232	#define CONFIG_OF_BOARD_SETUP 1
233
234	/* I2C */
235	#define CONFIG_HARD_I2C /* I2C with hardware support */
236	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
237	#define CONFIG_FSL_I2C
238	#define CONFIG_I2C_MULTI_BUS
239	#define CONFIG_I2C_CMD_TREE
240	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
241	#define CFG_I2C_SLAVE 0x7F
2b2f43ed	242	#define CFG_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */
fab6f556 AV	243	#define CFG_I2C_OFFSET 0x3000
	244	#define CFG_I2C2_OFFSET 0x3100
	245
	246	/*
	247	* General PCI
	248	* Addresses are mapped 1-1.
	249	*/
	250	#define CONFIG_PCI
	251	#define CONFIG_83XX_GENERIC_PCI 1
	252
	253	#define CFG_PCI1_MEM_BASE 0x80000000
	254	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	255	#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
	256	#define CFG_PCI1_MMIO_BASE 0x90000000
	257	#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
	258	#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	259	#define CFG_PCI1_IO_BASE 0xE0300000
	260	#define CFG_PCI1_IO_PHYS 0xE0300000
	261	#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
	262
	263	#ifdef CONFIG_PCI
	264
	265	#define CONFIG_NET_MULTI
	266	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	267
	268	#undef CONFIG_EEPRO100
	269	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	270	#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	271
	272	#endif /* CONFIG_PCI */
	273
	274
	275	#ifndef CONFIG_NET_MULTI
	276	#define CONFIG_NET_MULTI 1
	277	#endif
	278
	279	/*
	280	* QE UEC ethernet configuration
	281	*/
	282	#define CONFIG_UEC_ETH
711a7946	283	#define CONFIG_ETHPRIME "FSL UEC0"
fab6f556 AV	284
	285	#define CONFIG_UEC_ETH1 /* GETH1 */
	286
	287	#ifdef CONFIG_UEC_ETH1
	288	#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
	289	#define CFG_UEC1_RX_CLK QE_CLK_NONE
	290	#define CFG_UEC1_TX_CLK QE_CLK9
	291	#define CFG_UEC1_ETH_TYPE GIGA_ETH
	292	#define CFG_UEC1_PHY_ADDR 2
	293	#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
	294	#endif
	295
	296	#define CONFIG_UEC_ETH2 /* GETH2 */
	297
	298	#ifdef CONFIG_UEC_ETH2
	299	#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
	300	#define CFG_UEC2_RX_CLK QE_CLK_NONE
	301	#define CFG_UEC2_TX_CLK QE_CLK4
	302	#define CFG_UEC2_ETH_TYPE GIGA_ETH
	303	#define CFG_UEC2_PHY_ADDR 4
	304	#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
	305	#endif
	306
	307	/*
	308	* Environment
	309	*/
	310
	311	#ifndef CFG_RAMBOOT
	312	#define CFG_ENV_IS_IN_FLASH 1
	313	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
	314	#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	315	#define CFG_ENV_SIZE 0x20000
	316	#else /* CFG_RAMBOOT */
	317	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	318	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	319	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	320	#define CFG_ENV_SIZE 0x2000
	321	#endif /* CFG_RAMBOOT */
	322
	323	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	324	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	325
	326	/*
	327	* BOOTP options
	328	*/
	329	#define CONFIG_BOOTP_BOOTFILESIZE
	330	#define CONFIG_BOOTP_BOOTPATH
	331	#define CONFIG_BOOTP_GATEWAY
	332	#define CONFIG_BOOTP_HOSTNAME
	333
	334
	335	/*
	336	* Command line configuration.
	337	*/
	338	#include <config_cmd_default.h>
	339
	340	#define CONFIG_CMD_PING
	341	#define CONFIG_CMD_I2C
	342	#define CONFIG_CMD_ASKENV
	343
	344	#if defined(CONFIG_PCI)
	345	#define CONFIG_CMD_PCI
	346	#endif
	347
348	#if defined(CFG_RAMBOOT)
349	#undef CONFIG_CMD_ENV
350	#undef CONFIG_CMD_LOADS
351	#endif
352
353	#undef CONFIG_WATCHDOG /* watchdog disabled */
354
355	/*
356	* Miscellaneous configurable options
357	*/
358	#define CFG_LONGHELP /* undef to save memory */
359	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
360	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
361
362	#if defined(CONFIG_CMD_KGDB)
363	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
364	#else
365	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
366	#endif
367
368	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
369	#define CFG_MAXARGS 16 /* max number of command args */
370	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
371	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
372
373	/*
374	* For booting Linux, the board info and command line data
375	* have to be in the first 8 MB of memory, since this is
376	* the maximum mapped by the Linux kernel during initialization.
377	*/
378	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
379
380	/*
381	* Core HID Setup
382	*/
383	#define CFG_HID0_INIT 0x000000000
384	#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
385	#define CFG_HID2 HID2_HBE
386
fab6f556 AV	387	/*
	388	* MMU Setup
	389	*/
	390
	391	/* DDR: cache cacheable */
	392	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	393	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	394	#define CFG_DBAT0L CFG_IBAT0L
	395	#define CFG_DBAT0U CFG_IBAT0U
	396
	397	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
	398	#define CFG_IBAT1L (CFG_IMMR \| BATL_PP_10 \| \
	399	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	400	#define CFG_IBAT1U (CFG_IMMR \| BATU_BL_4M \| BATU_VS \| BATU_VP)
	401	#define CFG_DBAT1L CFG_IBAT1L
	402	#define CFG_DBAT1U CFG_IBAT1U
	403
	404	/* NAND: cache-inhibit and guarded */
	405	#define CFG_IBAT2L (CFG_NAND_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT \|\
	406	BATL_GUARDEDSTORAGE)
	407	#define CFG_IBAT2U (CFG_NAND_BASE \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	408	#define CFG_DBAT2L CFG_IBAT2L
	409	#define CFG_DBAT2U CFG_IBAT2U
	410
	411	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
	412	#define CFG_IBAT3L (CFG_FLASH_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	413	#define CFG_IBAT3U (CFG_FLASH_BASE \| BATU_BL_32M \| BATU_VS \| BATU_VP)
	414	#define CFG_DBAT3L (CFG_FLASH_BASE \| BATL_PP_10 \| \
	415	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	416	#define CFG_DBAT3U CFG_IBAT3U
	417
	418	/* Stack in dcache: cacheable, no memory coherence */
	419	#define CFG_IBAT4L (CFG_INIT_RAM_ADDR \| BATL_PP_10)
	420	#define CFG_IBAT4U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	421	#define CFG_DBAT4L CFG_IBAT4L
	422	#define CFG_DBAT4U CFG_IBAT4U
	423
	424	#define CFG_IBAT5L (CFG_VIDEO_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT \| \
	425	BATL_GUARDEDSTORAGE)
	426	#define CFG_IBAT5U (CFG_VIDEO_BASE \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	427	#define CFG_DBAT5L CFG_IBAT5L
	428	#define CFG_DBAT5U CFG_IBAT5U
	429
	430	#ifdef CONFIG_PCI
	431	/* PCI MEM space: cacheable */
	432	#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	433	#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	434	#define CFG_DBAT6L CFG_IBAT6L
	435	#define CFG_DBAT6U CFG_IBAT6U
	436	/* PCI MMIO space: cache-inhibit and guarded */
	437	#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS \| BATL_PP_10 \| \
	438	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	439	#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	440	#define CFG_DBAT7L CFG_IBAT7L
	441	#define CFG_DBAT7U CFG_IBAT7U
	442	#else /* CONFIG_PCI */
	443	#define CFG_IBAT6L (0)
	444	#define CFG_IBAT6U (0)
	445	#define CFG_IBAT7L (0)
	446	#define CFG_IBAT7U (0)
	447	#define CFG_DBAT6L CFG_IBAT6L
	448	#define CFG_DBAT6U CFG_IBAT6U
	449	#define CFG_DBAT7L CFG_IBAT7L
	450	#define CFG_DBAT7U CFG_IBAT7U
451	#endif /* CONFIG_PCI */
452
453	/*
454	* Internal Definitions
455	*
456	* Boot Flags
457	*/
458	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
459	#define BOOTFLAG_WARM 0x02 /* Software reboot */
460
461	#if defined(CONFIG_CMD_KGDB)
462	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
463	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
464	#endif
465
466	/*
467	* Environment Configuration
468	*/
469	#define CONFIG_ENV_OVERWRITE
470
471	#if defined(CONFIG_UEC_ETH)
472	#define CONFIG_HAS_ETH0
473	#define CONFIG_HAS_ETH1
474	#define CONFIG_HAS_ETH2
475	#define CONFIG_HAS_ETH3
476	#define CONFIG_ETHADDR 00:04:9f:ef:01:01
477	#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
478	#define CONFIG_ETH2ADDR 00:04:9f:ef:01:03
479	#define CONFIG_ETH3ADDR 00:04:9f:ef:01:04
480	#endif
481
482	#define CONFIG_BAUDRATE 115200
483
484	#define CONFIG_LOADADDR a00000
485	#define CONFIG_HOSTNAME mpc8360erdk
486	#define CONFIG_BOOTFILE uImage
487
488	#define CONFIG_IPADDR 10.0.0.99
489	#define CONFIG_SERVERIP 10.0.0.2
490	#define CONFIG_GATEWAYIP 10.0.0.2
491	#define CONFIG_NETMASK 255.255.255.0
492	#define CONFIG_ROOTPATH /nfsroot/
493
494	#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
495	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
496
497	#define CONFIG_EXTRA_ENV_SETTINGS \
498	"netdev=eth0\0"\
499	"consoledev=ttyS0\0"\
500	"loadaddr=a00000\0"\
501	"fdtaddr=900000\0"\
502	"bootfile=uImage\0"\
503	"fdtfile=dtb\0"\
504	"fsfile=fs\0"\
505	"ubootfile=u-boot.bin\0"\
506	"setbootargs=setenv bootargs console=$consoledev,$baudrate "\
507	"$mtdparts panic=1\0"\
508	"adddhcpargs=setenv bootargs $bootargs ip=on\0"\
509	"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\
510	"$gatewayip:$netmask:$hostname:$netdev:off "\
511	"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\
512	"tftp_get_uboot=tftp 100000 $ubootfile\0"\
513	"tftp_get_kernel=tftp $loadaddr $bootfile\0"\
514	"tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\
515	"tftp_get_fs=tftp c00000 $fsfile\0"\
516	"nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\
517	"cp.b 100000 ff800000 $filesize\0"\
518	"boot_m=bootm $loadaddr - $fdtaddr\0"\
519	"dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\
520	"boot_m\0"\
521	"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
522	"boot_m\0"\
523	""
524
525	#define CONFIG_BOOTCOMMAND "run dhcpboot"
526
527	#endif /* __CONFIG_H */