projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| fab6f556 AV |
1 | /* |
| 2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
| 3 | * Dave Liu <daveliu@freescale.com> | |
| 4 | * | |
| 5 | * Copyright (C) 2007 Logic Product Development, Inc. | |
| 6 | * Peter Barada <peterb@logicpd.com> | |
| 7 | * | |
| 8 | * Copyright (C) 2007 MontaVista Software, Inc. | |
| 9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of | |
| 14 | * the License, or (at your option) any later version. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef __CONFIG_H | |
| 18 | #define __CONFIG_H | |
| 19 | ||
| 20 | #undef DEBUG | |
| 21 | ||
| 22 | /* | |
| 23 | * High Level Configuration Options | |
| 24 | */ | |
| 25 | #define CONFIG_E300 1 /* E300 family */ | |
| 26 | #define CONFIG_QE 1 /* Has QE */ | |
| 27 | #define CONFIG_MPC83XX 1 /* MPC83XX family */ | |
| 28 | #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ | |
| 29 | #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ | |
| 30 | ||
| 31 | /* | |
| 32 | * System Clock Setup | |
| 33 | */ | |
| 34 | #ifdef CONFIG_CLKIN_33MHZ | |
| 35 | #define CONFIG_83XX_CLKIN 33000000 | |
| 36 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
| 37 | #define PCI_33M 1 | |
| 38 | #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 | |
| 39 | #else | |
| 40 | #define CONFIG_83XX_CLKIN 66000000 | |
| 41 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
| 42 | #define PCI_66M 1 | |
| 43 | #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 | |
| 44 | #endif /* CONFIG_CLKIN_33MHZ */ | |
| 45 | ||
| 46 | /* | |
| 47 | * Hardware Reset Configuration Word | |
| 48 | */ | |
| 49 | #define CFG_HRCW_LOW (\ | |
| 50 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
| 51 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 52 | HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\ | |
| 53 | HRCWL_CORE_TO_CSB_2X1 |\ | |
| 54 | HRCWL_CE_TO_PLL_1X15) | |
| 55 | ||
| 56 | #define CFG_HRCW_HIGH (\ | |
| 57 | HRCWH_PCI_HOST |\ | |
| 58 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 59 | HRCWH_PCICKDRV_ENABLE |\ | |
| 60 | HRCWH_CORE_ENABLE |\ | |
| 61 | HRCWH_FROM_0X00000100 |\ | |
| 62 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 63 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 64 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 65 | HRCWH_SECONDARY_DDR_DISABLE |\ | |
| 66 | HRCWH_BIG_ENDIAN |\ | |
| 67 | HRCWH_LALE_EARLY) | |
| 68 | ||
| 69 | /* | |
| 70 | * System IO Config | |
| 71 | */ | |
| 72 | #define CFG_SICRH 0x00000000 | |
| 73 | #define CFG_SICRL 0x40000000 | |
| 74 | ||
| 75 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
| 76 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 77 | ||
| 78 | /* | |
| 79 | * IMMR new address | |
| 80 | */ | |
| 81 | #define CFG_IMMR 0xE0000000 | |
| 82 | ||
| 83 | /* | |
| 84 | * DDR Setup | |
| 85 | */ | |
| 86 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ | |
| 87 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
| 88 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
| 89 | #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
| 90 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
| 91 | ||
| 92 | #define CFG_83XX_DDR_USES_CS0 | |
| 93 | ||
| 94 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
| 95 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
| 96 | ||
| 97 | /* | |
| 98 | * DDRCDR - DDR Control Driver Register | |
| 99 | */ | |
| 100 | #define CFG_DDRCDR_VALUE 0x80080001 | |
| 101 | ||
| 102 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ | |
| 103 | ||
| 104 | /* | |
| 105 | * Manually set up DDR parameters | |
| 106 | */ | |
| 107 | #define CONFIG_DDR_II | |
| 108 | #define CFG_DDR_SIZE 256 /* MB */ | |
| 109 | #define CFG_DDRCDR 0x80080001 | |
| 110 | #define CFG_DDR_CS0_BNDS 0x0000000f | |
| 111 | #define CFG_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ | |
| 112 | CSCONFIG_COL_BIT_10) | |
| 113 | #define CFG_DDR_TIMING_0 0x00330903 | |
| 114 | #define CFG_DDR_TIMING_1 0x3835a322 | |
| 115 | #define CFG_DDR_TIMING_2 0x00104909 | |
| 116 | #define CFG_DDR_TIMING_3 0x00000000 | |
| 117 | #define CFG_DDR_CLK_CNTL 0x02000000 | |
| 118 | #define CFG_DDR_MODE 0x47800432 | |
| 119 | #define CFG_DDR_MODE2 0x8000c000 | |
| 120 | #define CFG_DDR_INTERVAL 0x045b0100 | |
| 121 | #define CFG_DDR_SDRAM_CFG 0x03000000 | |
| 122 | #define CFG_DDR_SDRAM_CFG2 0x00001000 | |
| 123 | ||
| 124 | /* | |
| 125 | * Memory test | |
| 126 | */ | |
| 127 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
| 128 | #define CFG_MEMTEST_START 0x00000000 /* memtest region */ | |
| 129 | #define CFG_MEMTEST_END 0x00100000 | |
| 130 | ||
| 131 | /* | |
| 132 | * The reserved memory | |
| 133 | */ | |
| 134 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 135 | #define CFG_FLASH_BASE 0xFF800000 /* FLASH base address */ | |
| 136 | ||
| 137 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 138 | #define CFG_RAMBOOT | |
| 139 | #else | |
| 140 | #undef CFG_RAMBOOT | |
| 141 | #endif | |
| 142 | ||
| 143 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 144 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 145 | ||
| 146 | /* | |
| 147 | * Initial RAM Base Address Setup | |
| 148 | */ | |
| 149 | #define CFG_INIT_RAM_LOCK 1 | |
| 150 | #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
| 151 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
| 152 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
| 153 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 154 | ||
| 155 | /* | |
| 156 | * Local Bus Configuration & Clock Setup | |
| 157 | */ | |
| 158 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) | |
| 159 | #define CFG_LBC_LBCR 0x00000000 | |
| 160 | ||
| 161 | /* | |
| 162 | * FLASH on the Local Bus | |
| 163 | */ | |
| 164 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
| 165 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 166 | #define CFG_FLASH_SIZE 8 /* max FLASH size is 32M */ | |
| 167 | #define CFG_FLASH_PROTECTION 1 /* Use intel Flash protection. */ | |
| 168 | ||
| 169 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ | |
| 170 | #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
| 171 | ||
| 172 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ | |
| 173 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | |
| 174 | BR_V) /* valid */ | |
| 175 | #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ | |
| 176 | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ | |
| 177 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ | |
| 178 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
| 179 | ||
| 180 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 181 | #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ | |
| 182 | ||
| 183 | #undef CFG_FLASH_CHECKSUM | |
| 184 | ||
| 185 | /* | |
| 186 | * NAND flash on the local bus | |
| 187 | */ | |
| 188 | #define CFG_NAND_BASE 0x60000000 | |
| 189 | ||
| 190 | #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE | |
| 191 | #define CFG_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ | |
| 192 | ||
| 193 | /* Port size 8 bit, UPMA */ | |
| 194 | #define CFG_BR1_PRELIM (CFG_NAND_BASE | 0x00000881) | |
| 195 | #define CFG_OR1_PRELIM 0xfc000001 | |
| 196 | ||
| 197 | /* | |
| 198 | * Fujitsu MB86277 (MINT) graphics controller | |
| 199 | */ | |
| 200 | #define CFG_VIDEO_BASE 0x70000000 | |
| 201 | ||
| 202 | #define CFG_LBLAWBAR2_PRELIM CFG_VIDEO_BASE | |
| 203 | #define CFG_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */ | |
| 204 | ||
| 205 | /* Port size 32 bit, UPMB */ | |
| 206 | #define CFG_BR2_PRELIM (CFG_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */ | |
| 207 | #define CFG_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */ | |
| 208 | ||
| 209 | /* | |
| 210 | * Serial Port | |
| 211 | */ | |
| 212 | #define CONFIG_CONS_INDEX 1 | |
| 213 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 214 | #define CFG_NS16550 | |
| 215 | #define CFG_NS16550_SERIAL | |
| 216 | #define CFG_NS16550_REG_SIZE 1 | |
| 217 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 218 | ||
| 219 | #define CFG_BAUDRATE_TABLE \ | |
| 220 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200,} | |
| 221 | ||
| 222 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) | |
| 223 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
| 224 | ||
| 225 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 226 | /* Use the HUSH parser */ | |
| 227 | #define CFG_HUSH_PARSER | |
| 228 | #ifdef CFG_HUSH_PARSER | |
| 229 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 230 | #endif | |
| 231 | ||
| 232 | /* Pass open firmware flat tree */ | |
| 233 | #define CONFIG_OF_LIBFDT 1 | |
| 234 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 235 | ||
| 236 | /* I2C */ | |
| 237 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 238 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 239 | #define CONFIG_FSL_I2C | |
| 240 | #define CONFIG_I2C_MULTI_BUS | |
| 241 | #define CONFIG_I2C_CMD_TREE | |
| 242 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 243 | #define CFG_I2C_SLAVE 0x7F | |
| 244 | #define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ | |
| 245 | #define CFG_I2C_OFFSET 0x3000 | |
| 246 | #define CFG_I2C2_OFFSET 0x3100 | |
| 247 | ||
| 248 | /* | |
| 249 | * General PCI | |
| 250 | * Addresses are mapped 1-1. | |
| 251 | */ | |
| 252 | #define CONFIG_PCI | |
| 253 | #define CONFIG_83XX_GENERIC_PCI 1 | |
| 254 | ||
| 255 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
| 256 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
| 257 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 258 | #define CFG_PCI1_MMIO_BASE 0x90000000 | |
| 259 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE | |
| 260 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 261 | #define CFG_PCI1_IO_BASE 0xE0300000 | |
| 262 | #define CFG_PCI1_IO_PHYS 0xE0300000 | |
| 263 | #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ | |
| 264 | ||
| 265 | #ifdef CONFIG_PCI | |
| 266 | ||
| 267 | #define CONFIG_NET_MULTI | |
| 268 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 269 | ||
| 270 | #undef CONFIG_EEPRO100 | |
| 271 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 272 | #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
| 273 | ||
| 274 | #endif /* CONFIG_PCI */ | |
| 275 | ||
| 276 | ||
| 277 | #ifndef CONFIG_NET_MULTI | |
| 278 | #define CONFIG_NET_MULTI 1 | |
| 279 | #endif | |
| 280 | ||
| 281 | /* | |
| 282 | * QE UEC ethernet configuration | |
| 283 | */ | |
| 284 | #define CONFIG_UEC_ETH | |
| 285 | #define CONFIG_ETHPRIME "Freescale GETH" | |
| 286 | ||
| 287 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
| 288 | ||
| 289 | #ifdef CONFIG_UEC_ETH1 | |
| 290 | #define CFG_UEC1_UCC_NUM 0 /* UCC1 */ | |
| 291 | #define CFG_UEC1_RX_CLK QE_CLK_NONE | |
| 292 | #define CFG_UEC1_TX_CLK QE_CLK9 | |
| 293 | #define CFG_UEC1_ETH_TYPE GIGA_ETH | |
| 294 | #define CFG_UEC1_PHY_ADDR 2 | |
| 295 | #define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII | |
| 296 | #endif | |
| 297 | ||
| 298 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
| 299 | ||
| 300 | #ifdef CONFIG_UEC_ETH2 | |
| 301 | #define CFG_UEC2_UCC_NUM 1 /* UCC2 */ | |
| 302 | #define CFG_UEC2_RX_CLK QE_CLK_NONE | |
| 303 | #define CFG_UEC2_TX_CLK QE_CLK4 | |
| 304 | #define CFG_UEC2_ETH_TYPE GIGA_ETH | |
| 305 | #define CFG_UEC2_PHY_ADDR 4 | |
| 306 | #define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII | |
| 307 | #endif | |
| 308 | ||
| 309 | /* | |
| 310 | * Environment | |
| 311 | */ | |
| 312 | ||
| 313 | #ifndef CFG_RAMBOOT | |
| 314 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 315 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
| 316 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
| 317 | #define CFG_ENV_SIZE 0x20000 | |
| 318 | #else /* CFG_RAMBOOT */ | |
| 319 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
| 320 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 321 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
| 322 | #define CFG_ENV_SIZE 0x2000 | |
| 323 | #endif /* CFG_RAMBOOT */ | |
| 324 | ||
| 325 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 326 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 327 | ||
| 328 | /* | |
| 329 | * BOOTP options | |
| 330 | */ | |
| 331 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 332 | #define CONFIG_BOOTP_BOOTPATH | |
| 333 | #define CONFIG_BOOTP_GATEWAY | |
| 334 | #define CONFIG_BOOTP_HOSTNAME | |
| 335 | ||
| 336 | ||
| 337 | /* | |
| 338 | * Command line configuration. | |
| 339 | */ | |
| 340 | #include <config_cmd_default.h> | |
| 341 | ||
| 342 | #define CONFIG_CMD_PING | |
| 343 | #define CONFIG_CMD_I2C | |
| 344 | #define CONFIG_CMD_ASKENV | |
| 345 | ||
| 346 | #if defined(CONFIG_PCI) | |
| 347 | #define CONFIG_CMD_PCI | |
| 348 | #endif | |
| 349 | ||
| 350 | #if defined(CFG_RAMBOOT) | |
| 351 | #undef CONFIG_CMD_ENV | |
| 352 | #undef CONFIG_CMD_LOADS | |
| 353 | #endif | |
| 354 | ||
| 355 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 356 | ||
| 357 | /* | |
| 358 | * Miscellaneous configurable options | |
| 359 | */ | |
| 360 | #define CFG_LONGHELP /* undef to save memory */ | |
| 361 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
| 362 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 363 | ||
| 364 | #if defined(CONFIG_CMD_KGDB) | |
| 365 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 366 | #else | |
| 367 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 368 | #endif | |
| 369 | ||
| 370 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 371 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 372 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 373 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 374 | ||
| 375 | /* | |
| 376 | * For booting Linux, the board info and command line data | |
| 377 | * have to be in the first 8 MB of memory, since this is | |
| 378 | * the maximum mapped by the Linux kernel during initialization. | |
| 379 | */ | |
| 380 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 381 | ||
| 382 | /* | |
| 383 | * Core HID Setup | |
| 384 | */ | |
| 385 | #define CFG_HID0_INIT 0x000000000 | |
| 386 | #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
| 387 | #define CFG_HID2 HID2_HBE | |
| 388 | ||
| 389 | /* | |
| 390 | * Cache Config | |
| 391 | */ | |
| 392 | #define CFG_DCACHE_SIZE 32768 | |
| 393 | #define CFG_CACHELINE_SIZE 32 | |
| 394 | #if defined(CONFIG_CMD_KGDB) | |
| 395 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ | |
| 396 | #endif | |
| 397 | ||
| 398 | /* | |
| 399 | * MMU Setup | |
| 400 | */ | |
| 401 | ||
| 402 | /* DDR: cache cacheable */ | |
| 403 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 404 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 405 | #define CFG_DBAT0L CFG_IBAT0L | |
| 406 | #define CFG_DBAT0U CFG_IBAT0U | |
| 407 | ||
| 408 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
| 409 | #define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ | |
| 410 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 411 | #define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) | |
| 412 | #define CFG_DBAT1L CFG_IBAT1L | |
| 413 | #define CFG_DBAT1U CFG_IBAT1U | |
| 414 | ||
| 415 | /* NAND: cache-inhibit and guarded */ | |
| 416 | #define CFG_IBAT2L (CFG_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ | |
| 417 | BATL_GUARDEDSTORAGE) | |
| 418 | #define CFG_IBAT2U (CFG_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP) | |
| 419 | #define CFG_DBAT2L CFG_IBAT2L | |
| 420 | #define CFG_DBAT2U CFG_IBAT2U | |
| 421 | ||
| 422 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
| 423 | #define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 424 | #define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 425 | #define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ | |
| 426 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 427 | #define CFG_DBAT3U CFG_IBAT3U | |
| 428 | ||
| 429 | /* Stack in dcache: cacheable, no memory coherence */ | |
| 430 | #define CFG_IBAT4L (CFG_INIT_RAM_ADDR | BATL_PP_10) | |
| 431 | #define CFG_IBAT4U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 432 | #define CFG_DBAT4L CFG_IBAT4L | |
| 433 | #define CFG_DBAT4U CFG_IBAT4U | |
| 434 | ||
| 435 | #define CFG_IBAT5L (CFG_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \ | |
| 436 | BATL_GUARDEDSTORAGE) | |
| 437 | #define CFG_IBAT5U (CFG_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP) | |
| 438 | #define CFG_DBAT5L CFG_IBAT5L | |
| 439 | #define CFG_DBAT5U CFG_IBAT5U | |
| 440 | ||
| 441 | #ifdef CONFIG_PCI | |
| 442 | /* PCI MEM space: cacheable */ | |
| 443 | #define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 444 | #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 445 | #define CFG_DBAT6L CFG_IBAT6L | |
| 446 | #define CFG_DBAT6U CFG_IBAT6U | |
| 447 | /* PCI MMIO space: cache-inhibit and guarded */ | |
| 448 | #define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ | |
| 449 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 450 | #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 451 | #define CFG_DBAT7L CFG_IBAT7L | |
| 452 | #define CFG_DBAT7U CFG_IBAT7U | |
| 453 | #else /* CONFIG_PCI */ | |
| 454 | #define CFG_IBAT6L (0) | |
| 455 | #define CFG_IBAT6U (0) | |
| 456 | #define CFG_IBAT7L (0) | |
| 457 | #define CFG_IBAT7U (0) | |
| 458 | #define CFG_DBAT6L CFG_IBAT6L | |
| 459 | #define CFG_DBAT6U CFG_IBAT6U | |
| 460 | #define CFG_DBAT7L CFG_IBAT7L | |
| 461 | #define CFG_DBAT7U CFG_IBAT7U | |
| 462 | #endif /* CONFIG_PCI */ | |
| 463 | ||
| 464 | /* | |
| 465 | * Internal Definitions | |
| 466 | * | |
| 467 | * Boot Flags | |
| 468 | */ | |
| 469 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 470 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 471 | ||
| 472 | #if defined(CONFIG_CMD_KGDB) | |
| 473 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
| 474 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 475 | #endif | |
| 476 | ||
| 477 | /* | |
| 478 | * Environment Configuration | |
| 479 | */ | |
| 480 | #define CONFIG_ENV_OVERWRITE | |
| 481 | ||
| 482 | #if defined(CONFIG_UEC_ETH) | |
| 483 | #define CONFIG_HAS_ETH0 | |
| 484 | #define CONFIG_HAS_ETH1 | |
| 485 | #define CONFIG_HAS_ETH2 | |
| 486 | #define CONFIG_HAS_ETH3 | |
| 487 | #define CONFIG_ETHADDR 00:04:9f:ef:01:01 | |
| 488 | #define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 | |
| 489 | #define CONFIG_ETH2ADDR 00:04:9f:ef:01:03 | |
| 490 | #define CONFIG_ETH3ADDR 00:04:9f:ef:01:04 | |
| 491 | #endif | |
| 492 | ||
| 493 | #define CONFIG_BAUDRATE 115200 | |
| 494 | ||
| 495 | #define CONFIG_LOADADDR a00000 | |
| 496 | #define CONFIG_HOSTNAME mpc8360erdk | |
| 497 | #define CONFIG_BOOTFILE uImage | |
| 498 | ||
| 499 | #define CONFIG_IPADDR 10.0.0.99 | |
| 500 | #define CONFIG_SERVERIP 10.0.0.2 | |
| 501 | #define CONFIG_GATEWAYIP 10.0.0.2 | |
| 502 | #define CONFIG_NETMASK 255.255.255.0 | |
| 503 | #define CONFIG_ROOTPATH /nfsroot/ | |
| 504 | ||
| 505 | #define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ | |
| 506 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 507 | ||
| 508 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 509 | "netdev=eth0\0"\ | |
| 510 | "consoledev=ttyS0\0"\ | |
| 511 | "loadaddr=a00000\0"\ | |
| 512 | "fdtaddr=900000\0"\ | |
| 513 | "bootfile=uImage\0"\ | |
| 514 | "fdtfile=dtb\0"\ | |
| 515 | "fsfile=fs\0"\ | |
| 516 | "ubootfile=u-boot.bin\0"\ | |
| 517 | "setbootargs=setenv bootargs console=$consoledev,$baudrate "\ | |
| 518 | "$mtdparts panic=1\0"\ | |
| 519 | "adddhcpargs=setenv bootargs $bootargs ip=on\0"\ | |
| 520 | "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"\ | |
| 521 | "$gatewayip:$netmask:$hostname:$netdev:off "\ | |
| 522 | "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"\ | |
| 523 | "tftp_get_uboot=tftp 100000 $ubootfile\0"\ | |
| 524 | "tftp_get_kernel=tftp $loadaddr $bootfile\0"\ | |
| 525 | "tftp_get_dtb=tftp $fdtaddr $fdtfile\0"\ | |
| 526 | "tftp_get_fs=tftp c00000 $fsfile\0"\ | |
| 527 | "nor_reflash=protect off ff800000 ff87ffff ; erase ff800000 ff87ffff ; "\ | |
| 528 | "cp.b 100000 ff800000 $filesize\0"\ | |
| 529 | "boot_m=bootm $loadaddr - $fdtaddr\0"\ | |
| 530 | "dhcpboot=run setbootargs adddhcpargs tftp_get_kernel tftp_get_dtb "\ | |
| 531 | "boot_m\0"\ | |
| 532 | "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ | |
| 533 | "boot_m\0"\ | |
| 534 | "" | |
| 535 | ||
| 536 | #define CONFIG_BOOTCOMMAND "run dhcpboot" | |
| 537 | ||
| 538 | #endif /* __CONFIG_H */ |