[thirdparty/u-boot.git] / include / configs / MPC837XERDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 * Kevin Lam <kevin.lam@freescale.com>
 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */

#define CONFIG_HWCONFIG

/*
 * On-board devices
 */
#define CONFIG_VSC7385_ENET

/* System performance - define the value i.e. CONFIG_SYS_XXX
*/

/* System Clock Configuration Register */
#define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
#define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH		0x08200000
#define CONFIG_SYS_SICRL		0x00000000

/*
 * Output Buffer Impedance
 */
#define CONFIG_SYS_OBIR		0x30100000

/*
 * Device configurations
 */

/* Vitesse 7385 */

#ifdef CONFIG_VSC7385_ENET

#define CONFIG_TSEC2

/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE		0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE	8192

#endif

/*
 * DDR Setup
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
#define CONFIG_SYS_83XX_DDR_USES_CS0

#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)

#undef CONFIG_DDR_ECC		/* support DDR ECC function */
#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */

#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */

/*
 * Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE		256		/* MB */
#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
					| CSCONFIG_ODT_WR_ONLY_CURRENT \
					| CSCONFIG_ROW_BIT_13 \
					| CSCONFIG_COL_BIT_10)

#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00260802 */ /* DDR400 */
#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
				| (13 << TIMING_CFG1_REFREC_SHIFT) \
				| (3 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x3937d322 */
#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (5 << TIMING_CFG2_CPO_SHIFT) \
				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x02984cc8 */

#define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x06090100 */

#if defined(CONFIG_DDR_2T_TIMING)
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
					| SDRAM_CFG_32_BE \
					| SDRAM_CFG_2T_EN)
					/* 0x43088000 */
#else
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
					| SDRAM_CFG_SDRAM_TYPE_DDR2)
					/* 0x43000000 */
#endif
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
					| (0x0442 << SDRAM_MODE_SD_SHIFT))
					/* 0x04400442 */ /* DDR400 */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef	CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */


#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

/*
 * NAND Flash on the Local Bus
 */
#define CONFIG_SYS_NAND_BASE	0xE0600000


/* Vitesse 7385 */

#define CONFIG_SYS_VSC7385_BASE	0xF0000000

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* SERDES */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000
#define CONFIG_FSL_SERDES2	0xe3100

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_PCI_IO_BASE		0x00000000
#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000

#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

#define CONFIG_SYS_PCIE2_BASE		0xC0000000
#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE

#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#endif	/* CONFIG_PCI */

/*
 * TSEC
 */
#ifdef CONFIG_TSEC_ENET

#define CONFIG_GMII			/* MII PHY management */

#define CONFIG_TSEC1

#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME		"TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET		0x24000
#define TSEC1_PHY_ADDR			2
#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX			0
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME		"TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET		0x25000
#define TSEC2_PHY_ADDR			0x1c
#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHYIDX			0
#endif

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC0"

#endif

/*
 * SATA
 */
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1_OFFSET	0x18000
#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2_OFFSET	0x19000
#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA

#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#endif

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

#define CONFIG_NETDEV		"eth1"

#define CONFIG_HOSTNAME		"mpc837x_rdb"
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
#define CONFIG_BOOTFILE		"uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot.bin"
#define CONFIG_FDTFILE		"mpc8379_rdb.dtb"

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		800000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0"				\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftp $loadaddr $uboot;"				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=780000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"					\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5e918a98 KP	2	/*
	3	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	4	* Kevin Lam <kevin.lam@freescale.com>
	5	* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5e918a98 KP	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	*/
	14	#define CONFIG_E300 1 /* E300 family */
5e918a98	15
c9646ed7	16	#define CONFIG_HWCONFIG
89c7784e TT	17
	18	/*
	19	* On-board devices
	20	*/
89c7784e TT	21	#define CONFIG_VSC7385_ENET
89c7784e TT	22
6d0f6bcf	23	/* System performance - define the value i.e. CONFIG_SYS_XXX
5e918a98 KP	24	*/
5e918a98 KP	25
5e918a98	26	/* System Clock Configuration Register */
6d0f6bcf JCPV	27	#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
6d0f6bcf JCPV	28	#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
5afe9722	29	#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
5e918a98 KP	30
	31	/*
	32	* System IO Config
	33	*/
6d0f6bcf JCPV	34	#define CONFIG_SYS_SICRH 0x08200000
6d0f6bcf JCPV	35	#define CONFIG_SYS_SICRL 0x00000000
5e918a98 KP	36
	37	/*
	38	* Output Buffer Impedance
	39	*/
6d0f6bcf	40	#define CONFIG_SYS_OBIR 0x30100000
5e918a98	41
89c7784e TT	42	/*
	43	* Device configurations
	44	*/
	45
	46	/* Vitesse 7385 */
	47
	48	#ifdef CONFIG_VSC7385_ENET
	49
	50	#define CONFIG_TSEC2
	51
	52	/* The flash address and size of the VSC7385 firmware image */
	53	#define CONFIG_VSC7385_IMAGE 0xFE7FE000
	54	#define CONFIG_VSC7385_IMAGE_SIZE 8192
	55
	56	#endif
	57
5e918a98 KP	58	/*
	59	* DDR Setup
	60	*/
8a81bfd2	61	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
6d0f6bcf JCPV	62	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
6d0f6bcf JCPV	63	#define CONFIG_SYS_83XX_DDR_USES_CS0
5e918a98	64
6d0f6bcf	65	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \| DDRCDR_ODT \| DDRCDR_Q_DRN)
5e918a98 KP	66
	67	#undef CONFIG_DDR_ECC /* support DDR ECC function */
	68	#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
	69
	70	#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
	71
	72	/*
	73	* Manually set up DDR parameters
	74	*/
6d0f6bcf	75	#define CONFIG_SYS_DDR_SIZE 256 /* MB */
2fef4020 JH	76	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
	77	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
	78	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
	79	\| CSCONFIG_ROW_BIT_13 \
	80	\| CSCONFIG_COL_BIT_10)
5e918a98	81
6d0f6bcf JCPV	82	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
6d0f6bcf JCPV	83	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
5e918a98 KP	84	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	85	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	86	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	87	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	88	\| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	89	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	90	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
5e918a98	91	/* 0x00260802 / / DDR400 */
6d0f6bcf	92	#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
5e918a98 KP	93	\| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	94	\| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
	95	\| (7 << TIMING_CFG1_CASLAT_SHIFT) \
	96	\| (13 << TIMING_CFG1_REFREC_SHIFT) \
	97	\| (3 << TIMING_CFG1_WRREC_SHIFT) \
	98	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	99	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
5e918a98	100	/* 0x3937d322 */
2fef4020 JH	101	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
	102	\| (5 << TIMING_CFG2_CPO_SHIFT) \
	103	\| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	104	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	105	\| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	106	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	107	\| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
	108	/* 0x02984cc8 */
5e918a98	109
8eceeb7f KP	110	#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
8eceeb7f KP	111	\| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
5e918a98 KP	112	/* 0x06090100 */
	113
	114	#if defined(CONFIG_DDR_2T_TIMING)
5afe9722	115	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
2fef4020 JH	116	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
	117	\| SDRAM_CFG_32_BE \
	118	\| SDRAM_CFG_2T_EN)
	119	/* 0x43088000 */
5e918a98	120	#else
5afe9722	121	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
2fef4020	122	\| SDRAM_CFG_SDRAM_TYPE_DDR2)
5afe9722	123	/* 0x43000000 */
5e918a98	124	#endif
6d0f6bcf	125	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
8eceeb7f	126	#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
5afe9722 JH	127	\| (0x0442 << SDRAM_MODE_SD_SHIFT))
5afe9722 JH	128	/* 0x04400442 / / DDR400 */
6d0f6bcf	129	#define CONFIG_SYS_DDR_MODE2 0x00000000
5e918a98 KP	130
	131	/*
	132	* Memory test
	133	*/
6d0f6bcf	134	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
5e918a98 KP	135
	136	/*
	137	* The reserved memory
	138	*/
14d0a02a	139	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
5e918a98	140
6d0f6bcf JCPV	141	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	142	#define CONFIG_SYS_RAMBOOT
5e918a98	143	#else
6d0f6bcf	144	#undef CONFIG_SYS_RAMBOOT
5e918a98 KP	145	#endif
5e918a98 KP	146
16c8c170	147	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
5afe9722	148	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
5e918a98 KP	149
	150	/*
	151	* Initial RAM Base Address Setup
	152	*/
6d0f6bcf JCPV	153	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	154	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
553f0982	155	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
5afe9722 JH	156	#define CONFIG_SYS_GBL_DATA_OFFSET \
5afe9722 JH	157	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
5e918a98	158
5e918a98 KP	159	/*
	160	* FLASH on the Local Bus
	161	*/
6d0f6bcf JCPV	162	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
6d0f6bcf JCPV	163	#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
5e918a98	164
5afe9722	165	#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
5e918a98	166
5e918a98	167
6d0f6bcf JCPV	168	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
6d0f6bcf JCPV	169	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
5e918a98	170
6d0f6bcf JCPV	171	#undef CONFIG_SYS_FLASH_CHECKSUM
	172	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	173	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
5e918a98	174
46a3aeea AV	175	/*
	176	* NAND Flash on the Local Bus
	177	*/
7d6a0982	178	#define CONFIG_SYS_NAND_BASE 0xE0600000
a8f97539	179
a8f97539	180
89c7784e TT	181	/* Vitesse 7385 */
89c7784e TT	182
6d0f6bcf	183	#define CONFIG_SYS_VSC7385_BASE 0xF0000000
5e918a98	184
5e918a98 KP	185	/*
	186	* Serial Port
	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_NS16550_SERIAL
	189	#define CONFIG_SYS_NS16550_REG_SIZE 1
	190	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
5e918a98	191
6d0f6bcf	192	#define CONFIG_SYS_BAUDRATE_TABLE \
5afe9722	193	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
5e918a98	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	196	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
5e918a98	197
2bd7460e AV	198	/* SERDES */
	199	#define CONFIG_FSL_SERDES
	200	#define CONFIG_FSL_SERDES1 0xe3000
	201	#define CONFIG_FSL_SERDES2 0xe3100
	202
5e918a98	203	/* I2C */
00f792e0 HS	204	#define CONFIG_SYS_I2C
	205	#define CONFIG_SYS_I2C_FSL
	206	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	207	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	208	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	209	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
5e918a98 KP	210
	211	/*
	212	* Config on-board RTC
	213	*/
	214	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
6d0f6bcf	215	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
5e918a98 KP	216
	217	/*
	218	* General PCI
	219	* Addresses are mapped 1-1.
	220	*/
5afe9722 JH	221	#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
	222	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
	223	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
6d0f6bcf JCPV	224	#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
	225	#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
	226	#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
	227	#define CONFIG_SYS_PCI_IO_BASE 0x00000000
	228	#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
	229	#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
	230
	231	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
	232	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
	233	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
5e918a98	234
7e915580 AV	235	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	236	#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
	237	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
	238	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
	239	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
	240	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	241	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	242	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
	243	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	244
	245	#define CONFIG_SYS_PCIE2_BASE 0xC0000000
	246	#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
	247	#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
	248	#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
	249	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
	250	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
	251	#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
	252	#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
	253	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
	254
5e918a98	255	#ifdef CONFIG_PCI
842033e6	256	#define CONFIG_PCI_INDIRECT_BRIDGE
5e918a98	257
5e918a98	258	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	259	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
5e918a98 KP	260	#endif /* CONFIG_PCI */
5e918a98 KP	261
5e918a98 KP	262	/*
	263	* TSEC
	264	*/
89c7784e	265	#ifdef CONFIG_TSEC_ENET
5e918a98	266
89c7784e TT	267	#define CONFIG_GMII /* MII PHY management */
	268
	269	#define CONFIG_TSEC1
	270
	271	#ifdef CONFIG_TSEC1
	272	#define CONFIG_HAS_ETH0
5e918a98	273	#define CONFIG_TSEC1_NAME "TSEC0"
6d0f6bcf	274	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
5e918a98	275	#define TSEC1_PHY_ADDR 2
5e918a98	276	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
5e918a98	277	#define TSEC1_PHYIDX 0
89c7784e	278	#endif
5e918a98	279
89c7784e TT	280	#ifdef CONFIG_TSEC2
	281	#define CONFIG_HAS_ETH1
	282	#define CONFIG_TSEC2_NAME "TSEC1"
6d0f6bcf	283	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
89c7784e TT	284	#define TSEC2_PHY_ADDR 0x1c
	285	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	286	#define TSEC2_PHYIDX 0
	287	#endif
5e918a98 KP	288
	289	/* Options are: TSEC[0-1] */
	290	#define CONFIG_ETHPRIME "TSEC0"
	291
89c7784e TT	292	#endif
89c7784e TT	293
730e7929 KP	294	/*
	295	* SATA
	296	*/
6d0f6bcf	297	#define CONFIG_SYS_SATA_MAX_DEVICE 2
730e7929	298	#define CONFIG_SATA1
6d0f6bcf	299	#define CONFIG_SYS_SATA1_OFFSET 0x18000
5afe9722 JH	300	#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
5afe9722 JH	301	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
730e7929	302	#define CONFIG_SATA2
6d0f6bcf	303	#define CONFIG_SYS_SATA2_OFFSET 0x19000
5afe9722 JH	304	#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
5afe9722 JH	305	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
730e7929 KP	306
	307	#ifdef CONFIG_FSL_SATA
	308	#define CONFIG_LBA48
730e7929 KP	309	#endif
730e7929 KP	310
5e918a98 KP	311	/*
	312	* Environment
	313	*/
5e918a98 KP	314
5e918a98 KP	315	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	316	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
5e918a98 KP	317
	318	/*
	319	* BOOTP options
	320	*/
	321	#define CONFIG_BOOTP_BOOTFILESIZE
5e918a98	322
5e918a98 KP	323	/*
	324	* Command line configuration.
	325	*/
5e918a98	326
5e918a98 KP	327	#undef CONFIG_WATCHDOG /* watchdog disabled */
5e918a98 KP	328
c9646ed7	329	#ifdef CONFIG_MMC
a6da8b81	330	#define CONFIG_FSL_ESDHC_PIN_MUX
c9646ed7	331	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
c9646ed7 AV	332	#endif
c9646ed7 AV	333
5e918a98 KP	334	/*
	335	* Miscellaneous configurable options
	336	*/
5afe9722	337	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
5e918a98	338
5e918a98 KP	339	/*
5e918a98 KP	340	* For booting Linux, the board info and command line data
9f530d59	341	* have to be in the first 256 MB of memory, since this is
5e918a98 KP	342	* the maximum mapped by the Linux kernel during initialization.
5e918a98 KP	343	*/
5afe9722	344	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
63865278	345	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
5e918a98	346
5e918a98 KP	347	#if defined(CONFIG_CMD_KGDB)
5e918a98 KP	348	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
5e918a98 KP	349	#endif
	350
	351	/*
	352	* Environment Configuration
	353	*/
	354	#define CONFIG_ENV_OVERWRITE
	355
18e69a35	356	#define CONFIG_HAS_FSL_DR_USB
6c3c5750 NB	357	#define CONFIG_USB_EHCI_FSL
6c3c5750 NB	358	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
18e69a35	359
5afe9722	360	#define CONFIG_NETDEV "eth1"
5e918a98	361
5bc0543d	362	#define CONFIG_HOSTNAME "mpc837x_rdb"
8b3637c6	363	#define CONFIG_ROOTPATH "/nfsroot"
5afe9722	364	#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
b3f44c21	365	#define CONFIG_BOOTFILE "uImage"
5afe9722 JH	366	/* U-Boot image on TFTP server */
	367	#define CONFIG_UBOOTPATH "u-boot.bin"
	368	#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
5e918a98	369
5afe9722 JH	370	/* default location for tftp and bootm */
5afe9722 JH	371	#define CONFIG_LOADADDR 800000
5e918a98	372
5e918a98	373	#define CONFIG_EXTRA_ENV_SETTINGS \
5afe9722 JH	374	"netdev=" CONFIG_NETDEV "\0" \
5afe9722 JH	375	"uboot=" CONFIG_UBOOTPATH "\0" \
5e918a98	376	"tftpflash=tftp $loadaddr $uboot;" \
5368c55d MV	377	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	378	" +$filesize; " \
	379	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	380	" +$filesize; " \
	381	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	382	" $filesize; " \
	383	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	384	" +$filesize; " \
	385	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	386	" $filesize\0" \
79f516bc	387	"fdtaddr=780000\0" \
5afe9722	388	"fdtfile=" CONFIG_FDTFILE "\0" \
5e918a98	389	"ramdiskaddr=1000000\0" \
5afe9722	390	"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
5e918a98 KP	391	"console=ttyS0\0" \
	392	"setbootargs=setenv bootargs " \
	393	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	394	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
5afe9722 JH	395	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
5afe9722 JH	396	"$netdev:off " \
5e918a98 KP	397	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
	398
	399	#define CONFIG_NFSBOOTCOMMAND \
	400	"setenv rootdev /dev/nfs;" \
	401	"run setbootargs;" \
	402	"run setipargs;" \
	403	"tftp $loadaddr $bootfile;" \
	404	"tftp $fdtaddr $fdtfile;" \
	405	"bootm $loadaddr - $fdtaddr"
	406
	407	#define CONFIG_RAMBOOTCOMMAND \
	408	"setenv rootdev /dev/ram;" \
	409	"run setbootargs;" \
	410	"tftp $ramdiskaddr $ramdiskfile;" \
	411	"tftp $loadaddr $bootfile;" \
	412	"tftp $fdtaddr $fdtfile;" \
	413	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	414
5e918a98	415	#endif /* __CONFIG_H */