projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9490a7f1 | 1 | /* |
| 4bc6eb79 | 2 | * Copyright 2008-2009 Freescale Semiconductor, Inc. |
| 9490a7f1 KG |
3 | * |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * mpc8536ds board configuration file | |
| 25 | * | |
| 26 | */ | |
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 0e905ac2 | 30 | #ifdef CONFIG_MK_36BIT |
| 337f9fde KG |
31 | #define CONFIG_PHYS_64BIT 1 |
| 32 | #endif | |
| 33 | ||
| 9a1a0aed MH |
34 | #ifdef CONFIG_MK_NAND |
| 35 | #define CONFIG_NAND_U_BOOT 1 | |
| 36 | #define CONFIG_RAMBOOT_NAND 1 | |
| 37 | #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 | |
| 38 | #endif | |
| 39 | ||
| e40ac487 MH |
40 | #ifdef CONFIG_MK_SDCARD |
| 41 | #define CONFIG_RAMBOOT_SDCARD 1 | |
| 42 | #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 | |
| 43 | #endif | |
| 44 | ||
| 45 | #ifdef CONFIG_MK_SPIFLASH | |
| 46 | #define CONFIG_RAMBOOT_SPIFLASH 1 | |
| 47 | #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 | |
| 48 | #endif | |
| 49 | ||
| 9490a7f1 KG |
50 | /* High Level Configuration Options */ |
| 51 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 52 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 53 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 54 | #define CONFIG_MPC8536 1 | |
| 55 | #define CONFIG_MPC8536DS 1 | |
| 56 | ||
| c51fc5d5 | 57 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| 9490a7f1 KG |
58 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 59 | #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ | |
| 60 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
| 61 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 62 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
| 63 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 64 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 0151cbac | 65 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 9490a7f1 KG |
66 | |
| 67 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
| f6155c6f | 68 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
| 9490a7f1 KG |
69 | |
| 70 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 71 | #define CONFIG_ENV_OVERWRITE | |
| 72 | ||
| 9490a7f1 KG |
73 | #ifndef __ASSEMBLY__ |
| 74 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 75 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
| 76 | #endif | |
| 77 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
| c0391111 | 78 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) |
| 9490a7f1 KG |
79 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| 80 | #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq | |
| 81 | from ICS307 instead of switches */ | |
| 82 | ||
| 83 | /* | |
| 84 | * These can be toggled for performance analysis, otherwise use default. | |
| 85 | */ | |
| 86 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 87 | #define CONFIG_BTB /* toggle branch predition */ | |
| 9490a7f1 | 88 | |
| 80522dc8 AF |
89 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 90 | ||
| 9490a7f1 KG |
91 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 92 | ||
| 337f9fde KG |
93 | #ifdef CONFIG_PHYS_64BIT |
| 94 | #define CONFIG_ADDR_MAP 1 | |
| 95 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 96 | #endif | |
| 97 | ||
| 07355700 MH |
98 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ |
| 99 | #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ | |
| 9490a7f1 KG |
100 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 101 | ||
| 9a1a0aed MH |
102 | /* |
| 103 | * Config the L2 Cache as L2 SRAM | |
| 104 | */ | |
| 105 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 106 | #ifdef CONFIG_PHYS_64BIT | |
| 107 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
| 108 | #else | |
| 109 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 110 | #endif | |
| 111 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
| 112 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 113 | ||
| 9490a7f1 KG |
114 | /* |
| 115 | * Base addresses -- Note these are effective addresses where the | |
| 116 | * actual resources get mapped (not physical addresses) | |
| 117 | */ | |
| 6d0f6bcf | 118 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 337f9fde | 119 | #ifdef CONFIG_PHYS_64BIT |
| 07355700 | 120 | #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ |
| 337f9fde | 121 | #else |
| 07355700 | 122 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR |
| 337f9fde | 123 | #endif |
| 07355700 | 124 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| 9490a7f1 | 125 | |
| 9a1a0aed MH |
126 | #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) |
| 127 | #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR | |
| 128 | #else | |
| 129 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 130 | #endif | |
| 131 | ||
| 07355700 MH |
132 | #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) |
| 133 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) | |
| 134 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) | |
| 135 | #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) | |
| 9490a7f1 KG |
136 | |
| 137 | /* DDR Setup */ | |
| 337f9fde | 138 | #define CONFIG_VERY_BIG_RAM |
| 9490a7f1 KG |
139 | #define CONFIG_FSL_DDR2 |
| 140 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 141 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 142 | #define CONFIG_DDR_SPD | |
| 143 | #undef CONFIG_DDR_DLL | |
| 144 | ||
| 9b0ad1b1 | 145 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 9490a7f1 KG |
146 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 147 | ||
| 6d0f6bcf JCPV |
148 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 149 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 9490a7f1 KG |
150 | |
| 151 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 152 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 153 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 154 | ||
| 155 | /* I2C addresses of SPD EEPROMs */ | |
| 156 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
| 6d0f6bcf | 157 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
| 9490a7f1 KG |
158 | |
| 159 | /* These are used when DDR doesn't use SPD. */ | |
| 07355700 | 160 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 6d0f6bcf | 161 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
| 07355700 | 162 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
| 6d0f6bcf JCPV |
163 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 164 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 165 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
| 166 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
| 167 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
| 168 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 169 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
| 170 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 171 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 172 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 173 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
| 07355700 | 174 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ |
| 6d0f6bcf JCPV |
175 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
| 176 | ||
| 177 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 178 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 179 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
| 9490a7f1 | 180 | |
| 9490a7f1 KG |
181 | /* Make sure required options are set */ |
| 182 | #ifndef CONFIG_SPD_EEPROM | |
| 183 | #error ("CONFIG_SPD_EEPROM is required") | |
| 184 | #endif | |
| 185 | ||
| 186 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 187 | ||
| 188 | ||
| 189 | /* | |
| 190 | * Memory map -- xxx -this is wrong, needs updating | |
| 191 | * | |
| 192 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 193 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
| 194 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
| 195 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
| 196 | * | |
| 197 | * Localbus cacheable (TBD) | |
| 198 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 199 | * | |
| 200 | * Localbus non-cacheable | |
| c57fc289 | 201 | * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable |
| 9490a7f1 | 202 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
| c57fc289 | 203 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| 9490a7f1 KG |
204 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 205 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 206 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 207 | */ | |
| 208 | ||
| 209 | /* | |
| 210 | * Local Bus Definitions | |
| 211 | */ | |
| 6d0f6bcf | 212 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| 337f9fde KG |
213 | #ifdef CONFIG_PHYS_64BIT |
| 214 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
| 215 | #else | |
| c953ddfd | 216 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 337f9fde | 217 | #endif |
| 9490a7f1 | 218 | |
| 9a1a0aed | 219 | #define CONFIG_FLASH_BR_PRELIM \ |
| 07355700 MH |
220 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ |
| 221 | | BR_PS_16 | BR_V) | |
| 9a1a0aed | 222 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
| 9490a7f1 | 223 | |
| 07355700 MH |
224 | #define CONFIG_SYS_BR1_PRELIM \ |
| 225 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | |
| 226 | | BR_PS_16 | BR_V) | |
| c953ddfd | 227 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
| 9490a7f1 | 228 | |
| 07355700 MH |
229 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ |
| 230 | CONFIG_SYS_FLASH_BASE_PHYS } | |
| 6d0f6bcf | 231 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 9490a7f1 KG |
232 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 233 | ||
| 07355700 MH |
234 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 235 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 6d0f6bcf | 236 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 07355700 MH |
237 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 238 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 9490a7f1 | 239 | |
| 6d0f6bcf | 240 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 9490a7f1 | 241 | |
| e40ac487 MH |
242 | #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ |
| 243 | || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) | |
| 9a1a0aed MH |
244 | #define CONFIG_SYS_RAMBOOT |
| 245 | #else | |
| 246 | #undef CONFIG_SYS_RAMBOOT | |
| 247 | #endif | |
| 248 | ||
| 9490a7f1 | 249 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
250 | #define CONFIG_SYS_FLASH_CFI |
| 251 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 252 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 9490a7f1 KG |
253 | |
| 254 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 255 | ||
| 256 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ | |
| 257 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
| 337f9fde KG |
258 | #ifdef CONFIG_PHYS_64BIT |
| 259 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
| 260 | #else | |
| 52b565f5 | 261 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| 337f9fde | 262 | #endif |
| 9490a7f1 | 263 | |
| 52b565f5 | 264 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| 07355700 | 265 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| 9490a7f1 KG |
266 | |
| 267 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
| 268 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 269 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 270 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
| 271 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 272 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
| 273 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
| 274 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 275 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
| 276 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 277 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
| 278 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 279 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 280 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
| 281 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 6bb5b412 KG |
282 | #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ |
| 283 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
| 284 | #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ | |
| 285 | #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ | |
| 286 | #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ | |
| 287 | #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ | |
| 288 | #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ | |
| 9490a7f1 KG |
289 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 290 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 291 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
| 292 | #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ | |
| 293 | #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ | |
| 294 | #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ | |
| 295 | #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ | |
| 296 | #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ | |
| 297 | #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ | |
| 298 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
| 299 | #define PIXIS_LED 0x25 /* LED Register */ | |
| 300 | ||
| 9a1a0aed MH |
301 | #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ |
| 302 | ||
| 9490a7f1 KG |
303 | /* old pixis referenced names */ |
| 304 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 305 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 306 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
| 9490a7f1 | 307 | |
| 6d0f6bcf JCPV |
308 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 309 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 310 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
| 9490a7f1 | 311 | |
| 6d0f6bcf | 312 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 07355700 MH |
313 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 314 | (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 6d0f6bcf | 315 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 9490a7f1 | 316 | |
| 07355700 MH |
317 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 318 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 9490a7f1 | 319 | |
| 9a1a0aed | 320 | #ifndef CONFIG_NAND_SPL |
| 337f9fde KG |
321 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 322 | #ifdef CONFIG_PHYS_64BIT | |
| 323 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
| 324 | #else | |
| 325 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 326 | #endif | |
| 9a1a0aed MH |
327 | #else |
| 328 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
| 329 | #ifdef CONFIG_PHYS_64BIT | |
| 330 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
| 331 | #else | |
| 332 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 333 | #endif | |
| 334 | #endif | |
| c57fc289 JJ |
335 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 336 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
| 337 | CONFIG_SYS_NAND_BASE + 0x80000, \ | |
| 338 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
| 339 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
| c57fc289 JJ |
340 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 341 | #define CONFIG_CMD_NAND 1 | |
| 342 | #define CONFIG_NAND_FSL_ELBC 1 | |
| 343 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 344 | ||
| 9a1a0aed MH |
345 | /* NAND boot: 4K NAND loader config */ |
| 346 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
| 347 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
| 348 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
| 349 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
| 350 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
| 351 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
| 352 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 353 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 354 | ||
| c57fc289 | 355 | /* NAND flash config */ |
| 07355700 MH |
356 | #define CONFIG_NAND_BR_PRELIM \ |
| 357 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 358 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 359 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 360 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 361 | | BR_V) /* valid */ | |
| 362 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
| 363 | | OR_FCM_PGS /* Large Page*/ \ | |
| 364 | | OR_FCM_CSCT \ | |
| 365 | | OR_FCM_CST \ | |
| 366 | | OR_FCM_CHT \ | |
| 367 | | OR_FCM_SCY_1 \ | |
| 368 | | OR_FCM_TRLX \ | |
| 369 | | OR_FCM_EHTR) | |
| 370 | ||
| 9a1a0aed MH |
371 | #ifdef CONFIG_RAMBOOT_NAND |
| 372 | #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
| 373 | #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 374 | #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 375 | #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 376 | #else | |
| 377 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 378 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 07355700 MH |
379 | #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ |
| 380 | #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 9a1a0aed | 381 | #endif |
| 07355700 MH |
382 | |
| 383 | #define CONFIG_SYS_BR4_PRELIM \ | |
| 384 | (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ | |
| 385 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 386 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 387 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 388 | | BR_V) /* valid */ | |
| 389 | #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 390 | #define CONFIG_SYS_BR5_PRELIM \ | |
| 391 | (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ | |
| 392 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 393 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 394 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 395 | | BR_V) /* valid */ | |
| 396 | #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 397 | ||
| 398 | #define CONFIG_SYS_BR6_PRELIM \ | |
| 399 | (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ | |
| 400 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 401 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 402 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 403 | | BR_V) /* valid */ | |
| 404 | #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| c57fc289 | 405 | |
| 9490a7f1 KG |
406 | /* Serial Port - controlled on board with jumper J8 |
| 407 | * open - index 2 | |
| 408 | * shorted - index 1 | |
| 409 | */ | |
| 410 | #define CONFIG_CONS_INDEX 1 | |
| 411 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 6d0f6bcf JCPV |
412 | #define CONFIG_SYS_NS16550 |
| 413 | #define CONFIG_SYS_NS16550_SERIAL | |
| 414 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 415 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 93341909 KG |
416 | #ifdef CONFIG_NAND_SPL |
| 417 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 418 | #endif | |
| 9490a7f1 | 419 | |
| 6d0f6bcf | 420 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 9490a7f1 KG |
421 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 422 | ||
| 07355700 MH |
423 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) |
| 424 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
| 9490a7f1 KG |
425 | |
| 426 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
427 | #define CONFIG_SYS_HUSH_PARSER |
| 428 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 429 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 9490a7f1 KG |
430 | #endif |
| 431 | ||
| 432 | /* | |
| 433 | * Pass open firmware flat tree | |
| 434 | */ | |
| 435 | #define CONFIG_OF_LIBFDT 1 | |
| 436 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 437 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 438 | ||
| 9490a7f1 KG |
439 | /* |
| 440 | * I2C | |
| 441 | */ | |
| 442 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 443 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 444 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 445 | #define CONFIG_I2C_MULTI_BUS | |
| 6d0f6bcf JCPV |
446 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 447 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 448 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ | |
| 449 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 450 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 9490a7f1 KG |
451 | |
| 452 | /* | |
| 453 | * I2C2 EEPROM | |
| 454 | */ | |
| 32628c50 JCPV |
455 | #define CONFIG_ID_EEPROM |
| 456 | #ifdef CONFIG_ID_EEPROM | |
| 6d0f6bcf | 457 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 9490a7f1 | 458 | #endif |
| 6d0f6bcf JCPV |
459 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 460 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 461 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 9490a7f1 KG |
462 | |
| 463 | /* | |
| 464 | * General PCI | |
| 465 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 466 | */ | |
| 467 | ||
| 5af0fdd8 | 468 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
| 337f9fde KG |
469 | #ifdef CONFIG_PHYS_64BIT |
| 470 | #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 | |
| 471 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull | |
| 472 | #else | |
| 5af0fdd8 KG |
473 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| 474 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
| 337f9fde | 475 | #endif |
| 6d0f6bcf | 476 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
| 337f9fde KG |
477 | #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 |
| 478 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
| 479 | #ifdef CONFIG_PHYS_64BIT | |
| 480 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull | |
| 481 | #else | |
| 482 | #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 | |
| 483 | #endif | |
| 484 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
| 9490a7f1 KG |
485 | |
| 486 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 5af0fdd8 | 487 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 |
| 337f9fde KG |
488 | #ifdef CONFIG_PHYS_64BIT |
| 489 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 | |
| 490 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull | |
| 491 | #else | |
| 10795f42 | 492 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 |
| 5af0fdd8 | 493 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 |
| 337f9fde | 494 | #endif |
| 6d0f6bcf | 495 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ |
| aca5f018 | 496 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 |
| 337f9fde KG |
497 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 498 | #ifdef CONFIG_PHYS_64BIT | |
| 499 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull | |
| 500 | #else | |
| 6d0f6bcf | 501 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 |
| 337f9fde | 502 | #endif |
| 6d0f6bcf | 503 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 9490a7f1 KG |
504 | |
| 505 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 5af0fdd8 | 506 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 |
| 337f9fde KG |
507 | #ifdef CONFIG_PHYS_64BIT |
| 508 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 | |
| 509 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull | |
| 510 | #else | |
| 10795f42 | 511 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 |
| 5af0fdd8 | 512 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 |
| 337f9fde | 513 | #endif |
| 6d0f6bcf | 514 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ |
| aca5f018 | 515 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 |
| 337f9fde KG |
516 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 517 | #ifdef CONFIG_PHYS_64BIT | |
| 518 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull | |
| 519 | #else | |
| 6d0f6bcf | 520 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 |
| 337f9fde | 521 | #endif |
| 6d0f6bcf | 522 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 9490a7f1 KG |
523 | |
| 524 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ | |
| 5af0fdd8 | 525 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
| 337f9fde KG |
526 | #ifdef CONFIG_PHYS_64BIT |
| 527 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 528 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
| 529 | #else | |
| 10795f42 | 530 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
| 5af0fdd8 | 531 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 |
| 337f9fde | 532 | #endif |
| 6d0f6bcf | 533 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 534 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 |
| 337f9fde KG |
535 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 536 | #ifdef CONFIG_PHYS_64BIT | |
| 537 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull | |
| 538 | #else | |
| 6d0f6bcf | 539 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |
| 337f9fde | 540 | #endif |
| 6d0f6bcf | 541 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 9490a7f1 KG |
542 | |
| 543 | #if defined(CONFIG_PCI) | |
| 544 | ||
| 545 | #define CONFIG_NET_MULTI | |
| 546 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 547 | ||
| 548 | /*PCIE video card used*/ | |
| aca5f018 | 549 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT |
| 9490a7f1 KG |
550 | |
| 551 | /*PCI video card used*/ | |
| aca5f018 | 552 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
| 9490a7f1 KG |
553 | |
| 554 | /* video */ | |
| 555 | #define CONFIG_VIDEO | |
| 556 | ||
| 557 | #if defined(CONFIG_VIDEO) | |
| 558 | #define CONFIG_BIOSEMU | |
| 559 | #define CONFIG_CFB_CONSOLE | |
| 560 | #define CONFIG_VIDEO_SW_CURSOR | |
| 561 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 562 | #define CONFIG_ATI_RADEON_FB | |
| 563 | #define CONFIG_VIDEO_LOGO | |
| 564 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
| aca5f018 | 565 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT |
| 9490a7f1 KG |
566 | #endif |
| 567 | ||
| 568 | #undef CONFIG_EEPRO100 | |
| 569 | #undef CONFIG_TULIP | |
| 570 | #undef CONFIG_RTL8139 | |
| 571 | ||
| 9490a7f1 | 572 | #ifndef CONFIG_PCI_PNP |
| 5f91ef6a KG |
573 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
| 574 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
| 9490a7f1 KG |
575 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 576 | #endif | |
| 577 | ||
| 578 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 579 | ||
| 580 | #endif /* CONFIG_PCI */ | |
| 581 | ||
| 582 | /* SATA */ | |
| 583 | #define CONFIG_LIBATA | |
| 584 | #define CONFIG_FSL_SATA | |
| 585 | ||
| 6d0f6bcf | 586 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| 9490a7f1 | 587 | #define CONFIG_SATA1 |
| 6d0f6bcf JCPV |
588 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 589 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 9490a7f1 | 590 | #define CONFIG_SATA2 |
| 6d0f6bcf JCPV |
591 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| 592 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 9490a7f1 KG |
593 | |
| 594 | #ifdef CONFIG_FSL_SATA | |
| 595 | #define CONFIG_LBA48 | |
| 596 | #define CONFIG_CMD_SATA | |
| 597 | #define CONFIG_DOS_PARTITION | |
| 598 | #define CONFIG_CMD_EXT2 | |
| 599 | #endif | |
| 600 | ||
| 601 | #if defined(CONFIG_TSEC_ENET) | |
| 602 | ||
| 603 | #ifndef CONFIG_NET_MULTI | |
| 604 | #define CONFIG_NET_MULTI 1 | |
| 605 | #endif | |
| 606 | ||
| 607 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 608 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 609 | #define CONFIG_TSEC1 1 | |
| 610 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 611 | #define CONFIG_TSEC3 1 | |
| 612 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 613 | ||
| 2e26d837 JJ |
614 | #define CONFIG_FSL_SGMII_RISER 1 |
| 615 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
| 616 | ||
| 9490a7f1 KG |
617 | #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ |
| 618 | #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ | |
| 619 | ||
| 620 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 621 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 622 | ||
| 623 | #define TSEC1_PHYIDX 0 | |
| 624 | #define TSEC3_PHYIDX 0 | |
| 625 | ||
| 626 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 627 | ||
| 628 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 629 | ||
| 630 | #endif /* CONFIG_TSEC_ENET */ | |
| 631 | ||
| 632 | /* | |
| 633 | * Environment | |
| 634 | */ | |
| 9a1a0aed MH |
635 | |
| 636 | #if defined(CONFIG_SYS_RAMBOOT) | |
| 637 | #if defined(CONFIG_RAMBOOT_NAND) | |
| 638 | #define CONFIG_ENV_IS_IN_NAND 1 | |
| 639 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| 640 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
| e40ac487 MH |
641 | #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
| 642 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 643 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 644 | #define CONFIG_ENV_SIZE 0x2000 | |
| 9a1a0aed | 645 | #endif |
| 9490a7f1 | 646 | #else |
| 9a1a0aed MH |
647 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 648 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
| 649 | #define CONFIG_ENV_ADDR 0xfff80000 | |
| 650 | #else | |
| 651 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 652 | #endif | |
| 653 | #define CONFIG_ENV_SIZE 0x2000 | |
| 654 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 9490a7f1 | 655 | #endif |
| 9490a7f1 KG |
656 | |
| 657 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 658 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 9490a7f1 KG |
659 | |
| 660 | /* | |
| 661 | * Command line configuration. | |
| 662 | */ | |
| 663 | #include <config_cmd_default.h> | |
| 664 | ||
| 665 | #define CONFIG_CMD_IRQ | |
| 666 | #define CONFIG_CMD_PING | |
| 667 | #define CONFIG_CMD_I2C | |
| 668 | #define CONFIG_CMD_MII | |
| 669 | #define CONFIG_CMD_ELF | |
| 1c9aa76b KG |
670 | #define CONFIG_CMD_IRQ |
| 671 | #define CONFIG_CMD_SETEXPR | |
| 9490a7f1 KG |
672 | |
| 673 | #if defined(CONFIG_PCI) | |
| 674 | #define CONFIG_CMD_PCI | |
| 9490a7f1 KG |
675 | #define CONFIG_CMD_NET |
| 676 | #endif | |
| 677 | ||
| 678 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 679 | ||
| 80522dc8 AF |
680 | #define CONFIG_MMC 1 |
| 681 | ||
| 682 | #ifdef CONFIG_MMC | |
| 683 | #define CONFIG_FSL_ESDHC | |
| 684 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 685 | #define CONFIG_CMD_MMC | |
| 686 | #define CONFIG_GENERIC_MMC | |
| 687 | #define CONFIG_CMD_EXT2 | |
| 688 | #define CONFIG_CMD_FAT | |
| 689 | #define CONFIG_DOS_PARTITION | |
| 690 | #endif | |
| 691 | ||
| 9490a7f1 KG |
692 | /* |
| 693 | * Miscellaneous configurable options | |
| 694 | */ | |
| 6d0f6bcf | 695 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 07355700 | 696 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 6d0f6bcf JCPV |
697 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 698 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 9490a7f1 | 699 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 700 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 9490a7f1 | 701 | #else |
| 6d0f6bcf | 702 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 9490a7f1 | 703 | #endif |
| 07355700 MH |
704 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
| 705 | + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ | |
| 6d0f6bcf | 706 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 07355700 | 707 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 6d0f6bcf | 708 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 9490a7f1 KG |
709 | |
| 710 | /* | |
| 711 | * For booting Linux, the board info and command line data | |
| 89188a62 | 712 | * have to be in the first 16 MB of memory, since this is |
| 9490a7f1 KG |
713 | * the maximum mapped by the Linux kernel during initialization. |
| 714 | */ | |
| 07355700 | 715 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ |
| 9490a7f1 KG |
716 | |
| 717 | /* | |
| 718 | * Internal Definitions | |
| 719 | * | |
| 720 | * Boot Flags | |
| 721 | */ | |
| 722 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 723 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 724 | ||
| 725 | #if defined(CONFIG_CMD_KGDB) | |
| 726 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 727 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 728 | #endif | |
| 729 | ||
| 730 | /* | |
| 731 | * Environment Configuration | |
| 732 | */ | |
| 733 | ||
| 734 | /* The mac addresses for all ethernet interface */ | |
| 735 | #if defined(CONFIG_TSEC_ENET) | |
| 736 | #define CONFIG_HAS_ETH0 | |
| 737 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
| 738 | #define CONFIG_HAS_ETH1 | |
| 739 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
| 740 | #define CONFIG_HAS_ETH2 | |
| 741 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
| 742 | #define CONFIG_HAS_ETH3 | |
| 743 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
| 744 | #endif | |
| 745 | ||
| 746 | #define CONFIG_IPADDR 192.168.1.254 | |
| 747 | ||
| 748 | #define CONFIG_HOSTNAME unknown | |
| 749 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 750 | #define CONFIG_BOOTFILE uImage | |
| 07355700 | 751 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 9490a7f1 KG |
752 | |
| 753 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 754 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 755 | #define CONFIG_NETMASK 255.255.255.0 | |
| 756 | ||
| 757 | /* default location for tftp and bootm */ | |
| 758 | #define CONFIG_LOADADDR 1000000 | |
| 759 | ||
| 760 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 761 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 762 | ||
| 763 | #define CONFIG_BAUDRATE 115200 | |
| 764 | ||
| 765 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 766 | "netdev=eth0\0" \ | |
| 767 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 768 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 769 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 770 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 771 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 772 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 773 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 774 | "consoledev=ttyS0\0" \ | |
| 775 | "ramdiskaddr=2000000\0" \ | |
| 776 | "ramdiskfile=8536ds/ramdisk.uboot\0" \ | |
| 777 | "fdtaddr=c00000\0" \ | |
| 778 | "fdtfile=8536ds/mpc8536ds.dtb\0" \ | |
| 4bc6eb79 VM |
779 | "bdev=sda3\0" \ |
| 780 | "usb_phy_type=ulpi\0" | |
| 9490a7f1 KG |
781 | |
| 782 | #define CONFIG_HDBOOT \ | |
| 783 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 784 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 785 | "tftp $loadaddr $bootfile;" \ | |
| 786 | "tftp $fdtaddr $fdtfile;" \ | |
| 787 | "bootm $loadaddr - $fdtaddr" | |
| 788 | ||
| 789 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 790 | "setenv bootargs root=/dev/nfs rw " \ | |
| 791 | "nfsroot=$serverip:$rootpath " \ | |
| 792 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 793 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 794 | "tftp $loadaddr $bootfile;" \ | |
| 795 | "tftp $fdtaddr $fdtfile;" \ | |
| 796 | "bootm $loadaddr - $fdtaddr" | |
| 797 | ||
| 798 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 799 | "setenv bootargs root=/dev/ram rw " \ | |
| 800 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 801 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 802 | "tftp $loadaddr $bootfile;" \ | |
| 803 | "tftp $fdtaddr $fdtfile;" \ | |
| 804 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 805 | ||
| 806 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 807 | ||
| 808 | #endif /* __CONFIG_H */ |