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42d1f039 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
42d1f039 WD |
7 | */ |
8 | ||
0ac6f8b7 WD |
9 | /* |
10 | * mpc8540ads board configuration file | |
11 | * | |
12 | * Please refer to doc/README.mpc85xx for more info. | |
13 | * | |
14 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 15 | * search for CONFIG_SERVERIP, etc in this file. |
42d1f039 WD |
16 | */ |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
2ae18241 WD |
21 | /* |
22 | * default CCARBAR is at 0xff700000 | |
23 | * assume U-Boot is less than 0.5MB | |
24 | */ | |
25 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
26 | ||
288693ab JL |
27 | #ifndef CONFIG_HAS_FEC |
28 | #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ | |
29 | #endif | |
30 | ||
842033e6 | 31 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0151cbac | 32 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 33 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
42d1f039 | 34 | #define CONFIG_ENV_OVERWRITE |
42d1f039 | 35 | |
0ac6f8b7 WD |
36 | /* |
37 | * sysclk for MPC85xx | |
38 | * | |
39 | * Two valid values are: | |
40 | * 33000000 | |
41 | * 66000000 | |
42 | * | |
43 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
44 | * is likely the desired value here, so that is now the default. |
45 | * The board, however, can run at 66MHz. In any event, this value | |
46 | * must match the settings of some switches. Details can be found | |
47 | * in the README.mpc85xxads. | |
34c3c0e0 MM |
48 | * |
49 | * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to | |
50 | * 33MHz to accommodate, based on a PCI pin. | |
51 | * Note that PCI-X won't work at 33MHz. | |
0ac6f8b7 WD |
52 | */ |
53 | ||
9aea9530 | 54 | #ifndef CONFIG_SYS_CLK_FREQ |
34c3c0e0 | 55 | #define CONFIG_SYS_CLK_FREQ 33000000 |
42d1f039 WD |
56 | #endif |
57 | ||
0ac6f8b7 WD |
58 | /* |
59 | * These can be toggled for performance analysis, otherwise use default. | |
60 | */ | |
61 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
62 | #define CONFIG_BTB /* toggle branch predition */ | |
42d1f039 | 63 | |
6d0f6bcf JCPV |
64 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
65 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
42d1f039 | 66 | |
e46fedfe TT |
67 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
68 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
42d1f039 | 69 | |
9617c8d4 | 70 | /* DDR Setup */ |
9617c8d4 KG |
71 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
72 | #define CONFIG_DDR_SPD | |
73 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
74 | ||
75 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9aea9530 | 76 | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
78 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9aea9530 | 79 | |
9617c8d4 KG |
80 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
81 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
82 | ||
83 | /* I2C addresses of SPD EEPROMs */ | |
84 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
85 | ||
86 | /* These are used when DDR doesn't use SPD. */ | |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ |
88 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
89 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 | |
90 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 | |
91 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
92 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
93 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
94 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
42d1f039 | 95 | |
0ac6f8b7 WD |
96 | /* |
97 | * SDRAM on the Local Bus | |
98 | */ | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
100 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
42d1f039 | 101 | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
103 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
106 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
107 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
108 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
109 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
110 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
0ac6f8b7 | 111 | |
14d0a02a | 112 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
42d1f039 | 113 | |
6d0f6bcf JCPV |
114 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
115 | #define CONFIG_SYS_RAMBOOT | |
42d1f039 | 116 | #else |
6d0f6bcf | 117 | #undef CONFIG_SYS_RAMBOOT |
42d1f039 WD |
118 | #endif |
119 | ||
00b1883a | 120 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_FLASH_CFI |
122 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
42d1f039 | 123 | |
0ac6f8b7 WD |
124 | #undef CONFIG_CLOCKS_IN_MHZ |
125 | ||
0ac6f8b7 WD |
126 | /* |
127 | * Local Bus Definitions | |
128 | */ | |
129 | ||
130 | /* | |
131 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 132 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
0ac6f8b7 WD |
133 | * |
134 | * For BR2, need: | |
135 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
136 | * port-size = 32-bits = BR2[19:20] = 11 | |
137 | * no parity checking = BR2[21:22] = 00 | |
138 | * SDRAM for MSEL = BR2[24:26] = 011 | |
139 | * Valid = BR[31] = 1 | |
140 | * | |
141 | * 0 4 8 12 16 20 24 28 | |
142 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
143 | * | |
6d0f6bcf | 144 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
0ac6f8b7 WD |
145 | * FIXME: the top 17 bits of BR2. |
146 | */ | |
147 | ||
6d0f6bcf | 148 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
0ac6f8b7 WD |
149 | |
150 | /* | |
6d0f6bcf | 151 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
0ac6f8b7 WD |
152 | * |
153 | * For OR2, need: | |
154 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
155 | * XAM, OR2[17:18] = 11 | |
156 | * 9 columns OR2[19-21] = 010 | |
157 | * 13 rows OR2[23-25] = 100 | |
158 | * EAD set for extra time OR[31] = 1 | |
159 | * | |
160 | * 0 4 8 12 16 20 24 28 | |
161 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
162 | */ | |
163 | ||
6d0f6bcf | 164 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
0ac6f8b7 | 165 | |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
167 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
168 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
169 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
0ac6f8b7 | 170 | |
b0fe93ed KG |
171 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ |
172 | | LSDMR_RFCR5 \ | |
173 | | LSDMR_PRETOACT3 \ | |
174 | | LSDMR_ACTTORW3 \ | |
175 | | LSDMR_BL8 \ | |
176 | | LSDMR_WRC2 \ | |
177 | | LSDMR_CL3 \ | |
178 | | LSDMR_RFEN \ | |
0ac6f8b7 WD |
179 | ) |
180 | ||
181 | /* | |
182 | * SDRAM Controller configuration sequence. | |
183 | */ | |
b0fe93ed KG |
184 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
185 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
186 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
187 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
188 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
0ac6f8b7 | 189 | |
9aea9530 WD |
190 | /* |
191 | * 32KB, 8-bit wide for ADS config reg | |
192 | */ | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 |
194 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 | |
195 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) | |
42d1f039 | 196 | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
198 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 199 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
42d1f039 | 200 | |
25ddd1fb | 201 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 202 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
42d1f039 | 203 | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
205 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
42d1f039 WD |
206 | |
207 | /* Serial Port */ | |
208 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_NS16550_SERIAL |
210 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
211 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
42d1f039 | 212 | |
6d0f6bcf | 213 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
42d1f039 WD |
214 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
215 | ||
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
217 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
42d1f039 | 218 | |
20476726 JL |
219 | /* |
220 | * I2C | |
221 | */ | |
00f792e0 HS |
222 | #define CONFIG_SYS_I2C |
223 | #define CONFIG_SYS_I2C_FSL | |
224 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
225 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
226 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
227 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
0ac6f8b7 WD |
228 | |
229 | /* RapidIO MMU */ | |
5af0fdd8 | 230 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
10795f42 | 231 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ |
5af0fdd8 | 232 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 |
6d0f6bcf | 233 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
0ac6f8b7 WD |
234 | |
235 | /* | |
236 | * General PCI | |
362dd830 | 237 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 | 238 | */ |
5af0fdd8 | 239 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 240 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 241 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 242 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 243 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 244 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
245 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
246 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
42d1f039 | 247 | |
42d1f039 | 248 | #if defined(CONFIG_PCI) |
42d1f039 | 249 | #undef CONFIG_EEPRO100 |
0ac6f8b7 WD |
250 | #undef CONFIG_TULIP |
251 | ||
252 | #if !defined(CONFIG_PCI_PNP) | |
253 | #define PCI_ENET0_IOADDR 0xe0000000 | |
254 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 255 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
42d1f039 | 256 | #endif |
0ac6f8b7 WD |
257 | |
258 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 259 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
0ac6f8b7 WD |
260 | |
261 | #endif /* CONFIG_PCI */ | |
262 | ||
0ac6f8b7 WD |
263 | #if defined(CONFIG_TSEC_ENET) |
264 | ||
0ac6f8b7 | 265 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
266 | #define CONFIG_TSEC1 1 |
267 | #define CONFIG_TSEC1_NAME "TSEC0" | |
268 | #define CONFIG_TSEC2 1 | |
269 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
270 | #define TSEC1_PHY_ADDR 0 |
271 | #define TSEC2_PHY_ADDR 1 | |
0ac6f8b7 WD |
272 | #define TSEC1_PHYIDX 0 |
273 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
274 | #define TSEC1_FLAGS TSEC_GIGABIT |
275 | #define TSEC2_FLAGS TSEC_GIGABIT | |
9aea9530 | 276 | |
288693ab | 277 | #if CONFIG_HAS_FEC |
9aea9530 | 278 | #define CONFIG_MPC85XX_FEC 1 |
d9b94f28 | 279 | #define CONFIG_MPC85XX_FEC_NAME "FEC" |
9aea9530 | 280 | #define FEC_PHY_ADDR 3 |
0ac6f8b7 | 281 | #define FEC_PHYIDX 0 |
3a79013e | 282 | #define FEC_FLAGS 0 |
288693ab | 283 | #endif |
9aea9530 | 284 | |
d9b94f28 JL |
285 | /* Options are: TSEC[0-1], FEC */ |
286 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 WD |
287 | |
288 | #endif /* CONFIG_TSEC_ENET */ | |
289 | ||
0ac6f8b7 WD |
290 | /* |
291 | * Environment | |
292 | */ | |
6d0f6bcf | 293 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 294 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 295 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
296 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
297 | #define CONFIG_ENV_SIZE 0x2000 | |
42d1f039 | 298 | #else |
6d0f6bcf | 299 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 300 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 301 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 302 | #define CONFIG_ENV_SIZE 0x2000 |
42d1f039 WD |
303 | #endif |
304 | ||
0ac6f8b7 | 305 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 306 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
42d1f039 | 307 | |
659e2f67 JL |
308 | /* |
309 | * BOOTP options | |
310 | */ | |
311 | #define CONFIG_BOOTP_BOOTFILESIZE | |
312 | #define CONFIG_BOOTP_BOOTPATH | |
313 | #define CONFIG_BOOTP_GATEWAY | |
314 | #define CONFIG_BOOTP_HOSTNAME | |
315 | ||
2835e518 JL |
316 | /* |
317 | * Command line configuration. | |
318 | */ | |
1c9aa76b | 319 | #define CONFIG_CMD_IRQ |
2835e518 JL |
320 | |
321 | #if defined(CONFIG_PCI) | |
322 | #define CONFIG_CMD_PCI | |
323 | #endif | |
324 | ||
0ac6f8b7 | 325 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
326 | |
327 | /* | |
328 | * Miscellaneous configurable options | |
329 | */ | |
6d0f6bcf | 330 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
331 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
332 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 333 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
0ac6f8b7 | 334 | |
2835e518 | 335 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 336 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 337 | #else |
6d0f6bcf | 338 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 339 | #endif |
0ac6f8b7 | 340 | |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
342 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
343 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
42d1f039 WD |
344 | |
345 | /* | |
346 | * For booting Linux, the board info and command line data | |
a832ac41 | 347 | * have to be in the first 64 MB of memory, since this is |
42d1f039 WD |
348 | * the maximum mapped by the Linux kernel during initialization. |
349 | */ | |
a832ac41 KG |
350 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
351 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
42d1f039 | 352 | |
2835e518 | 353 | #if defined(CONFIG_CMD_KGDB) |
42d1f039 | 354 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
42d1f039 WD |
355 | #endif |
356 | ||
9aea9530 WD |
357 | /* |
358 | * Environment Configuration | |
359 | */ | |
0ac6f8b7 WD |
360 | |
361 | /* The mac addresses for all ethernet interface */ | |
42d1f039 | 362 | #if defined(CONFIG_TSEC_ENET) |
10327dc5 | 363 | #define CONFIG_HAS_ETH0 |
e2ffd59b | 364 | #define CONFIG_HAS_ETH1 |
e2ffd59b | 365 | #define CONFIG_HAS_ETH2 |
42d1f039 WD |
366 | #endif |
367 | ||
0ac6f8b7 WD |
368 | #define CONFIG_IPADDR 192.168.1.253 |
369 | ||
370 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 371 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 372 | #define CONFIG_BOOTFILE "your.uImage" |
0ac6f8b7 WD |
373 | |
374 | #define CONFIG_SERVERIP 192.168.1.1 | |
375 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
376 | #define CONFIG_NETMASK 255.255.255.0 | |
377 | ||
378 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
379 | ||
0ac6f8b7 WD |
380 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
381 | ||
382 | #define CONFIG_BAUDRATE 115200 | |
383 | ||
9aea9530 | 384 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
0ac6f8b7 WD |
385 | "netdev=eth0\0" \ |
386 | "consoledev=ttyS0\0" \ | |
d3ec0d94 | 387 | "ramdiskaddr=1000000\0" \ |
8272dc2f AF |
388 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
389 | "fdtaddr=400000\0" \ | |
390 | "fdtfile=your.fdt.dtb\0" | |
0ac6f8b7 | 391 | |
9aea9530 | 392 | #define CONFIG_NFSBOOTCOMMAND \ |
0ac6f8b7 WD |
393 | "setenv bootargs root=/dev/nfs rw " \ |
394 | "nfsroot=$serverip:$rootpath " \ | |
395 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
396 | "console=$consoledev,$baudrate $othbootargs;" \ | |
397 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f AF |
398 | "tftp $fdtaddr $fdtfile;" \ |
399 | "bootm $loadaddr - $fdtaddr" | |
0ac6f8b7 WD |
400 | |
401 | #define CONFIG_RAMBOOTCOMMAND \ | |
402 | "setenv bootargs root=/dev/ram rw " \ | |
403 | "console=$consoledev,$baudrate $othbootargs;" \ | |
404 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
405 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f | 406 | "tftp $fdtaddr $fdtfile;" \ |
d3ec0d94 | 407 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
0ac6f8b7 WD |
408 | |
409 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
410 | |
411 | #endif /* __CONFIG_H */ |