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42d1f039 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
42d1f039 WD |
7 | */ |
8 | ||
0ac6f8b7 WD |
9 | /* |
10 | * mpc8540ads board configuration file | |
11 | * | |
12 | * Please refer to doc/README.mpc85xx for more info. | |
13 | * | |
14 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 15 | * search for CONFIG_SERVERIP, etc in this file. |
42d1f039 WD |
16 | */ |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
9ae14ca2 YS |
21 | #define CONFIG_DISPLAY_BOARDINFO |
22 | ||
42d1f039 | 23 | /* High Level Configuration Options */ |
0ac6f8b7 WD |
24 | #define CONFIG_BOOKE 1 /* BOOKE */ |
25 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
0ac6f8b7 WD |
26 | #define CONFIG_MPC8540 1 /* MPC8540 specific */ |
27 | #define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */ | |
28 | ||
2ae18241 WD |
29 | /* |
30 | * default CCARBAR is at 0xff700000 | |
31 | * assume U-Boot is less than 0.5MB | |
32 | */ | |
33 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
34 | ||
288693ab JL |
35 | #ifndef CONFIG_HAS_FEC |
36 | #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ | |
37 | #endif | |
38 | ||
0ac6f8b7 | 39 | #define CONFIG_PCI |
842033e6 | 40 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0151cbac | 41 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 42 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
42d1f039 | 43 | #define CONFIG_ENV_OVERWRITE |
7232a272 | 44 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
42d1f039 | 45 | |
0ac6f8b7 WD |
46 | /* |
47 | * sysclk for MPC85xx | |
48 | * | |
49 | * Two valid values are: | |
50 | * 33000000 | |
51 | * 66000000 | |
52 | * | |
53 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
54 | * is likely the desired value here, so that is now the default. |
55 | * The board, however, can run at 66MHz. In any event, this value | |
56 | * must match the settings of some switches. Details can be found | |
57 | * in the README.mpc85xxads. | |
34c3c0e0 MM |
58 | * |
59 | * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to | |
60 | * 33MHz to accommodate, based on a PCI pin. | |
61 | * Note that PCI-X won't work at 33MHz. | |
0ac6f8b7 WD |
62 | */ |
63 | ||
9aea9530 | 64 | #ifndef CONFIG_SYS_CLK_FREQ |
34c3c0e0 | 65 | #define CONFIG_SYS_CLK_FREQ 33000000 |
42d1f039 WD |
66 | #endif |
67 | ||
9aea9530 | 68 | |
0ac6f8b7 WD |
69 | /* |
70 | * These can be toggled for performance analysis, otherwise use default. | |
71 | */ | |
72 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
73 | #define CONFIG_BTB /* toggle branch predition */ | |
42d1f039 | 74 | |
6d0f6bcf JCPV |
75 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
76 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
42d1f039 | 77 | |
e46fedfe TT |
78 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
79 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
42d1f039 | 80 | |
9617c8d4 | 81 | /* DDR Setup */ |
5614e71b | 82 | #define CONFIG_SYS_FSL_DDR1 |
9617c8d4 KG |
83 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
84 | #define CONFIG_DDR_SPD | |
85 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
86 | ||
87 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9aea9530 | 88 | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
90 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9aea9530 | 91 | |
9617c8d4 KG |
92 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
93 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
94 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
95 | ||
96 | /* I2C addresses of SPD EEPROMs */ | |
97 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
98 | ||
99 | /* These are used when DDR doesn't use SPD. */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ |
101 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
102 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 | |
103 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 | |
104 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
105 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
106 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
107 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
42d1f039 | 108 | |
0ac6f8b7 WD |
109 | /* |
110 | * SDRAM on the Local Bus | |
111 | */ | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
113 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
42d1f039 | 114 | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
116 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
119 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
120 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
121 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
122 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
123 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
0ac6f8b7 | 124 | |
14d0a02a | 125 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
42d1f039 | 126 | |
6d0f6bcf JCPV |
127 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
128 | #define CONFIG_SYS_RAMBOOT | |
42d1f039 | 129 | #else |
6d0f6bcf | 130 | #undef CONFIG_SYS_RAMBOOT |
42d1f039 WD |
131 | #endif |
132 | ||
00b1883a | 133 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_FLASH_CFI |
135 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
42d1f039 | 136 | |
0ac6f8b7 WD |
137 | #undef CONFIG_CLOCKS_IN_MHZ |
138 | ||
42d1f039 | 139 | |
0ac6f8b7 WD |
140 | /* |
141 | * Local Bus Definitions | |
142 | */ | |
143 | ||
144 | /* | |
145 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 146 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
0ac6f8b7 WD |
147 | * |
148 | * For BR2, need: | |
149 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
150 | * port-size = 32-bits = BR2[19:20] = 11 | |
151 | * no parity checking = BR2[21:22] = 00 | |
152 | * SDRAM for MSEL = BR2[24:26] = 011 | |
153 | * Valid = BR[31] = 1 | |
154 | * | |
155 | * 0 4 8 12 16 20 24 28 | |
156 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
157 | * | |
6d0f6bcf | 158 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
0ac6f8b7 WD |
159 | * FIXME: the top 17 bits of BR2. |
160 | */ | |
161 | ||
6d0f6bcf | 162 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
0ac6f8b7 WD |
163 | |
164 | /* | |
6d0f6bcf | 165 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
0ac6f8b7 WD |
166 | * |
167 | * For OR2, need: | |
168 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
169 | * XAM, OR2[17:18] = 11 | |
170 | * 9 columns OR2[19-21] = 010 | |
171 | * 13 rows OR2[23-25] = 100 | |
172 | * EAD set for extra time OR[31] = 1 | |
173 | * | |
174 | * 0 4 8 12 16 20 24 28 | |
175 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
176 | */ | |
177 | ||
6d0f6bcf | 178 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
0ac6f8b7 | 179 | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
181 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
182 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
183 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
0ac6f8b7 | 184 | |
b0fe93ed KG |
185 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ |
186 | | LSDMR_RFCR5 \ | |
187 | | LSDMR_PRETOACT3 \ | |
188 | | LSDMR_ACTTORW3 \ | |
189 | | LSDMR_BL8 \ | |
190 | | LSDMR_WRC2 \ | |
191 | | LSDMR_CL3 \ | |
192 | | LSDMR_RFEN \ | |
0ac6f8b7 WD |
193 | ) |
194 | ||
195 | /* | |
196 | * SDRAM Controller configuration sequence. | |
197 | */ | |
b0fe93ed KG |
198 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
199 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
200 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
201 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
202 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
0ac6f8b7 | 203 | |
42d1f039 | 204 | |
9aea9530 WD |
205 | /* |
206 | * 32KB, 8-bit wide for ADS config reg | |
207 | */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 |
209 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 | |
210 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) | |
42d1f039 | 211 | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
213 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 214 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
42d1f039 | 215 | |
25ddd1fb | 216 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 217 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
42d1f039 | 218 | |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
220 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
42d1f039 WD |
221 | |
222 | /* Serial Port */ | |
223 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_NS16550_SERIAL |
225 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
226 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
42d1f039 | 227 | |
6d0f6bcf | 228 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
42d1f039 WD |
229 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
230 | ||
6d0f6bcf JCPV |
231 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
232 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
42d1f039 WD |
233 | |
234 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_HUSH_PARSER |
236 | #ifdef CONFIG_SYS_HUSH_PARSER | |
42d1f039 WD |
237 | #endif |
238 | ||
0e16387d | 239 | /* pass open firmware flat tree */ |
0fd5ec66 KG |
240 | #define CONFIG_OF_LIBFDT 1 |
241 | #define CONFIG_OF_BOARD_SETUP 1 | |
242 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0e16387d | 243 | |
20476726 JL |
244 | /* |
245 | * I2C | |
246 | */ | |
00f792e0 HS |
247 | #define CONFIG_SYS_I2C |
248 | #define CONFIG_SYS_I2C_FSL | |
249 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
250 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
251 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
252 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
0ac6f8b7 WD |
253 | |
254 | /* RapidIO MMU */ | |
5af0fdd8 | 255 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
10795f42 | 256 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ |
5af0fdd8 | 257 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 |
6d0f6bcf | 258 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
0ac6f8b7 WD |
259 | |
260 | /* | |
261 | * General PCI | |
362dd830 | 262 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 | 263 | */ |
5af0fdd8 | 264 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 265 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 266 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 267 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 268 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 269 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
271 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
42d1f039 | 272 | |
42d1f039 | 273 | #if defined(CONFIG_PCI) |
0ac6f8b7 | 274 | |
53677ef1 | 275 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
0ac6f8b7 | 276 | |
42d1f039 | 277 | #undef CONFIG_EEPRO100 |
0ac6f8b7 WD |
278 | #undef CONFIG_TULIP |
279 | ||
280 | #if !defined(CONFIG_PCI_PNP) | |
281 | #define PCI_ENET0_IOADDR 0xe0000000 | |
282 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 283 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
42d1f039 | 284 | #endif |
0ac6f8b7 WD |
285 | |
286 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 287 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
0ac6f8b7 WD |
288 | |
289 | #endif /* CONFIG_PCI */ | |
290 | ||
291 | ||
292 | #if defined(CONFIG_TSEC_ENET) | |
293 | ||
0ac6f8b7 | 294 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
295 | #define CONFIG_TSEC1 1 |
296 | #define CONFIG_TSEC1_NAME "TSEC0" | |
297 | #define CONFIG_TSEC2 1 | |
298 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
299 | #define TSEC1_PHY_ADDR 0 |
300 | #define TSEC2_PHY_ADDR 1 | |
0ac6f8b7 WD |
301 | #define TSEC1_PHYIDX 0 |
302 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
303 | #define TSEC1_FLAGS TSEC_GIGABIT |
304 | #define TSEC2_FLAGS TSEC_GIGABIT | |
9aea9530 | 305 | |
288693ab JL |
306 | |
307 | #if CONFIG_HAS_FEC | |
9aea9530 | 308 | #define CONFIG_MPC85XX_FEC 1 |
d9b94f28 | 309 | #define CONFIG_MPC85XX_FEC_NAME "FEC" |
9aea9530 | 310 | #define FEC_PHY_ADDR 3 |
0ac6f8b7 | 311 | #define FEC_PHYIDX 0 |
3a79013e | 312 | #define FEC_FLAGS 0 |
288693ab | 313 | #endif |
9aea9530 | 314 | |
d9b94f28 JL |
315 | /* Options are: TSEC[0-1], FEC */ |
316 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 WD |
317 | |
318 | #endif /* CONFIG_TSEC_ENET */ | |
319 | ||
320 | ||
321 | /* | |
322 | * Environment | |
323 | */ | |
6d0f6bcf | 324 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 325 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 326 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
327 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
328 | #define CONFIG_ENV_SIZE 0x2000 | |
42d1f039 | 329 | #else |
6d0f6bcf | 330 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 331 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 332 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 333 | #define CONFIG_ENV_SIZE 0x2000 |
42d1f039 WD |
334 | #endif |
335 | ||
0ac6f8b7 | 336 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 337 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
42d1f039 | 338 | |
2835e518 | 339 | |
659e2f67 JL |
340 | /* |
341 | * BOOTP options | |
342 | */ | |
343 | #define CONFIG_BOOTP_BOOTFILESIZE | |
344 | #define CONFIG_BOOTP_BOOTPATH | |
345 | #define CONFIG_BOOTP_GATEWAY | |
346 | #define CONFIG_BOOTP_HOSTNAME | |
347 | ||
348 | ||
2835e518 JL |
349 | /* |
350 | * Command line configuration. | |
351 | */ | |
2835e518 JL |
352 | #define CONFIG_CMD_PING |
353 | #define CONFIG_CMD_I2C | |
1c9aa76b | 354 | #define CONFIG_CMD_IRQ |
2835e518 JL |
355 | |
356 | #if defined(CONFIG_PCI) | |
357 | #define CONFIG_CMD_PCI | |
358 | #endif | |
359 | ||
0ac6f8b7 | 360 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
361 | |
362 | /* | |
363 | * Miscellaneous configurable options | |
364 | */ | |
6d0f6bcf | 365 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
366 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
367 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 368 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
0ac6f8b7 | 369 | |
2835e518 | 370 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 371 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 372 | #else |
6d0f6bcf | 373 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 374 | #endif |
0ac6f8b7 | 375 | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
377 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
378 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
42d1f039 WD |
379 | |
380 | /* | |
381 | * For booting Linux, the board info and command line data | |
a832ac41 | 382 | * have to be in the first 64 MB of memory, since this is |
42d1f039 WD |
383 | * the maximum mapped by the Linux kernel during initialization. |
384 | */ | |
a832ac41 KG |
385 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
386 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
42d1f039 | 387 | |
2835e518 | 388 | #if defined(CONFIG_CMD_KGDB) |
42d1f039 | 389 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
42d1f039 WD |
390 | #endif |
391 | ||
9aea9530 WD |
392 | |
393 | /* | |
394 | * Environment Configuration | |
395 | */ | |
0ac6f8b7 WD |
396 | |
397 | /* The mac addresses for all ethernet interface */ | |
42d1f039 | 398 | #if defined(CONFIG_TSEC_ENET) |
10327dc5 | 399 | #define CONFIG_HAS_ETH0 |
e2ffd59b | 400 | #define CONFIG_HAS_ETH1 |
e2ffd59b | 401 | #define CONFIG_HAS_ETH2 |
42d1f039 WD |
402 | #endif |
403 | ||
0ac6f8b7 WD |
404 | #define CONFIG_IPADDR 192.168.1.253 |
405 | ||
406 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 407 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 408 | #define CONFIG_BOOTFILE "your.uImage" |
0ac6f8b7 WD |
409 | |
410 | #define CONFIG_SERVERIP 192.168.1.1 | |
411 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
412 | #define CONFIG_NETMASK 255.255.255.0 | |
413 | ||
414 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
415 | ||
416 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
417 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
418 | ||
419 | #define CONFIG_BAUDRATE 115200 | |
420 | ||
9aea9530 | 421 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
0ac6f8b7 WD |
422 | "netdev=eth0\0" \ |
423 | "consoledev=ttyS0\0" \ | |
d3ec0d94 | 424 | "ramdiskaddr=1000000\0" \ |
8272dc2f AF |
425 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
426 | "fdtaddr=400000\0" \ | |
427 | "fdtfile=your.fdt.dtb\0" | |
0ac6f8b7 | 428 | |
9aea9530 | 429 | #define CONFIG_NFSBOOTCOMMAND \ |
0ac6f8b7 WD |
430 | "setenv bootargs root=/dev/nfs rw " \ |
431 | "nfsroot=$serverip:$rootpath " \ | |
432 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
433 | "console=$consoledev,$baudrate $othbootargs;" \ | |
434 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f AF |
435 | "tftp $fdtaddr $fdtfile;" \ |
436 | "bootm $loadaddr - $fdtaddr" | |
0ac6f8b7 WD |
437 | |
438 | #define CONFIG_RAMBOOTCOMMAND \ | |
439 | "setenv bootargs root=/dev/ram rw " \ | |
440 | "console=$consoledev,$baudrate $othbootargs;" \ | |
441 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
442 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f | 443 | "tftp $fdtaddr $fdtfile;" \ |
d3ec0d94 | 444 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
0ac6f8b7 WD |
445 | |
446 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
447 | |
448 | #endif /* __CONFIG_H */ |