[people/ms/u-boot.git] / include / configs / MPC8540ADS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8540ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC8540		1	/* MPC8540 specific */
#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */
#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#ifndef CONFIG_HAS_FEC
#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
#endif

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 *
 * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
 * 33MHz to accommodate, based on a PCI pin.
 * Note that PCI-X won't work at 33MHz.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)


/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT


#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC	1
#define CONFIG_MPC85XX_FEC_NAME		"FEC"
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0
#define FEC_FLAGS		0
#endif

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */


/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_IS_IN_FLASH	1
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CONFIG_ENV_SIZE		0x2000
#else
  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#if defined(CONFIG_CMD_KGDB)
    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif


/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=1000000\0"						\
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	7	*/
42d1f039 WD	8
0ac6f8b7 WD	9	/*
	10	* mpc8540ads board configuration file
	11	*
	12	* Please refer to doc/README.mpc85xx for more info.
	13	*
	14	* Make sure you change the MAC address and other network params first,
92ac5208	15	* search for CONFIG_SERVERIP, etc in this file.
42d1f039 WD	16	*/
	17
	18	#ifndef __CONFIG_H
	19	#define __CONFIG_H
	20
9ae14ca2 YS	21	#define CONFIG_SYS_GENERIC_BOARD
	22	#define CONFIG_DISPLAY_BOARDINFO
	23
42d1f039	24	/* High Level Configuration Options */
0ac6f8b7 WD	25	#define CONFIG_BOOKE 1 /* BOOKE */
0ac6f8b7 WD	26	#define CONFIG_E500 1 /* BOOKE e500 family */
0ac6f8b7 WD	27	#define CONFIG_MPC8540 1 /* MPC8540 specific */
	28	#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
	29
2ae18241 WD	30	/*
	31	* default CCARBAR is at 0xff700000
	32	* assume U-Boot is less than 0.5MB
	33	*/
	34	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	35
288693ab JL	36	#ifndef CONFIG_HAS_FEC
	37	#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
	38	#endif
	39
0ac6f8b7	40	#define CONFIG_PCI
842033e6	41	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	42	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	43	#define CONFIG_TSEC_ENET /* tsec ethernet support */
42d1f039	44	#define CONFIG_ENV_OVERWRITE
7232a272	45	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
42d1f039	46
0ac6f8b7 WD	47	/*
	48	* sysclk for MPC85xx
	49	*
	50	* Two valid values are:
	51	* 33000000
	52	* 66000000
	53	*
	54	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	55	* is likely the desired value here, so that is now the default.
	56	* The board, however, can run at 66MHz. In any event, this value
	57	* must match the settings of some switches. Details can be found
	58	* in the README.mpc85xxads.
34c3c0e0 MM	59	*
	60	* XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
	61	* 33MHz to accommodate, based on a PCI pin.
	62	* Note that PCI-X won't work at 33MHz.
0ac6f8b7 WD	63	*/
0ac6f8b7 WD	64
9aea9530	65	#ifndef CONFIG_SYS_CLK_FREQ
34c3c0e0	66	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	67	#endif
42d1f039 WD	68
9aea9530	69
0ac6f8b7 WD	70	/*
	71	* These can be toggled for performance analysis, otherwise use default.
	72	*/
	73	#define CONFIG_L2_CACHE /* toggle L2 cache */
	74	#define CONFIG_BTB /* toggle branch predition */
42d1f039	75
6d0f6bcf JCPV	76	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	77	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	78
e46fedfe TT	79	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	80	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
42d1f039	81
9617c8d4	82	/* DDR Setup */
5614e71b	83	#define CONFIG_SYS_FSL_DDR1
9617c8d4 KG	84	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	85	#define CONFIG_DDR_SPD
	86	#undef CONFIG_FSL_DDR_INTERACTIVE
	87
	88	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	89
6d0f6bcf JCPV	90	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	91	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	92
9617c8d4 KG	93	#define CONFIG_NUM_DDR_CONTROLLERS 1
	94	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	95	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	96
	97	/* I2C addresses of SPD EEPROMs */
	98	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	99
	100	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	101	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	102	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	103	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	104	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	105	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	106	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	107	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	108	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	109
0ac6f8b7 WD	110	/*
	111	* SDRAM on the Local Bus
	112	*/
6d0f6bcf JCPV	113	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	114	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	117	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	118
6d0f6bcf JCPV	119	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	120	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	121	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	122	#undef CONFIG_SYS_FLASH_CHECKSUM
	123	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	124	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	125
14d0a02a	126	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	127
6d0f6bcf JCPV	128	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	129	#define CONFIG_SYS_RAMBOOT
42d1f039	130	#else
6d0f6bcf	131	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	132	#endif
42d1f039 WD	133
00b1883a	134	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	135	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	136	#define CONFIG_SYS_FLASH_EMPTY_INFO
42d1f039	137
0ac6f8b7 WD	138	#undef CONFIG_CLOCKS_IN_MHZ
0ac6f8b7 WD	139
42d1f039	140
0ac6f8b7 WD	141	/*
	142	* Local Bus Definitions
	143	*/
	144
	145	/*
	146	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	147	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	148	*
	149	* For BR2, need:
	150	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	151	* port-size = 32-bits = BR2[19:20] = 11
	152	* no parity checking = BR2[21:22] = 00
	153	* SDRAM for MSEL = BR2[24:26] = 011
	154	* Valid = BR[31] = 1
	155	*
	156	* 0 4 8 12 16 20 24 28
	157	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	158	*
6d0f6bcf	159	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	160	* FIXME: the top 17 bits of BR2.
	161	*/
	162
6d0f6bcf	163	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	164
0ac6f8b7 WD	165	/*
6d0f6bcf	166	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	167	*
	168	* For OR2, need:
	169	* 64MB mask for AM, OR2[0:7] = 1111 1100
	170	* XAM, OR2[17:18] = 11
	171	* 9 columns OR2[19-21] = 010
	172	* 13 rows OR2[23-25] = 100
	173	* EAD set for extra time OR[31] = 1
	174	*
	175	* 0 4 8 12 16 20 24 28
	176	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	177	*/
	178
6d0f6bcf	179	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	182	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	183	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	184	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	185
b0fe93ed KG	186	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	187	\| LSDMR_RFCR5 \
	188	\| LSDMR_PRETOACT3 \
	189	\| LSDMR_ACTTORW3 \
	190	\| LSDMR_BL8 \
	191	\| LSDMR_WRC2 \
	192	\| LSDMR_CL3 \
	193	\| LSDMR_RFEN \
0ac6f8b7 WD	194	)
	195
	196	/*
	197	* SDRAM Controller configuration sequence.
	198	*/
b0fe93ed KG	199	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	200	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	201	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	202	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	203	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	204
42d1f039	205
9aea9530 WD	206	/*
	207	* 32KB, 8-bit wide for ADS config reg
	208	*/
6d0f6bcf JCPV	209	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	210	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	211	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	214	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	215	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	216
25ddd1fb	217	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	218	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	219
6d0f6bcf JCPV	220	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	221	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	222
	223	/* Serial Port */
	224	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	225	#define CONFIG_SYS_NS16550
	226	#define CONFIG_SYS_NS16550_SERIAL
	227	#define CONFIG_SYS_NS16550_REG_SIZE 1
	228	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
42d1f039	229
6d0f6bcf	230	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	231	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
42d1f039 WD	232
6d0f6bcf JCPV	233	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	234	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
42d1f039 WD	235
42d1f039 WD	236	/* Use the HUSH parser */
6d0f6bcf JCPV	237	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	238	#ifdef CONFIG_SYS_HUSH_PARSER
42d1f039 WD	239	#endif
42d1f039 WD	240
0e16387d	241	/* pass open firmware flat tree */
0fd5ec66 KG	242	#define CONFIG_OF_LIBFDT 1
	243	#define CONFIG_OF_BOARD_SETUP 1
	244	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
0e16387d	245
20476726 JL	246	/*
	247	* I2C
	248	*/
00f792e0 HS	249	#define CONFIG_SYS_I2C
	250	#define CONFIG_SYS_I2C_FSL
	251	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	252	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	253	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	254	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
0ac6f8b7 WD	255
0ac6f8b7 WD	256	/* RapidIO MMU */
5af0fdd8	257	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	258	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	259	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	260	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	261
	262	/*
	263	* General PCI
362dd830	264	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	265	*/
5af0fdd8	266	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	267	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	268	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	269	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	270	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	271	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	272	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	273	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
42d1f039	274
42d1f039	275	#if defined(CONFIG_PCI)
0ac6f8b7	276
53677ef1	277	#define CONFIG_PCI_PNP /* do pci plug-and-play */
0ac6f8b7	278
42d1f039	279	#undef CONFIG_EEPRO100
0ac6f8b7 WD	280	#undef CONFIG_TULIP
	281
	282	#if !defined(CONFIG_PCI_PNP)
	283	#define PCI_ENET0_IOADDR 0xe0000000
	284	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	285	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	286	#endif
0ac6f8b7 WD	287
0ac6f8b7 WD	288	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	289	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	290
	291	#endif /* CONFIG_PCI */
	292
	293
	294	#if defined(CONFIG_TSEC_ENET)
	295
0ac6f8b7	296	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	297	#define CONFIG_TSEC1 1
	298	#define CONFIG_TSEC1_NAME "TSEC0"
	299	#define CONFIG_TSEC2 1
	300	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	301	#define TSEC1_PHY_ADDR 0
0ac6f8b7 WD	302	#define TSEC2_PHY_ADDR 1
0ac6f8b7 WD	303	#define TSEC1_PHYIDX 0
0ac6f8b7 WD	304	#define TSEC2_PHYIDX 0
3a79013e AF	305	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	306	#define TSEC2_FLAGS TSEC_GIGABIT
9aea9530	307
288693ab JL	308
288693ab JL	309	#if CONFIG_HAS_FEC
9aea9530	310	#define CONFIG_MPC85XX_FEC 1
d9b94f28	311	#define CONFIG_MPC85XX_FEC_NAME "FEC"
9aea9530	312	#define FEC_PHY_ADDR 3
0ac6f8b7	313	#define FEC_PHYIDX 0
3a79013e	314	#define FEC_FLAGS 0
288693ab	315	#endif
9aea9530	316
d9b94f28 JL	317	/* Options are: TSEC[0-1], FEC */
d9b94f28 JL	318	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7 WD	319
	320	#endif /* CONFIG_TSEC_ENET */
	321
	322
	323	/*
	324	* Environment
	325	*/
6d0f6bcf	326	#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0	327	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	328	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	329	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	330	#define CONFIG_ENV_SIZE 0x2000
42d1f039	331	#else
6d0f6bcf	332	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725	333	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	334	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	335	#define CONFIG_ENV_SIZE 0x2000
42d1f039 WD	336	#endif
42d1f039 WD	337
0ac6f8b7	338	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	339	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	340
2835e518	341
659e2f67 JL	342	/*
	343	* BOOTP options
	344	*/
	345	#define CONFIG_BOOTP_BOOTFILESIZE
	346	#define CONFIG_BOOTP_BOOTPATH
	347	#define CONFIG_BOOTP_GATEWAY
	348	#define CONFIG_BOOTP_HOSTNAME
	349
	350
2835e518 JL	351	/*
	352	* Command line configuration.
	353	*/
2835e518 JL	354	#define CONFIG_CMD_PING
2835e518 JL	355	#define CONFIG_CMD_I2C
82ac8c97	356	#define CONFIG_CMD_ELF
1c9aa76b	357	#define CONFIG_CMD_IRQ
2835e518 JL	358
	359	#if defined(CONFIG_PCI)
	360	#define CONFIG_CMD_PCI
	361	#endif
	362
0ac6f8b7	363	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	364
	365	/*
	366	* Miscellaneous configurable options
	367	*/
6d0f6bcf	368	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	369	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	370	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	371	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
0ac6f8b7	372
2835e518	373	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	374	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	375	#else
6d0f6bcf	376	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	377	#endif
0ac6f8b7	378
6d0f6bcf JCPV	379	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	380	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	381	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42d1f039 WD	382
	383	/*
	384	* For booting Linux, the board info and command line data
a832ac41	385	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	386	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	387	*/
a832ac41 KG	388	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	389	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	390
2835e518	391	#if defined(CONFIG_CMD_KGDB)
42d1f039	392	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
42d1f039 WD	393	#endif
42d1f039 WD	394
9aea9530 WD	395
	396	/*
	397	* Environment Configuration
	398	*/
0ac6f8b7 WD	399
0ac6f8b7 WD	400	/* The mac addresses for all ethernet interface */
42d1f039	401	#if defined(CONFIG_TSEC_ENET)
10327dc5	402	#define CONFIG_HAS_ETH0
e2ffd59b	403	#define CONFIG_HAS_ETH1
e2ffd59b	404	#define CONFIG_HAS_ETH2
42d1f039 WD	405	#endif
42d1f039 WD	406
0ac6f8b7 WD	407	#define CONFIG_IPADDR 192.168.1.253
	408
	409	#define CONFIG_HOSTNAME unknown
8b3637c6	410	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	411	#define CONFIG_BOOTFILE "your.uImage"
0ac6f8b7 WD	412
	413	#define CONFIG_SERVERIP 192.168.1.1
	414	#define CONFIG_GATEWAYIP 192.168.1.1
	415	#define CONFIG_NETMASK 255.255.255.0
	416
	417	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	418
	419	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	420	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	421
	422	#define CONFIG_BAUDRATE 115200
	423
9aea9530	424	#define CONFIG_EXTRA_ENV_SETTINGS \
0ac6f8b7 WD	425	"netdev=eth0\0" \
0ac6f8b7 WD	426	"consoledev=ttyS0\0" \
d3ec0d94	427	"ramdiskaddr=1000000\0" \
8272dc2f AF	428	"ramdiskfile=your.ramdisk.u-boot\0" \
	429	"fdtaddr=400000\0" \
	430	"fdtfile=your.fdt.dtb\0"
0ac6f8b7	431
9aea9530	432	#define CONFIG_NFSBOOTCOMMAND \
0ac6f8b7 WD	433	"setenv bootargs root=/dev/nfs rw " \
	434	"nfsroot=$serverip:$rootpath " \
	435	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	436	"console=$consoledev,$baudrate $othbootargs;" \
	437	"tftp $loadaddr $bootfile;" \
8272dc2f AF	438	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	439	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	440
	441	#define CONFIG_RAMBOOTCOMMAND \
	442	"setenv bootargs root=/dev/ram rw " \
	443	"console=$consoledev,$baudrate $othbootargs;" \
	444	"tftp $ramdiskaddr $ramdiskfile;" \
	445	"tftp $loadaddr $bootfile;" \
8272dc2f	446	"tftp $fdtaddr $fdtfile;" \
d3ec0d94	447	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	448
0ac6f8b7 WD	449	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	450
42d1f039 WD	451	#endif /* __CONFIG_H */