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42d1f039 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
42d1f039 WD |
7 | */ |
8 | ||
0ac6f8b7 WD |
9 | /* |
10 | * mpc8540ads board configuration file | |
11 | * | |
12 | * Please refer to doc/README.mpc85xx for more info. | |
13 | * | |
14 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 15 | * search for CONFIG_SERVERIP, etc in this file. |
42d1f039 WD |
16 | */ |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
21 | /* High Level Configuration Options */ | |
0ac6f8b7 WD |
22 | #define CONFIG_BOOKE 1 /* BOOKE */ |
23 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
0ac6f8b7 | 24 | |
2ae18241 WD |
25 | /* |
26 | * default CCARBAR is at 0xff700000 | |
27 | * assume U-Boot is less than 0.5MB | |
28 | */ | |
29 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
30 | ||
288693ab JL |
31 | #ifndef CONFIG_HAS_FEC |
32 | #define CONFIG_HAS_FEC 1 /* 8540 has FEC */ | |
33 | #endif | |
34 | ||
842033e6 | 35 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0151cbac | 36 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 37 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
42d1f039 | 38 | #define CONFIG_ENV_OVERWRITE |
7232a272 | 39 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
42d1f039 | 40 | |
0ac6f8b7 WD |
41 | /* |
42 | * sysclk for MPC85xx | |
43 | * | |
44 | * Two valid values are: | |
45 | * 33000000 | |
46 | * 66000000 | |
47 | * | |
48 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
49 | * is likely the desired value here, so that is now the default. |
50 | * The board, however, can run at 66MHz. In any event, this value | |
51 | * must match the settings of some switches. Details can be found | |
52 | * in the README.mpc85xxads. | |
34c3c0e0 MM |
53 | * |
54 | * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to | |
55 | * 33MHz to accommodate, based on a PCI pin. | |
56 | * Note that PCI-X won't work at 33MHz. | |
0ac6f8b7 WD |
57 | */ |
58 | ||
9aea9530 | 59 | #ifndef CONFIG_SYS_CLK_FREQ |
34c3c0e0 | 60 | #define CONFIG_SYS_CLK_FREQ 33000000 |
42d1f039 WD |
61 | #endif |
62 | ||
0ac6f8b7 WD |
63 | /* |
64 | * These can be toggled for performance analysis, otherwise use default. | |
65 | */ | |
66 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
67 | #define CONFIG_BTB /* toggle branch predition */ | |
42d1f039 | 68 | |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
70 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
42d1f039 | 71 | |
e46fedfe TT |
72 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
73 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
42d1f039 | 74 | |
9617c8d4 | 75 | /* DDR Setup */ |
5614e71b | 76 | #define CONFIG_SYS_FSL_DDR1 |
9617c8d4 KG |
77 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
78 | #define CONFIG_DDR_SPD | |
79 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
80 | ||
81 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9aea9530 | 82 | |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
84 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9aea9530 | 85 | |
9617c8d4 KG |
86 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
87 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
88 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
89 | ||
90 | /* I2C addresses of SPD EEPROMs */ | |
91 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
92 | ||
93 | /* These are used when DDR doesn't use SPD. */ | |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ |
95 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
96 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 | |
97 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 | |
98 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
99 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
100 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
101 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
42d1f039 | 102 | |
0ac6f8b7 WD |
103 | /* |
104 | * SDRAM on the Local Bus | |
105 | */ | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
107 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
42d1f039 | 108 | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
110 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
113 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
114 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
115 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
116 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
117 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
0ac6f8b7 | 118 | |
14d0a02a | 119 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
42d1f039 | 120 | |
6d0f6bcf JCPV |
121 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
122 | #define CONFIG_SYS_RAMBOOT | |
42d1f039 | 123 | #else |
6d0f6bcf | 124 | #undef CONFIG_SYS_RAMBOOT |
42d1f039 WD |
125 | #endif |
126 | ||
00b1883a | 127 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_FLASH_CFI |
129 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
42d1f039 | 130 | |
0ac6f8b7 WD |
131 | #undef CONFIG_CLOCKS_IN_MHZ |
132 | ||
0ac6f8b7 WD |
133 | /* |
134 | * Local Bus Definitions | |
135 | */ | |
136 | ||
137 | /* | |
138 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 139 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
0ac6f8b7 WD |
140 | * |
141 | * For BR2, need: | |
142 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
143 | * port-size = 32-bits = BR2[19:20] = 11 | |
144 | * no parity checking = BR2[21:22] = 00 | |
145 | * SDRAM for MSEL = BR2[24:26] = 011 | |
146 | * Valid = BR[31] = 1 | |
147 | * | |
148 | * 0 4 8 12 16 20 24 28 | |
149 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
150 | * | |
6d0f6bcf | 151 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
0ac6f8b7 WD |
152 | * FIXME: the top 17 bits of BR2. |
153 | */ | |
154 | ||
6d0f6bcf | 155 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
0ac6f8b7 WD |
156 | |
157 | /* | |
6d0f6bcf | 158 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
0ac6f8b7 WD |
159 | * |
160 | * For OR2, need: | |
161 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
162 | * XAM, OR2[17:18] = 11 | |
163 | * 9 columns OR2[19-21] = 010 | |
164 | * 13 rows OR2[23-25] = 100 | |
165 | * EAD set for extra time OR[31] = 1 | |
166 | * | |
167 | * 0 4 8 12 16 20 24 28 | |
168 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
169 | */ | |
170 | ||
6d0f6bcf | 171 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
0ac6f8b7 | 172 | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
174 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
175 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
176 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
0ac6f8b7 | 177 | |
b0fe93ed KG |
178 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ |
179 | | LSDMR_RFCR5 \ | |
180 | | LSDMR_PRETOACT3 \ | |
181 | | LSDMR_ACTTORW3 \ | |
182 | | LSDMR_BL8 \ | |
183 | | LSDMR_WRC2 \ | |
184 | | LSDMR_CL3 \ | |
185 | | LSDMR_RFEN \ | |
0ac6f8b7 WD |
186 | ) |
187 | ||
188 | /* | |
189 | * SDRAM Controller configuration sequence. | |
190 | */ | |
b0fe93ed KG |
191 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
192 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
193 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
194 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
195 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
0ac6f8b7 | 196 | |
9aea9530 WD |
197 | /* |
198 | * 32KB, 8-bit wide for ADS config reg | |
199 | */ | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 |
201 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 | |
202 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) | |
42d1f039 | 203 | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
205 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 206 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
42d1f039 | 207 | |
25ddd1fb | 208 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 209 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
42d1f039 | 210 | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
212 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
42d1f039 WD |
213 | |
214 | /* Serial Port */ | |
215 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_NS16550_SERIAL |
217 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
218 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
42d1f039 | 219 | |
6d0f6bcf | 220 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
42d1f039 WD |
221 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
222 | ||
6d0f6bcf JCPV |
223 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
224 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
42d1f039 | 225 | |
20476726 JL |
226 | /* |
227 | * I2C | |
228 | */ | |
00f792e0 HS |
229 | #define CONFIG_SYS_I2C |
230 | #define CONFIG_SYS_I2C_FSL | |
231 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
232 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
233 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
234 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
0ac6f8b7 WD |
235 | |
236 | /* RapidIO MMU */ | |
5af0fdd8 | 237 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
10795f42 | 238 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ |
5af0fdd8 | 239 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 |
6d0f6bcf | 240 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
0ac6f8b7 WD |
241 | |
242 | /* | |
243 | * General PCI | |
362dd830 | 244 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 | 245 | */ |
5af0fdd8 | 246 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 247 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 248 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 249 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 250 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 251 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
253 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
42d1f039 | 254 | |
42d1f039 | 255 | #if defined(CONFIG_PCI) |
42d1f039 | 256 | #undef CONFIG_EEPRO100 |
0ac6f8b7 WD |
257 | #undef CONFIG_TULIP |
258 | ||
259 | #if !defined(CONFIG_PCI_PNP) | |
260 | #define PCI_ENET0_IOADDR 0xe0000000 | |
261 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 262 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
42d1f039 | 263 | #endif |
0ac6f8b7 WD |
264 | |
265 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
0ac6f8b7 WD |
267 | |
268 | #endif /* CONFIG_PCI */ | |
269 | ||
0ac6f8b7 WD |
270 | #if defined(CONFIG_TSEC_ENET) |
271 | ||
0ac6f8b7 | 272 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
273 | #define CONFIG_TSEC1 1 |
274 | #define CONFIG_TSEC1_NAME "TSEC0" | |
275 | #define CONFIG_TSEC2 1 | |
276 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
277 | #define TSEC1_PHY_ADDR 0 |
278 | #define TSEC2_PHY_ADDR 1 | |
0ac6f8b7 WD |
279 | #define TSEC1_PHYIDX 0 |
280 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
281 | #define TSEC1_FLAGS TSEC_GIGABIT |
282 | #define TSEC2_FLAGS TSEC_GIGABIT | |
9aea9530 | 283 | |
288693ab | 284 | #if CONFIG_HAS_FEC |
9aea9530 | 285 | #define CONFIG_MPC85XX_FEC 1 |
d9b94f28 | 286 | #define CONFIG_MPC85XX_FEC_NAME "FEC" |
9aea9530 | 287 | #define FEC_PHY_ADDR 3 |
0ac6f8b7 | 288 | #define FEC_PHYIDX 0 |
3a79013e | 289 | #define FEC_FLAGS 0 |
288693ab | 290 | #endif |
9aea9530 | 291 | |
d9b94f28 JL |
292 | /* Options are: TSEC[0-1], FEC */ |
293 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 WD |
294 | |
295 | #endif /* CONFIG_TSEC_ENET */ | |
296 | ||
0ac6f8b7 WD |
297 | /* |
298 | * Environment | |
299 | */ | |
6d0f6bcf | 300 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 301 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 302 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
303 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
304 | #define CONFIG_ENV_SIZE 0x2000 | |
42d1f039 | 305 | #else |
6d0f6bcf | 306 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 307 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 308 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 309 | #define CONFIG_ENV_SIZE 0x2000 |
42d1f039 WD |
310 | #endif |
311 | ||
0ac6f8b7 | 312 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 313 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
42d1f039 | 314 | |
659e2f67 JL |
315 | /* |
316 | * BOOTP options | |
317 | */ | |
318 | #define CONFIG_BOOTP_BOOTFILESIZE | |
319 | #define CONFIG_BOOTP_BOOTPATH | |
320 | #define CONFIG_BOOTP_GATEWAY | |
321 | #define CONFIG_BOOTP_HOSTNAME | |
322 | ||
2835e518 JL |
323 | /* |
324 | * Command line configuration. | |
325 | */ | |
1c9aa76b | 326 | #define CONFIG_CMD_IRQ |
2835e518 JL |
327 | |
328 | #if defined(CONFIG_PCI) | |
329 | #define CONFIG_CMD_PCI | |
330 | #endif | |
331 | ||
0ac6f8b7 | 332 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
333 | |
334 | /* | |
335 | * Miscellaneous configurable options | |
336 | */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
338 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
339 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 340 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
0ac6f8b7 | 341 | |
2835e518 | 342 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 343 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 344 | #else |
6d0f6bcf | 345 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 346 | #endif |
0ac6f8b7 | 347 | |
6d0f6bcf JCPV |
348 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
349 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
350 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
42d1f039 WD |
351 | |
352 | /* | |
353 | * For booting Linux, the board info and command line data | |
a832ac41 | 354 | * have to be in the first 64 MB of memory, since this is |
42d1f039 WD |
355 | * the maximum mapped by the Linux kernel during initialization. |
356 | */ | |
a832ac41 KG |
357 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
358 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
42d1f039 | 359 | |
2835e518 | 360 | #if defined(CONFIG_CMD_KGDB) |
42d1f039 | 361 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
42d1f039 WD |
362 | #endif |
363 | ||
9aea9530 WD |
364 | /* |
365 | * Environment Configuration | |
366 | */ | |
0ac6f8b7 WD |
367 | |
368 | /* The mac addresses for all ethernet interface */ | |
42d1f039 | 369 | #if defined(CONFIG_TSEC_ENET) |
10327dc5 | 370 | #define CONFIG_HAS_ETH0 |
e2ffd59b | 371 | #define CONFIG_HAS_ETH1 |
e2ffd59b | 372 | #define CONFIG_HAS_ETH2 |
42d1f039 WD |
373 | #endif |
374 | ||
0ac6f8b7 WD |
375 | #define CONFIG_IPADDR 192.168.1.253 |
376 | ||
377 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 378 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 379 | #define CONFIG_BOOTFILE "your.uImage" |
0ac6f8b7 WD |
380 | |
381 | #define CONFIG_SERVERIP 192.168.1.1 | |
382 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
383 | #define CONFIG_NETMASK 255.255.255.0 | |
384 | ||
385 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
386 | ||
0ac6f8b7 WD |
387 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
388 | ||
389 | #define CONFIG_BAUDRATE 115200 | |
390 | ||
9aea9530 | 391 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
0ac6f8b7 WD |
392 | "netdev=eth0\0" \ |
393 | "consoledev=ttyS0\0" \ | |
d3ec0d94 | 394 | "ramdiskaddr=1000000\0" \ |
8272dc2f AF |
395 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
396 | "fdtaddr=400000\0" \ | |
397 | "fdtfile=your.fdt.dtb\0" | |
0ac6f8b7 | 398 | |
9aea9530 | 399 | #define CONFIG_NFSBOOTCOMMAND \ |
0ac6f8b7 WD |
400 | "setenv bootargs root=/dev/nfs rw " \ |
401 | "nfsroot=$serverip:$rootpath " \ | |
402 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
403 | "console=$consoledev,$baudrate $othbootargs;" \ | |
404 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f AF |
405 | "tftp $fdtaddr $fdtfile;" \ |
406 | "bootm $loadaddr - $fdtaddr" | |
0ac6f8b7 WD |
407 | |
408 | #define CONFIG_RAMBOOTCOMMAND \ | |
409 | "setenv bootargs root=/dev/ram rw " \ | |
410 | "console=$consoledev,$baudrate $othbootargs;" \ | |
411 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
412 | "tftp $loadaddr $bootfile;" \ | |
8272dc2f | 413 | "tftp $fdtaddr $fdtfile;" \ |
d3ec0d94 | 414 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
0ac6f8b7 WD |
415 | |
416 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
417 | |
418 | #endif /* __CONFIG_H */ |