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1 | /* |
2 | * Copyright 2004 Freescale Semiconductor. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8541cds board configuration file | |
25 | * | |
26 | * Please refer to doc/README.mpc85xxcds for more info. | |
27 | * | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* High Level Configuration Options */ | |
34 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
35 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
36 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ | |
37 | #define CONFIG_MPC8541 1 /* MPC8541 specific */ | |
38 | #define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */ | |
39 | ||
40 | #define CONFIG_PCI | |
41 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
42 | #define CONFIG_ENV_OVERWRITE | |
43 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
44 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
45 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
46 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
47 | ||
48 | /* | |
49 | * When initializing flash, if we cannot find the manufacturer ID, | |
50 | * assume this is the AMD flash associated with the CDS board. | |
51 | * This allows booting from a promjet. | |
52 | */ | |
53 | #define CONFIG_ASSUME_AMD_FLASH | |
54 | ||
55 | #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ | |
56 | ||
57 | #ifndef __ASSEMBLY__ | |
58 | extern unsigned long get_clock_freq(void); | |
59 | #endif | |
60 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
61 | ||
62 | /* | |
63 | * These can be toggled for performance analysis, otherwise use default. | |
64 | */ | |
65 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
66 | #define CONFIG_BTB /* toggle branch predition */ | |
67 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
68 | ||
69 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
70 | ||
71 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
72 | #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ | |
73 | #define CFG_MEMTEST_END 0x00400000 | |
74 | ||
75 | ||
76 | /* | |
77 | * Base addresses -- Note these are effective addresses where the | |
78 | * actual resources get mapped (not physical addresses) | |
79 | */ | |
80 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
81 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
82 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
83 | ||
84 | ||
85 | /* | |
86 | * DDR Setup | |
87 | */ | |
88 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
89 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
90 | ||
91 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
92 | ||
93 | /* | |
94 | * Make sure required options are set | |
95 | */ | |
96 | #ifndef CONFIG_SPD_EEPROM | |
97 | #error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") | |
98 | #endif | |
99 | ||
100 | ||
101 | ||
102 | /* | |
103 | * SDRAM on the Local Bus | |
104 | */ | |
105 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
106 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
107 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ | |
108 | ||
109 | #define CFG_BR0_PRELIM 0xff801001 /* port size 16bit */ | |
110 | #define CFG_BR1_PRELIM 0xff001001 /* port size 16bit */ | |
111 | ||
112 | #define CFG_OR0_PRELIM 0xff806e61 /* 8MB Flash */ | |
113 | #define CFG_OR1_PRELIM 0xff806e61 /* 8MB Flash */ | |
114 | ||
115 | #define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} | |
116 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
117 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ | |
118 | #undef CFG_FLASH_CHECKSUM | |
119 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
120 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
121 | ||
122 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
123 | ||
124 | #define CFG_FLASH_CFI_DRIVER | |
125 | #define CFG_FLASH_CFI | |
126 | #define CFG_FLASH_EMPTY_INFO | |
127 | ||
128 | #undef CONFIG_CLOCKS_IN_MHZ | |
129 | ||
130 | /* | |
131 | * Local Bus Definitions | |
132 | */ | |
133 | ||
134 | /* | |
135 | * Base Register 2 and Option Register 2 configure SDRAM. | |
136 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. | |
137 | * | |
138 | * For BR2, need: | |
139 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
140 | * port-size = 32-bits = BR2[19:20] = 11 | |
141 | * no parity checking = BR2[21:22] = 00 | |
142 | * SDRAM for MSEL = BR2[24:26] = 011 | |
143 | * Valid = BR[31] = 1 | |
144 | * | |
145 | * 0 4 8 12 16 20 24 28 | |
146 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
147 | * | |
148 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into | |
149 | * FIXME: the top 17 bits of BR2. | |
150 | */ | |
151 | ||
152 | #define CFG_BR2_PRELIM 0xf0001861 | |
153 | ||
154 | /* | |
155 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. | |
156 | * | |
157 | * For OR2, need: | |
158 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
159 | * XAM, OR2[17:18] = 11 | |
160 | * 9 columns OR2[19-21] = 010 | |
161 | * 13 rows OR2[23-25] = 100 | |
162 | * EAD set for extra time OR[31] = 1 | |
163 | * | |
164 | * 0 4 8 12 16 20 24 28 | |
165 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
166 | */ | |
167 | ||
168 | #define CFG_OR2_PRELIM 0xfc006901 | |
169 | ||
170 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
171 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
172 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
173 | #define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
174 | ||
175 | /* | |
176 | * LSDMR masks | |
177 | */ | |
178 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) | |
179 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | |
180 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | |
181 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | |
182 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) | |
183 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) | |
184 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) | |
185 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) | |
186 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) | |
187 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) | |
188 | ||
189 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) | |
190 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
191 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
192 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) | |
193 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
194 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) | |
195 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
196 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) | |
197 | ||
198 | /* | |
199 | * Common settings for all Local Bus SDRAM commands. | |
200 | * At run time, either BSMA1516 (for CPU 1.1) | |
201 | * or BSMA1617 (for CPU 1.0) (old) | |
202 | * is OR'ed in too. | |
203 | */ | |
204 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ | |
205 | | CFG_LBC_LSDMR_PRETOACT7 \ | |
206 | | CFG_LBC_LSDMR_ACTTORW7 \ | |
207 | | CFG_LBC_LSDMR_BL8 \ | |
208 | | CFG_LBC_LSDMR_WRC4 \ | |
209 | | CFG_LBC_LSDMR_CL3 \ | |
210 | | CFG_LBC_LSDMR_RFEN \ | |
211 | ) | |
212 | ||
213 | /* | |
214 | * The CADMUS registers are connected to CS3 on CDS. | |
215 | * The new memory map places CADMUS at 0xf8000000. | |
216 | * | |
217 | * For BR3, need: | |
218 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
219 | * port-size = 8-bits = BR[19:20] = 01 | |
220 | * no parity checking = BR[21:22] = 00 | |
221 | * GPMC for MSEL = BR[24:26] = 000 | |
222 | * Valid = BR[31] = 1 | |
223 | * | |
224 | * 0 4 8 12 16 20 24 28 | |
225 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
226 | * | |
227 | * For OR3, need: | |
228 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
229 | * disable buffer ctrl OR[19] = 0 | |
230 | * CSNT OR[20] = 1 | |
231 | * ACS OR[21:22] = 11 | |
232 | * XACS OR[23] = 1 | |
233 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
234 | * SETA OR[28] = 0 | |
235 | * TRLX OR[29] = 1 | |
236 | * EHTR OR[30] = 1 | |
237 | * EAD extra time OR[31] = 1 | |
238 | * | |
239 | * 0 4 8 12 16 20 24 28 | |
240 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
241 | */ | |
242 | ||
243 | #define CADMUS_BASE_ADDR 0xf8000000 | |
244 | #define CFG_BR3_PRELIM 0xf8000801 | |
245 | #define CFG_OR3_PRELIM 0xfff00ff7 | |
246 | ||
247 | ||
248 | #define CONFIG_L1_INIT_RAM | |
249 | #define CFG_INIT_RAM_LOCK 1 | |
250 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
251 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
252 | ||
253 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
254 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
255 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
256 | ||
257 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ | |
258 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
259 | ||
260 | /* Serial Port */ | |
261 | #define CONFIG_CONS_INDEX 2 | |
262 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
263 | #define CFG_NS16550 | |
264 | #define CFG_NS16550_SERIAL | |
265 | #define CFG_NS16550_REG_SIZE 1 | |
266 | #define CFG_NS16550_CLK get_bus_freq(0) | |
267 | ||
268 | #define CFG_BAUDRATE_TABLE \ | |
269 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
270 | ||
271 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
272 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
273 | ||
274 | /* Use the HUSH parser */ | |
275 | #define CFG_HUSH_PARSER | |
276 | #ifdef CFG_HUSH_PARSER | |
277 | #define CFG_PROMPT_HUSH_PS2 "> " | |
278 | #endif | |
279 | ||
280 | /* I2C */ | |
281 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
282 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
283 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
284 | #define CFG_I2C_EEPROM_ADDR 0x57 | |
285 | #define CFG_I2C_SLAVE 0x7F | |
286 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
287 | ||
288 | /* | |
289 | * General PCI | |
290 | * Addresses are mapped 1-1. | |
291 | */ | |
292 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
293 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
294 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
295 | #define CFG_PCI1_IO_BASE 0xe2000000 | |
296 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE | |
297 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
298 | ||
299 | #define CFG_PCI2_MEM_BASE 0xa0000000 | |
300 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
301 | #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ | |
302 | #define CFG_PCI2_IO_BASE 0xe3000000 | |
303 | #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE | |
304 | #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ | |
305 | ||
306 | ||
307 | #if defined(CONFIG_PCI) | |
308 | ||
309 | #define CONFIG_NET_MULTI | |
310 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
311 | ||
312 | #undef CONFIG_EEPRO100 | |
313 | #undef CONFIG_TULIP | |
314 | ||
315 | #if !defined(CONFIG_PCI_PNP) | |
316 | #define PCI_ENET0_IOADDR 0xe0000000 | |
317 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
318 | #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ | |
319 | #endif | |
320 | ||
321 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
322 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
323 | ||
324 | #endif /* CONFIG_PCI */ | |
325 | ||
326 | ||
327 | #if defined(CONFIG_TSEC_ENET) | |
328 | ||
329 | #ifndef CONFIG_NET_MULTI | |
330 | #define CONFIG_NET_MULTI 1 | |
331 | #endif | |
332 | ||
333 | #define CONFIG_MII 1 /* MII PHY management */ | |
334 | #define CONFIG_MPC85XX_TSEC1 1 | |
335 | #define CONFIG_MPC85XX_TSEC2 1 | |
336 | #undef CONFIG_MPC85XX_FEC | |
337 | #define TSEC1_PHY_ADDR 0 | |
338 | #define TSEC2_PHY_ADDR 1 | |
339 | #define FEC_PHY_ADDR 3 | |
340 | #define TSEC1_PHYIDX 0 | |
341 | #define TSEC2_PHYIDX 0 | |
342 | #define FEC_PHYIDX 0 | |
343 | #define CONFIG_ETHPRIME "MOTO ENET0" | |
344 | ||
345 | #endif /* CONFIG_TSEC_ENET */ | |
346 | ||
347 | ||
348 | ||
349 | /* | |
350 | * Environment | |
351 | */ | |
352 | #define CFG_ENV_IS_IN_FLASH 1 | |
353 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
354 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ | |
355 | #define CFG_ENV_SIZE 0x2000 | |
356 | ||
357 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
358 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
359 | ||
360 | #if defined(CONFIG_PCI) | |
361 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
362 | | CFG_CMD_PCI \ | |
363 | | CFG_CMD_PING \ | |
364 | | CFG_CMD_I2C \ | |
365 | | CFG_CMD_MII) | |
366 | #else | |
367 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
368 | | CFG_CMD_PING \ | |
369 | | CFG_CMD_I2C \ | |
370 | | CFG_CMD_MII) | |
371 | #endif | |
372 | ||
373 | ||
374 | #include <cmd_confdefs.h> | |
375 | ||
376 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
377 | ||
378 | /* | |
379 | * Miscellaneous configurable options | |
380 | */ | |
381 | #define CFG_LONGHELP /* undef to save memory */ | |
382 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
383 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
384 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
385 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
386 | #else | |
387 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
388 | #endif | |
389 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
390 | #define CFG_MAXARGS 16 /* max number of command args */ | |
391 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
392 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
393 | ||
394 | /* | |
395 | * For booting Linux, the board info and command line data | |
396 | * have to be in the first 8 MB of memory, since this is | |
397 | * the maximum mapped by the Linux kernel during initialization. | |
398 | */ | |
399 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
400 | ||
401 | /* Cache Configuration */ | |
402 | #define CFG_DCACHE_SIZE 32768 | |
403 | #define CFG_CACHELINE_SIZE 32 | |
404 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
405 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ | |
406 | #endif | |
407 | ||
408 | /* | |
409 | * Internal Definitions | |
410 | * | |
411 | * Boot Flags | |
412 | */ | |
413 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
414 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
415 | ||
416 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
417 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
418 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
419 | #endif | |
420 | ||
421 | ||
422 | /* | |
423 | * Environment Configuration | |
424 | */ | |
425 | ||
426 | /* The mac addresses for all ethernet interface */ | |
427 | #if defined(CONFIG_TSEC_ENET) | |
428 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD | |
429 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD | |
430 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
431 | #endif | |
432 | ||
433 | #define CONFIG_IPADDR 192.168.1.253 | |
434 | ||
435 | #define CONFIG_HOSTNAME unknown | |
436 | #define CONFIG_ROOTPATH /nfsroot | |
437 | #define CONFIG_BOOTFILE your.uImage | |
438 | ||
439 | #define CONFIG_SERVERIP 192.168.1.1 | |
440 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
441 | #define CONFIG_NETMASK 255.255.255.0 | |
442 | ||
443 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
444 | ||
445 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
446 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
447 | ||
448 | #define CONFIG_BAUDRATE 115200 | |
449 | ||
450 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
451 | "netdev=eth0\0" \ | |
452 | "consoledev=ttyS1\0" \ | |
453 | "ramdiskaddr=400000\0" \ | |
454 | "ramdiskfile=your.ramdisk.u-boot\0" | |
455 | ||
456 | #define CONFIG_NFSBOOTCOMMAND \ | |
457 | "setenv bootargs root=/dev/nfs rw " \ | |
458 | "nfsroot=$serverip:$rootpath " \ | |
459 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
460 | "console=$consoledev,$baudrate $othbootargs;" \ | |
461 | "tftp $loadaddr $bootfile;" \ | |
462 | "bootm $loadaddr" | |
463 | ||
464 | #define CONFIG_RAMBOOTCOMMAND \ | |
465 | "setenv bootargs root=/dev/ram rw " \ | |
466 | "console=$consoledev,$baudrate $othbootargs;" \ | |
467 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
468 | "tftp $loadaddr $bootfile;" \ | |
469 | "bootm $loadaddr $ramdiskaddr" | |
470 | ||
471 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
472 | ||
473 | ||
474 | #endif /* __CONFIG_H */ |