[thirdparty/u-boot.git] / include / configs / MPC8544DS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
 */

/*
 * mpc8544ds board configuration file
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_PCI1		1	/* PCI controller 1 */
#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */

#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Memory map
 *
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 *
 * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
 *
 * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
 *
 * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
 * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
 *
 * Localbus cacheable
 *
 * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
 * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
 *
 * Localbus non-cacheable
 *
 * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
 * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
 * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
 *
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */

#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */

#define CONFIG_SYS_BR0_PRELIM		0xff801001
#define CONFIG_SYS_BR1_PRELIM		0xfe801001

#define CONFIG_SYS_OR0_PRELIM		0xff806e65
#define CONFIG_SYS_OR1_PRELIM		0xff806e65

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}

#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000

#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/

#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/

#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
#define PIXIS_ID		0x0	/* Board ID at offset 0 */
#define PIXIS_VER		0x1	/* Board version at offset 1 */
#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
					 * register */
#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
#define PIXIS_VCTL		0x10	/* VELA Control Register */
#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
#define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
#define PIXIS_VSPEED2_TSEC1SER	0x2
#define PIXIS_VSPEED2_TSEC3SER	0x1
#define PIXIS_VCFGEN1_TSEC1SER	0x20
#define PIXIS_VCFGEN1_TSEC3SER	0x40
#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)

#define CONFIG_SYS_INIT_RAM_LOCK      1
#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */

#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */

/* controller 2, Slot 1, tgtid 1, Base address 9000 */
#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_NAME		"ULI"
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */

#if defined(CONFIG_PCI)

/*PCIE video card used*/
#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT

/*PCI video card used*/
/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/

/* video */

#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
#define CONFIG_ATI_RADEON_FB
#define CONFIG_VIDEO_LOGO
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#ifndef CONFIG_PCI_PNP
	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

#ifdef CONFIG_SCSI_AHCI
#define CONFIG_SATA_ULI5288
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
#define CONFIG_SYS_SCSI_MAX_LUN	1
#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
#endif /* CONFIG_SCSI_AHCI */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC3"

#define CONFIG_PIXIS_SGMII_CMD
#define CONFIG_FSL_SGMII_RISER	1
#define SGMII_RISER_PHY_OFFSET	0x1c

#define TSEC1_PHY_ADDR		0
#define TSEC3_PHY_ADDR		1

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0
#define TSEC3_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * USB
 */

#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_EHCI_DEVICE			0
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_IPADDR	192.168.1.251

#define CONFIG_HOSTNAME	"8544ds_unknown"
#define CONFIG_ROOTPATH	"/nfs/mpc85xx"
#define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */

#define CONFIG_SERVERIP	192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK	255.255.0.0

#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/

#define	CONFIG_EXTRA_ENV_SETTINGS				\
"netdev=eth0\0"						\
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
"tftpflash=tftpboot $loadaddr $uboot; "			\
	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" +$filesize; "	\
	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
		" +$filesize; "	\
	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" $filesize; "	\
	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
		" +$filesize; "	\
	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
		" $filesize\0"	\
"consoledev=ttyS0\0"				\
"ramdiskaddr=2000000\0"			\
"ramdiskfile=8544ds/ramdisk.uboot\0"		\
"fdtaddr=1e00000\0"				\
"fdtfile=8544ds/mpc8544ds.dtb\0"		\
"bdev=sda3\0"

#define CONFIG_NFSBOOTCOMMAND		\
 "setenv bootargs root=/dev/nfs rw "	\
 "nfsroot=$serverip:$rootpath "		\
 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND		\
 "setenv bootargs root=/dev/ram rw "	\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $ramdiskaddr $ramdiskfile;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		\
 "setenv bootargs root=/dev/$bdev rw "	\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr - $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
0cde4b00	2	/*
7c57f3e8	3	* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
0cde4b00 JL	4	*/
	5
	6	/*
	7	* mpc8544ds board configuration file
	8	*
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
837f1ba0	13	#define CONFIG_PCI1 1 /* PCI controller 1 */
b38eaec5 RD	14	#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
	15	#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
	16	#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
837f1ba0	17	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
842033e6	18	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
0151cbac	19	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
837f1ba0	20
0cde4b00	21	#define CONFIG_ENV_OVERWRITE
837f1ba0	22	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
0cde4b00	23
0cde4b00 JL	24	#ifndef __ASSEMBLY__
	25	extern unsigned long get_board_sys_clk(unsigned long dummy);
	26	#endif
	27	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
	28
	29	/*
	30	* These can be toggled for performance analysis, otherwise use default.
	31	*/
837f1ba0	32	#define CONFIG_L2_CACHE /* toggle L2 cache */
0cde4b00	33	#define CONFIG_BTB /* toggle branch predition */
0cde4b00 JL	34
	35	/*
	36	* Only possible on E500 Version 2 or newer cores.
	37	*/
	38	#define CONFIG_ENABLE_36BIT_PHYS 1
	39
e46fedfe TT	40	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	41	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
0cde4b00	42
1167a2fd	43	/* DDR Setup */
1167a2fd KG	44	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	45	#define CONFIG_DDR_SPD
	46
9b0ad1b1	47	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
1167a2fd KG	48	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
1167a2fd KG	49
6d0f6bcf JCPV	50	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	51	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
1167a2fd KG	52	#define CONFIG_VERY_BIG_RAM
1167a2fd KG	53
1167a2fd KG	54	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
1167a2fd KG	55	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
0cde4b00	56
1167a2fd	57	/* I2C addresses of SPD EEPROMs */
0cde4b00 JL	58	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
0cde4b00 JL	59
1167a2fd	60	/* Make sure required options are set */
0cde4b00 JL	61	#ifndef CONFIG_SPD_EEPROM
	62	#error ("CONFIG_SPD_EEPROM is required")
	63	#endif
	64
	65	#undef CONFIG_CLOCKS_IN_MHZ
	66
	67	/*
	68	* Memory map
	69	*
	70	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	71	*
	72	* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
	73	*
	74	* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
	75	*
	76	* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
	77	* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
	78	*
	79	* Localbus cacheable
	80	*
	81	* 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
	82	* 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
	83	*
	84	* Localbus non-cacheable
	85	*
	86	* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
	87	* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
	88	* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
	89	*
	90	*/
	91
	92	/*
	93	* Local Bus Definitions
	94	*/
6d0f6bcf	95	#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
0cde4b00	96
6d0f6bcf	97	#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
0cde4b00	98
6d0f6bcf JCPV	99	#define CONFIG_SYS_BR0_PRELIM 0xff801001
6d0f6bcf JCPV	100	#define CONFIG_SYS_BR1_PRELIM 0xfe801001
0cde4b00	101
6d0f6bcf JCPV	102	#define CONFIG_SYS_OR0_PRELIM 0xff806e65
6d0f6bcf JCPV	103	#define CONFIG_SYS_OR1_PRELIM 0xff806e65
0cde4b00	104
6d0f6bcf	105	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
0cde4b00	106
6d0f6bcf JCPV	107	#define CONFIG_SYS_FLASH_QUIET_TEST
	108	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	109	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
	110	#undef CONFIG_SYS_FLASH_CHECKSUM
	111	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	112	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
81e56e9a	113	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
0cde4b00	114
14d0a02a	115	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
0cde4b00	116
6d0f6bcf	117	#define CONFIG_SYS_FLASH_EMPTY_INFO
0cde4b00	118
6d0f6bcf	119	#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
0cde4b00	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
6d0f6bcf JCPV	122	#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
0cde4b00	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
6d0f6bcf JCPV	125	#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
0cde4b00	126
7608d75f	127	#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
0cde4b00 JL	128	#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
	129	#define PIXIS_ID 0x0 /* Board ID at offset 0 */
	130	#define PIXIS_VER 0x1 /* Board version at offset 1 */
	131	#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
	132	#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
	133	#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
	134	* register */
	135	#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
	136	#define PIXIS_VCTL 0x10 /* VELA Control Register */
	137	#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
	138	#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
	139	#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
6bb5b412 KG	140	#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
6bb5b412 KG	141	#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
0cde4b00 JL	142	#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
	143	#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
	144	#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
	145	#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
5a8a163a	146	#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
6d0f6bcf	147	#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
5a8a163a AF	148	#define PIXIS_VSPEED2_TSEC1SER 0x2
	149	#define PIXIS_VSPEED2_TSEC3SER 0x1
	150	#define PIXIS_VCFGEN1_TSEC1SER 0x20
	151	#define PIXIS_VCFGEN1_TSEC3SER 0x40
bff188ba LY	152	#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER\|PIXIS_VSPEED2_TSEC3SER)
bff188ba LY	153	#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER\|PIXIS_VCFGEN1_TSEC3SER)
0cde4b00	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	156	#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
553f0982	157	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
1107014e	158
25ddd1fb	159	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	160	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0cde4b00	161
6d0f6bcf JCPV	162	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	163	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
0cde4b00 JL	164
	165	/* Serial Port - controlled on board with jumper J8
	166	* open - index 2
	167	* shorted - index 1
	168	*/
6d0f6bcf JCPV	169	#define CONFIG_SYS_NS16550_SERIAL
	170	#define CONFIG_SYS_NS16550_REG_SIZE 1
	171	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
0cde4b00	172
6d0f6bcf	173	#define CONFIG_SYS_BAUDRATE_TABLE \
0cde4b00 JL	174	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
0cde4b00 JL	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	177	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
0cde4b00	178
0cde4b00	179	/* I2C */
00f792e0 HS	180	#define CONFIG_SYS_I2C
	181	#define CONFIG_SYS_I2C_FSL
	182	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	183	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
7f25fdc7	184	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
00f792e0	185	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
6d0f6bcf	186	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
0cde4b00 JL	187
	188	/*
	189	* General PCI
	190	* Memory space is mapped 1-1, but I/O space must start from 0.
	191	*/
5af0fdd8	192	#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
6d0f6bcf	193	#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
5af0fdd8	194	#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
6d0f6bcf	195	#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
0cde4b00	196
5af0fdd8	197	#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
10795f42	198	#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
5af0fdd8	199	#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
6d0f6bcf	200	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	201	#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
5f91ef6a	202	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	203	#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
6d0f6bcf JCPV	204	#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
0cde4b00	205
0cde4b00	206	/* controller 2, Slot 1, tgtid 1, Base address 9000 */
64a1686a	207	#define CONFIG_SYS_PCIE2_NAME "Slot 1"
5af0fdd8	208	#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
10795f42	209	#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
5af0fdd8	210	#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
6d0f6bcf	211	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
aca5f018	212	#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
5f91ef6a	213	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
6d0f6bcf JCPV	214	#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
6d0f6bcf JCPV	215	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
0cde4b00 JL	216
0cde4b00 JL	217	/* controller 1, Slot 2,tgtid 2, Base address a000 */
64a1686a	218	#define CONFIG_SYS_PCIE1_NAME "Slot 2"
5af0fdd8	219	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
10795f42	220	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
5af0fdd8	221	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
6d0f6bcf	222	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
aca5f018	223	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
5f91ef6a	224	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
6d0f6bcf JCPV	225	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
6d0f6bcf JCPV	226	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
0cde4b00 JL	227
0cde4b00 JL	228	/* controller 3, direct to uli, tgtid 3, Base address b000 */
64a1686a	229	#define CONFIG_SYS_PCIE3_NAME "ULI"
5af0fdd8	230	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
10795f42	231	#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
5af0fdd8	232	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
6d0f6bcf	233	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
aca5f018	234	#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
5f91ef6a	235	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
6d0f6bcf JCPV	236	#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
6d0f6bcf JCPV	237	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
5af0fdd8	238	#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
10795f42	239	#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
5af0fdd8	240	#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
6d0f6bcf	241	#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
0cde4b00 JL	242
	243	#if defined(CONFIG_PCI)
	244
630d9bfc	245	/PCIE video card used/
aca5f018	246	#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
630d9bfc KG	247
630d9bfc KG	248	/PCI video card used/
aca5f018	249	/#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT/
630d9bfc KG	250
630d9bfc KG	251	/* video */
630d9bfc KG	252
	253	#if defined(CONFIG_VIDEO)
	254	#define CONFIG_BIOSEMU
630d9bfc KG	255	#define CONFIG_ATI_RADEON_FB
630d9bfc KG	256	#define CONFIG_VIDEO_LOGO
6d0f6bcf	257	#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
630d9bfc KG	258	#endif
630d9bfc KG	259
0cde4b00 JL	260	#undef CONFIG_EEPRO100
0cde4b00 JL	261	#undef CONFIG_TULIP
0cde4b00	262
0cde4b00	263	#ifndef CONFIG_PCI_PNP
5f91ef6a KG	264	#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
5f91ef6a KG	265	#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
0cde4b00 JL	266	#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
	267	#endif
	268
	269	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
0cde4b00 JL	270
	271	#ifdef CONFIG_SCSI_AHCI
	272	#define CONFIG_SATA_ULI5288
6d0f6bcf JCPV	273	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
	274	#define CONFIG_SYS_SCSI_MAX_LUN 1
	275	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
247b4f9f	276	#endif /* CONFIG_SCSI_AHCI */
0cde4b00 JL	277
	278	#endif /* CONFIG_PCI */
	279
0cde4b00 JL	280	#if defined(CONFIG_TSEC_ENET)
0cde4b00 JL	281
0cde4b00	282	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
255a3577 KP	283	#define CONFIG_TSEC1 1
	284	#define CONFIG_TSEC1_NAME "eTSEC1"
	285	#define CONFIG_TSEC3 1
	286	#define CONFIG_TSEC3_NAME "eTSEC3"
837f1ba0	287
bff188ba	288	#define CONFIG_PIXIS_SGMII_CMD
652f7c2e AF	289	#define CONFIG_FSL_SGMII_RISER 1
	290	#define SGMII_RISER_PHY_OFFSET 0x1c
	291
0cde4b00 JL	292	#define TSEC1_PHY_ADDR 0
	293	#define TSEC3_PHY_ADDR 1
	294
3a79013e AF	295	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	296	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	297
0cde4b00 JL	298	#define TSEC1_PHYIDX 0
	299	#define TSEC3_PHYIDX 0
	300
	301	#define CONFIG_ETHPRIME "eTSEC1"
0cde4b00 JL	302	#endif /* CONFIG_TSEC_ENET */
	303
	304	/*
	305	* Environment
	306	*/
0cde4b00 JL	307
0cde4b00 JL	308	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	309	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
0cde4b00	310
659e2f67 JL	311	/*
	312	* BOOTP options
	313	*/
	314	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	315
86a194b7 HJ	316	/*
	317	* USB
	318	*/
86a194b7	319
8850c5d5	320	#ifdef CONFIG_USB_EHCI_HCD
86a194b7	321	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
86a194b7 HJ	322	#define CONFIG_PCI_EHCI_DEVICE 0
86a194b7 HJ	323	#endif
0cde4b00 JL	324
	325	#undef CONFIG_WATCHDOG /* watchdog disabled */
	326
	327	/*
	328	* Miscellaneous configurable options
	329	*/
6d0f6bcf	330	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
0cde4b00 JL	331
	332	/*
	333	* For booting Linux, the board info and command line data
a832ac41	334	* have to be in the first 64 MB of memory, since this is
0cde4b00 JL	335	* the maximum mapped by the Linux kernel during initialization.
0cde4b00 JL	336	*/
a832ac41 KG	337	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	338	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
0cde4b00	339
2835e518	340	#if defined(CONFIG_CMD_KGDB)
0cde4b00	341	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
0cde4b00 JL	342	#endif
	343
	344	/*
	345	* Environment Configuration
	346	*/
	347
	348	/* The mac addresses for all ethernet interface */
	349	#if defined(CONFIG_TSEC_ENET)
ea5877e3	350	#define CONFIG_HAS_ETH0
0cde4b00	351	#define CONFIG_HAS_ETH1
0cde4b00 JL	352	#endif
	353
	354	#define CONFIG_IPADDR 192.168.1.251
	355
5bc0543d	356	#define CONFIG_HOSTNAME "8544ds_unknown"
8b3637c6	357	#define CONFIG_ROOTPATH "/nfs/mpc85xx"
b3f44c21	358	#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
837f1ba0	359	#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
0cde4b00	360
50c03c8c KG	361	#define CONFIG_SERVERIP 192.168.1.1
50c03c8c KG	362	#define CONFIG_GATEWAYIP 192.168.1.1
0cde4b00 JL	363	#define CONFIG_NETMASK 255.255.0.0
	364
	365	#define CONFIG_LOADADDR 1000000 /default location for tftp and bootm/
	366
837f1ba0	367	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d MV	368	"netdev=eth0\0" \
	369	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	370	"tftpflash=tftpboot $loadaddr $uboot; " \
	371	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	372	" +$filesize; " \
	373	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	374	" +$filesize; " \
	375	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	376	" $filesize; " \
	377	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	378	" +$filesize; " \
	379	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	380	" $filesize\0" \
	381	"consoledev=ttyS0\0" \
	382	"ramdiskaddr=2000000\0" \
	383	"ramdiskfile=8544ds/ramdisk.uboot\0" \
b24a4f62	384	"fdtaddr=1e00000\0" \
5368c55d MV	385	"fdtfile=8544ds/mpc8544ds.dtb\0" \
5368c55d MV	386	"bdev=sda3\0"
0cde4b00 JL	387
	388	#define CONFIG_NFSBOOTCOMMAND \
	389	"setenv bootargs root=/dev/nfs rw " \
	390	"nfsroot=$serverip:$rootpath " \
	391	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	392	"console=$consoledev,$baudrate $othbootargs;" \
	393	"tftp $loadaddr $bootfile;" \
50c03c8c KG	394	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	395	"bootm $loadaddr - $fdtaddr"
0cde4b00	396
837f1ba0	397	#define CONFIG_RAMBOOTCOMMAND \
0cde4b00 JL	398	"setenv bootargs root=/dev/ram rw " \
	399	"console=$consoledev,$baudrate $othbootargs;" \
	400	"tftp $ramdiskaddr $ramdiskfile;" \
	401	"tftp $loadaddr $bootfile;" \
50c03c8c KG	402	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	403	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0cde4b00	404
837f1ba0 ES	405	#define CONFIG_BOOTCOMMAND \
837f1ba0 ES	406	"setenv bootargs root=/dev/$bdev rw " \
0cde4b00 JL	407	"console=$consoledev,$baudrate $othbootargs;" \
0cde4b00 JL	408	"tftp $loadaddr $bootfile;" \
50c03c8c KG	409	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	410	"bootm $loadaddr - $fdtaddr"
0cde4b00 JL	411
0cde4b00 JL	412	#endif /* __CONFIG_H */