[people/ms/u-boot.git] / include / configs / MPC8555CDS.h

/*
 * Copyright 2004 Freescale Semiconductor.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8555cds board configuration file
 *
 * Please refer to doc/README.mpc85xxcds for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41 */
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_MPC8555		1	/* MPC8555 specific */
#define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */

#define CONFIG_PCI
#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

/*
 * When initializing flash, if we cannot find the manufacturer ID,
 * assume this is the AMD flash associated with the CDS board.
 * This allows booting from a promjet.
 */
#define CONFIG_ASSUME_AMD_FLASH

#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE		    	    /* toggle L2 cache 	*/
#define CONFIG_BTB			    /* toggle branch predition */
#define CONFIG_ADDR_STREAMING		    /* toggle addr streaming   */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
#define CFG_MEMTEST_END		0x00400000

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */

/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

/*
 * Make sure required options are set
 */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 */

#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 8M */

#define CFG_BR0_PRELIM		0xff801001
#define CFG_BR1_PRELIM		0xff001001

#define	CFG_OR0_PRELIM		0xff806e65
#define	CFG_OR1_PRELIM		0xff806e65

#define CFG_FLASH_BANKS_LIST	{0xff800000, CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO


/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CFG_BR2_PRELIM          0xf0001861

/*
 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CFG_OR2_PRELIM		0xfc006901

#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
#define CFG_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
#define CFG_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/

/*
 * LSDMR masks
 */
#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))

#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *                  or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_RFCR16		\
				| CFG_LBC_LSDMR_PRETOACT7	\
				| CFG_LBC_LSDMR_ACTTORW7	\
				| CFG_LBC_LSDMR_BL8		\
				| CFG_LBC_LSDMR_WRC4		\
				| CFG_LBC_LSDMR_CL3		\
				| CFG_LBC_LSDMR_RFEN		\
				)

/*
 * The CADMUS registers are connected to CS3 on CDS.
 * The new memory map places CADMUS at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL       = BR[24:26] = 000
 *    Valid               = BR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT                OR[20]    = 1
 *    ACS                 OR[21:22] = 11
 *    XACS                OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA                OR[28]    = 0
 *    TRLX                OR[29]    = 1
 *    EHTR                OR[30]    = 1
 *    EAD extra time      OR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */

#define CADMUS_BASE_ADDR 0xf8000000
#define CFG_BR3_PRELIM   0xf8000801
#define CFG_OR3_PRELIM   0xfff00ff7

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END    	0x4000	    /* End of used area in RAM */

#define CFG_GBL_DATA_SIZE  	128	    /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    	(256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN	    	(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     2
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* I2C */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR	0x57
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0xe2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */

#define CFG_PCI2_MEM_BASE	0xa0000000
#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI2_IO_BASE	0xe3000000
#define CFG_PCI2_IO_PHYS	CFG_PCI2_IO_BASE
#define CFG_PCI2_IO_SIZE	0x1000000	/* 16M */


#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR      0xe0000000
    #define PCI_ENET0_MEMADDR     0xe0000000
    #define PCI_IDSEL_NUMBER      0x0c 	/*slot0->3(IDSEL)=12->15*/
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MPC85XX_TSEC1	1
#define CONFIG_MPC85XX_TSEC2	1
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define FEC_PHY_ADDR		3
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define FEC_PHYIDX		0
#define CONFIG_ETHPRIME		"MOTO ENET0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#define CFG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#if defined(CONFIG_PCI)
#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
				| CFG_CMD_PCI \
				| CFG_CMD_PING \
				| CFG_CMD_I2C \
				| CFG_CMD_MII)
#else
#define  CONFIG_COMMANDS	(CONFIG_CMD_DFL \
				| CFG_CMD_PING \
				| CFG_CMD_I2C \
				| CFG_CMD_MII)
#endif
#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CFG_LOAD_ADDR	0x2000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE	32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME  unknown
#define CONFIG_ROOTPATH  /nfsroot
#define CONFIG_BOOTFILE  your.uImage

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/

#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS1\0"                                                 \
   "ramdiskaddr=400000\0"                                               \
   "ramdiskfile=your.ramdisk.u-boot\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
03f5c550 WD	1	/*
	2	* Copyright 2004 Freescale Semiconductor.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/*
	24	* mpc8555cds board configuration file
	25	*
	26	* Please refer to doc/README.mpc85xxcds for more info.
	27	*
	28	*/
03f5c550 WD	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/* High Level Configuration Options */
	33	#define CONFIG_BOOKE 1 /* BOOKE */
	34	#define CONFIG_E500 1 /* BOOKE e500 family */
	35	#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
9c4c5ae3	36	#define CONFIG_CPM2 1 /* has CPM2 */
03f5c550 WD	37	#define CONFIG_MPC8555 1 /* MPC8555 specific */
	38	#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
	39
	40	#define CONFIG_PCI
	41	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	42	#define CONFIG_ENV_OVERWRITE
	43	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	44	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	45	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	46	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
	47
	48	/*
	49	* When initializing flash, if we cannot find the manufacturer ID,
	50	* assume this is the AMD flash associated with the CDS board.
	51	* This allows booting from a promjet.
	52	*/
	53	#define CONFIG_ASSUME_AMD_FLASH
	54
	55	#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
	56
	57	#ifndef __ASSEMBLY__
	58	extern unsigned long get_clock_freq(void);
	59	#endif
	60	#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
	61
	62	/*
	63	* These can be toggled for performance analysis, otherwise use default.
	64	*/
	65	#define CONFIG_L2_CACHE /* toggle L2 cache */
	66	#define CONFIG_BTB /* toggle branch predition */
	67	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
	68
	69	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	70
	71	#undef CFG_DRAM_TEST /* memory test, takes time */
	72	#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
	73	#define CFG_MEMTEST_END 0x00400000
	74
03f5c550 WD	75	/*
	76	* Base addresses -- Note these are effective addresses where the
	77	* actual resources get mapped (not physical addresses)
	78	*/
	79	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	80	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
	81	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
	82
03f5c550 WD	83	/*
	84	* DDR Setup
	85	*/
	86	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
	87	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	88
	89	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	90
	91	/*
	92	* Make sure required options are set
	93	*/
	94	#ifndef CONFIG_SPD_EEPROM
	95	#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
	96	#endif
	97
7202d43d JL	98	#undef CONFIG_CLOCKS_IN_MHZ
	99
	100
03f5c550	101	/*
7202d43d	102	* Local Bus Definitions
03f5c550	103	*/
7202d43d JL	104
	105	/*
	106	* FLASH on the Local Bus
	107	* Two banks, 8M each, using the CFI driver.
	108	* Boot from BR0/OR0 bank at 0xff00_0000
	109	* Alternate BR1/OR1 bank at 0xff80_0000
	110	*
	111	* BR0, BR1:
	112	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	113	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	114	* Port Size = 16 bits = BRx[19:20] = 10
	115	* Use GPCM = BRx[24:26] = 000
	116	* Valid = BRx[31] = 1
	117	*
	118	* 0 4 8 12 16 20 24 28
	119	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	120	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
	121	*
	122	* OR0, OR1:
	123	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	124	* Reserved ORx[17:18] = 11, confusion here?
	125	* CSNT = ORx[20] = 1
	126	* ACS = half cycle delay = ORx[21:22] = 11
	127	* SCY = 6 = ORx[24:27] = 0110
	128	* TRLX = use relaxed timing = ORx[29] = 1
	129	* EAD = use external address latch delay = OR[31] = 1
	130	*
	131	* 0 4 8 12 16 20 24 28
	132	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
	133	*/
	134
03f5c550 WD	135	#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
03f5c550 WD	136
7202d43d JL	137	#define CFG_BR0_PRELIM 0xff801001
7202d43d JL	138	#define CFG_BR1_PRELIM 0xff001001
03f5c550	139
7202d43d JL	140	#define CFG_OR0_PRELIM 0xff806e65
7202d43d JL	141	#define CFG_OR1_PRELIM 0xff806e65
03f5c550 WD	142
	143	#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE}
	144	#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
	145	#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
	146	#undef CFG_FLASH_CHECKSUM
	147	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	148	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	149
	150	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	151
	152	#define CFG_FLASH_CFI_DRIVER
	153	#define CFG_FLASH_CFI
	154	#define CFG_FLASH_EMPTY_INFO
	155
03f5c550 WD	156
03f5c550 WD	157	/*
7202d43d	158	* SDRAM on the Local Bus
03f5c550	159	*/
7202d43d JL	160	#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
7202d43d JL	161	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
03f5c550 WD	162
	163	/*
	164	* Base Register 2 and Option Register 2 configure SDRAM.
	165	* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
	166	*
	167	* For BR2, need:
	168	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	169	* port-size = 32-bits = BR2[19:20] = 11
	170	* no parity checking = BR2[21:22] = 00
	171	* SDRAM for MSEL = BR2[24:26] = 011
	172	* Valid = BR[31] = 1
	173	*
	174	* 0 4 8 12 16 20 24 28
	175	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	176	*
	177	* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
	178	* FIXME: the top 17 bits of BR2.
	179	*/
	180
	181	#define CFG_BR2_PRELIM 0xf0001861
	182
	183	/*
	184	* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
	185	*
	186	* For OR2, need:
	187	* 64MB mask for AM, OR2[0:7] = 1111 1100
	188	* XAM, OR2[17:18] = 11
	189	* 9 columns OR2[19-21] = 010
	190	* 13 rows OR2[23-25] = 100
	191	* EAD set for extra time OR[31] = 1
	192	*
	193	* 0 4 8 12 16 20 24 28
	194	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	195	*/
	196
	197	#define CFG_OR2_PRELIM 0xfc006901
	198
	199	#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	200	#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
	201	#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	202	#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
	203
	204	/*
	205	* LSDMR masks
	206	*/
	207	#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
	208	#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
	209	#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
	210	#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
	211	#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
	212	#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
	213	#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
	214	#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
	215	#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
	216	#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
	217
	218	#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
	219	#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
	220	#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
	221	#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
	222	#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
	223	#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
	224	#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
	225	#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
226
227	/*
228	* Common settings for all Local Bus SDRAM commands.
229	* At run time, either BSMA1516 (for CPU 1.1)
230	* or BSMA1617 (for CPU 1.0) (old)
231	* is OR'ed in too.
232	*/
233	#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
234	\| CFG_LBC_LSDMR_PRETOACT7 \
235	\| CFG_LBC_LSDMR_ACTTORW7 \
236	\| CFG_LBC_LSDMR_BL8 \
237	\| CFG_LBC_LSDMR_WRC4 \
238	\| CFG_LBC_LSDMR_CL3 \
239	\| CFG_LBC_LSDMR_RFEN \
240	)
241
242	/*
243	* The CADMUS registers are connected to CS3 on CDS.
244	* The new memory map places CADMUS at 0xf8000000.
245	*
246	* For BR3, need:
247	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
248	* port-size = 8-bits = BR[19:20] = 01
249	* no parity checking = BR[21:22] = 00
250	* GPMC for MSEL = BR[24:26] = 000
251	* Valid = BR[31] = 1
252	*
253	* 0 4 8 12 16 20 24 28
254	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
255	*
256	* For OR3, need:
257	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
258	* disable buffer ctrl OR[19] = 0
259	* CSNT OR[20] = 1
260	* ACS OR[21:22] = 11
261	* XACS OR[23] = 1
262	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
263	* SETA OR[28] = 0
264	* TRLX OR[29] = 1
265	* EHTR OR[30] = 1
266	* EAD extra time OR[31] = 1
267	*
268	* 0 4 8 12 16 20 24 28
269	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
270	*/
271
272	#define CADMUS_BASE_ADDR 0xf8000000
273	#define CFG_BR3_PRELIM 0xf8000801
274	#define CFG_OR3_PRELIM 0xfff00ff7
275
03f5c550 WD	276	#define CONFIG_L1_INIT_RAM
	277	#define CFG_INIT_RAM_LOCK 1
	278	#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
	279	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
	280
	281	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
	282	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	283	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	284
a1191902	285	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
03f5c550 WD	286	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
	287
	288	/* Serial Port */
	289	#define CONFIG_CONS_INDEX 2
	290	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	291	#define CFG_NS16550
	292	#define CFG_NS16550_SERIAL
	293	#define CFG_NS16550_REG_SIZE 1
	294	#define CFG_NS16550_CLK get_bus_freq(0)
	295
	296	#define CFG_BAUDRATE_TABLE \
	297	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	298
	299	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
	300	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
	301
	302	/* Use the HUSH parser */
	303	#define CFG_HUSH_PARSER
	304	#ifdef CFG_HUSH_PARSER
	305	#define CFG_PROMPT_HUSH_PS2 "> "
	306	#endif
	307
	308	/* I2C */
	309	#define CONFIG_HARD_I2C /* I2C with hardware support */
	310	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	311	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	312	#define CFG_I2C_EEPROM_ADDR 0x57
	313	#define CFG_I2C_SLAVE 0x7F
	314	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	315
	316	/*
	317	* General PCI
	318	* Addresses are mapped 1-1.
	319	*/
	320	#define CFG_PCI1_MEM_BASE 0x80000000
	321	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	322	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	323	#define CFG_PCI1_IO_BASE 0xe2000000
	324	#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
	325	#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
	326
	327	#define CFG_PCI2_MEM_BASE 0xa0000000
	328	#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
	329	#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
	330	#define CFG_PCI2_IO_BASE 0xe3000000
	331	#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE
	332	#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
	333
	334
	335	#if defined(CONFIG_PCI)
	336
	337	#define CONFIG_NET_MULTI
	338	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	339
	340	#undef CONFIG_EEPRO100
	341	#undef CONFIG_TULIP
	342
	343	#if !defined(CONFIG_PCI_PNP)
	344	#define PCI_ENET0_IOADDR 0xe0000000
	345	#define PCI_ENET0_MEMADDR 0xe0000000
	346	#define PCI_IDSEL_NUMBER 0x0c /slot0->3(IDSEL)=12->15/
	347	#endif
	348
	349	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
350	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
351
352	#endif /* CONFIG_PCI */
353
354
355	#if defined(CONFIG_TSEC_ENET)
356
357	#ifndef CONFIG_NET_MULTI
358	#define CONFIG_NET_MULTI 1
359	#endif
360
361	#define CONFIG_MII 1 /* MII PHY management */
362	#define CONFIG_MPC85XX_TSEC1 1
363	#define CONFIG_MPC85XX_TSEC2 1
364	#undef CONFIG_MPC85XX_FEC
365	#define TSEC1_PHY_ADDR 0
366	#define TSEC2_PHY_ADDR 1
367	#define FEC_PHY_ADDR 3
368	#define TSEC1_PHYIDX 0
369	#define TSEC2_PHYIDX 0
370	#define FEC_PHYIDX 0
371	#define CONFIG_ETHPRIME "MOTO ENET0"
372
373	#endif /* CONFIG_TSEC_ENET */
374
03f5c550 WD	375	/*
	376	* Environment
	377	*/
	378	#define CFG_ENV_IS_IN_FLASH 1
	379	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
	380	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
	381	#define CFG_ENV_SIZE 0x2000
	382
	383	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	384	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	385
	386	#if defined(CONFIG_PCI)
	387	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	388	\| CFG_CMD_PCI \
	389	\| CFG_CMD_PING \
	390	\| CFG_CMD_I2C \
	391	\| CFG_CMD_MII)
	392	#else
	393	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	394	\| CFG_CMD_PING \
	395	\| CFG_CMD_I2C \
	396	\| CFG_CMD_MII)
	397	#endif
03f5c550 WD	398	#include <cmd_confdefs.h>
	399
	400	#undef CONFIG_WATCHDOG /* watchdog disabled */
	401
	402	/*
	403	* Miscellaneous configurable options
	404	*/
	405	#define CFG_LONGHELP /* undef to save memory */
	406	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	407	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	408	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	409	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	410	#else
	411	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	412	#endif
	413	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	414	#define CFG_MAXARGS 16 /* max number of command args */
	415	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	416	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	417
	418	/*
	419	* For booting Linux, the board info and command line data
	420	* have to be in the first 8 MB of memory, since this is
	421	* the maximum mapped by the Linux kernel during initialization.
	422	*/
	423	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
	424
	425	/* Cache Configuration */
	426	#define CFG_DCACHE_SIZE 32768
	427	#define CFG_CACHELINE_SIZE 32
	428	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	429	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value/
	430	#endif
	431
	432	/*
	433	* Internal Definitions
	434	*
	435	* Boot Flags
	436	*/
	437	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	438	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	439
	440	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	441	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	442	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	443	#endif
	444
03f5c550 WD	445	/*
	446	* Environment Configuration
	447	*/
	448
	449	/* The mac addresses for all ethernet interface */
	450	#if defined(CONFIG_TSEC_ENET)
	451	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
e2ffd59b	452	#define CONFIG_HAS_ETH1
03f5c550	453	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
e2ffd59b	454	#define CONFIG_HAS_ETH2
03f5c550 WD	455	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
	456	#endif
	457
	458	#define CONFIG_IPADDR 192.168.1.253
	459
	460	#define CONFIG_HOSTNAME unknown
	461	#define CONFIG_ROOTPATH /nfsroot
	462	#define CONFIG_BOOTFILE your.uImage
	463
	464	#define CONFIG_SERVERIP 192.168.1.1
	465	#define CONFIG_GATEWAYIP 192.168.1.1
	466	#define CONFIG_NETMASK 255.255.255.0
	467
	468	#define CONFIG_LOADADDR 200000 /default location for tftp and bootm/
	469
	470	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	471	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
	472
	473	#define CONFIG_BAUDRATE 115200
	474
	475	#define CONFIG_EXTRA_ENV_SETTINGS \
	476	"netdev=eth0\0" \
	477	"consoledev=ttyS1\0" \
	478	"ramdiskaddr=400000\0" \
	479	"ramdiskfile=your.ramdisk.u-boot\0"
	480
	481	#define CONFIG_NFSBOOTCOMMAND \
	482	"setenv bootargs root=/dev/nfs rw " \
	483	"nfsroot=$serverip:$rootpath " \
	484	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	485	"console=$consoledev,$baudrate $othbootargs;" \
	486	"tftp $loadaddr $bootfile;" \
	487	"bootm $loadaddr"
	488
	489	#define CONFIG_RAMBOOTCOMMAND \
	490	"setenv bootargs root=/dev/ram rw " \
	491	"console=$consoledev,$baudrate $othbootargs;" \
	492	"tftp $ramdiskaddr $ramdiskfile;" \
	493	"tftp $loadaddr $bootfile;" \
	494	"bootm $loadaddr $ramdiskaddr"
	495
	496	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	497
03f5c550	498	#endif /* __CONFIG_H */