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42d1f039 | 1 | /* |
0ac6f8b7 | 2 | * Copyright 2004 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
0ac6f8b7 WD |
25 | /* |
26 | * mpc8560ads board configuration file | |
27 | * | |
28 | * Please refer to doc/README.mpc85xx for more info. | |
29 | * | |
30 | * Make sure you change the MAC address and other network params first, | |
31 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
42d1f039 WD |
32 | */ |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* High Level Configuration Options */ | |
0ac6f8b7 WD |
38 | #define CONFIG_BOOKE 1 /* BOOKE */ |
39 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
40 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
9c4c5ae3 | 41 | #define CONFIG_CPM2 1 /* has CPM2 */ |
0ac6f8b7 | 42 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ |
f060054d | 43 | #define CONFIG_MPC8560 1 |
0ac6f8b7 WD |
44 | |
45 | #define CONFIG_PCI | |
53677ef1 | 46 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
ccc091aa | 47 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
42d1f039 | 48 | #define CONFIG_ENV_OVERWRITE |
9aea9530 | 49 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
9aea9530 WD |
50 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
51 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
42d1f039 | 52 | |
d9b94f28 JL |
53 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ |
54 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
55 | ||
7232a272 | 56 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
42d1f039 | 57 | |
0ac6f8b7 WD |
58 | /* |
59 | * sysclk for MPC85xx | |
60 | * | |
61 | * Two valid values are: | |
62 | * 33000000 | |
63 | * 66000000 | |
64 | * | |
65 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
66 | * is likely the desired value here, so that is now the default. |
67 | * The board, however, can run at 66MHz. In any event, this value | |
68 | * must match the settings of some switches. Details can be found | |
69 | * in the README.mpc85xxads. | |
0ac6f8b7 WD |
70 | */ |
71 | ||
9aea9530 WD |
72 | #ifndef CONFIG_SYS_CLK_FREQ |
73 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
42d1f039 WD |
74 | #endif |
75 | ||
9aea9530 | 76 | |
0ac6f8b7 WD |
77 | /* |
78 | * These can be toggled for performance analysis, otherwise use default. | |
79 | */ | |
80 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
81 | #define CONFIG_BTB /* toggle branch predition */ | |
82 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
42d1f039 | 83 | |
0ac6f8b7 WD |
84 | #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
85 | ||
0ac6f8b7 | 86 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
c837dcb1 | 87 | #define CFG_MEMTEST_END 0x00400000 |
42d1f039 | 88 | |
42d1f039 WD |
89 | |
90 | /* | |
91 | * Base addresses -- Note these are effective addresses where the | |
92 | * actual resources get mapped (not physical addresses) | |
93 | */ | |
53677ef1 | 94 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
9aea9530 | 95 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
f69766e4 | 96 | #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ |
0ac6f8b7 | 97 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
42d1f039 | 98 | |
9aea9530 WD |
99 | |
100 | /* | |
101 | * DDR Setup | |
102 | */ | |
0ac6f8b7 | 103 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
42d1f039 | 104 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
9aea9530 WD |
105 | |
106 | #if defined(CONFIG_SPD_EEPROM) | |
107 | /* | |
108 | * Determine DDR configuration from I2C interface. | |
109 | */ | |
110 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
111 | ||
112 | #else | |
113 | /* | |
114 | * Manually set up DDR parameters | |
115 | */ | |
116 | #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */ | |
117 | #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
118 | #define CFG_DDR_CS0_CONFIG 0x80000002 | |
119 | #define CFG_DDR_TIMING_1 0x37344321 | |
120 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
121 | #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
122 | #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
123 | #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
124 | #endif | |
125 | ||
42d1f039 | 126 | |
0ac6f8b7 WD |
127 | /* |
128 | * SDRAM on the Local Bus | |
129 | */ | |
0ac6f8b7 | 130 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
0ac6f8b7 | 131 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
42d1f039 | 132 | |
0ac6f8b7 WD |
133 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
134 | #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 135 | |
0ac6f8b7 WD |
136 | #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
137 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
138 | #define CFG_MAX_FLASH_SECT 64 /* sectors per device */ | |
42d1f039 | 139 | #undef CFG_FLASH_CHECKSUM |
0ac6f8b7 WD |
140 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
141 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
142 | ||
53677ef1 | 143 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
42d1f039 | 144 | |
42d1f039 WD |
145 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
146 | #define CFG_RAMBOOT | |
147 | #else | |
0ac6f8b7 | 148 | #undef CFG_RAMBOOT |
42d1f039 WD |
149 | #endif |
150 | ||
cf33678e WD |
151 | #define CFG_FLASH_CFI_DRIVER |
152 | #define CFG_FLASH_CFI | |
153 | #define CFG_FLASH_EMPTY_INFO | |
0ac6f8b7 WD |
154 | |
155 | #undef CONFIG_CLOCKS_IN_MHZ | |
42d1f039 | 156 | |
42d1f039 | 157 | |
0ac6f8b7 WD |
158 | /* |
159 | * Local Bus Definitions | |
160 | */ | |
161 | ||
162 | /* | |
163 | * Base Register 2 and Option Register 2 configure SDRAM. | |
164 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. | |
165 | * | |
166 | * For BR2, need: | |
167 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
168 | * port-size = 32-bits = BR2[19:20] = 11 | |
169 | * no parity checking = BR2[21:22] = 00 | |
170 | * SDRAM for MSEL = BR2[24:26] = 011 | |
171 | * Valid = BR[31] = 1 | |
172 | * | |
173 | * 0 4 8 12 16 20 24 28 | |
174 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
175 | * | |
176 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into | |
177 | * FIXME: the top 17 bits of BR2. | |
178 | */ | |
179 | ||
180 | #define CFG_BR2_PRELIM 0xf0001861 | |
181 | ||
182 | /* | |
183 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. | |
184 | * | |
185 | * For OR2, need: | |
186 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
187 | * XAM, OR2[17:18] = 11 | |
188 | * 9 columns OR2[19-21] = 010 | |
189 | * 13 rows OR2[23-25] = 100 | |
190 | * EAD set for extra time OR[31] = 1 | |
191 | * | |
192 | * 0 4 8 12 16 20 24 28 | |
193 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
194 | */ | |
195 | ||
42d1f039 | 196 | #define CFG_OR2_PRELIM 0xfc006901 |
0ac6f8b7 WD |
197 | |
198 | #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ | |
199 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
200 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
201 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
202 | ||
203 | /* | |
204 | * LSDMR masks | |
205 | */ | |
206 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) | |
207 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | |
208 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | |
209 | #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) | |
210 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | |
211 | #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) | |
212 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) | |
213 | #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) | |
214 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) | |
215 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) | |
216 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) | |
217 | #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) | |
218 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) | |
219 | #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) | |
220 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) | |
221 | ||
222 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) | |
223 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
224 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
225 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) | |
226 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
227 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) | |
228 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
229 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) | |
230 | ||
231 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \ | |
232 | | CFG_LBC_LSDMR_RFCR5 \ | |
233 | | CFG_LBC_LSDMR_PRETOACT3 \ | |
234 | | CFG_LBC_LSDMR_ACTTORW3 \ | |
235 | | CFG_LBC_LSDMR_BL8 \ | |
236 | | CFG_LBC_LSDMR_WRC2 \ | |
237 | | CFG_LBC_LSDMR_CL3 \ | |
238 | | CFG_LBC_LSDMR_RFEN \ | |
239 | ) | |
240 | ||
241 | /* | |
242 | * SDRAM Controller configuration sequence. | |
243 | */ | |
244 | #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ | |
9aea9530 | 245 | | CFG_LBC_LSDMR_OP_PCHALL) |
0ac6f8b7 | 246 | #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 247 | | CFG_LBC_LSDMR_OP_ARFRSH) |
0ac6f8b7 | 248 | #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 249 | | CFG_LBC_LSDMR_OP_ARFRSH) |
0ac6f8b7 | 250 | #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 251 | | CFG_LBC_LSDMR_OP_MRW) |
0ac6f8b7 | 252 | #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
9aea9530 | 253 | | CFG_LBC_LSDMR_OP_NORMAL) |
0ac6f8b7 | 254 | |
42d1f039 | 255 | |
9aea9530 WD |
256 | /* |
257 | * 32KB, 8-bit wide for ADS config reg | |
258 | */ | |
259 | #define CFG_BR4_PRELIM 0xf8000801 | |
42d1f039 WD |
260 | #define CFG_OR4_PRELIM 0xffffe1f1 |
261 | #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000) | |
262 | ||
263 | #define CONFIG_L1_INIT_RAM | |
53677ef1 | 264 | #define CFG_INIT_RAM_LOCK 1 |
9aea9530 | 265 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
53677ef1 | 266 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
42d1f039 | 267 | |
53677ef1 | 268 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
42d1f039 WD |
269 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
270 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
271 | ||
53677ef1 WD |
272 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
273 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
42d1f039 WD |
274 | |
275 | /* Serial Port */ | |
0ac6f8b7 WD |
276 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
277 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
278 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
42d1f039 | 279 | |
53677ef1 | 280 | #define CONFIG_BAUDRATE 115200 |
42d1f039 WD |
281 | |
282 | #define CFG_BAUDRATE_TABLE \ | |
283 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
284 | ||
285 | /* Use the HUSH parser */ | |
286 | #define CFG_HUSH_PARSER | |
0ac6f8b7 | 287 | #ifdef CFG_HUSH_PARSER |
42d1f039 WD |
288 | #define CFG_PROMPT_HUSH_PS2 "> " |
289 | #endif | |
290 | ||
0e16387d | 291 | /* pass open firmware flat tree */ |
5ce71580 KG |
292 | #define CONFIG_OF_LIBFDT 1 |
293 | #define CONFIG_OF_BOARD_SETUP 1 | |
294 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0e16387d | 295 | |
20476726 JL |
296 | /* |
297 | * I2C | |
298 | */ | |
299 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
300 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
42d1f039 | 301 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
0ac6f8b7 | 302 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
42d1f039 | 303 | #define CFG_I2C_SLAVE 0x7F |
9aea9530 | 304 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
20476726 | 305 | #define CFG_I2C_OFFSET 0x3000 |
42d1f039 | 306 | |
0ac6f8b7 WD |
307 | /* RapidIO MMU */ |
308 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ | |
309 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
310 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
311 | ||
312 | /* | |
313 | * General PCI | |
362dd830 | 314 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 WD |
315 | */ |
316 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
317 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
318 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
362dd830 SS |
319 | #define CFG_PCI1_IO_BASE 0x00000000 |
320 | #define CFG_PCI1_IO_PHYS 0xe2000000 | |
321 | #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ | |
0ac6f8b7 WD |
322 | |
323 | #if defined(CONFIG_PCI) | |
42d1f039 | 324 | |
42d1f039 | 325 | #define CONFIG_NET_MULTI |
53677ef1 | 326 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
0ac6f8b7 WD |
327 | |
328 | #undef CONFIG_EEPRO100 | |
42d1f039 | 329 | #undef CONFIG_TULIP |
0ac6f8b7 WD |
330 | |
331 | #if !defined(CONFIG_PCI_PNP) | |
332 | #define PCI_ENET0_IOADDR 0xe0000000 | |
333 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 334 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
42d1f039 | 335 | #endif |
0ac6f8b7 WD |
336 | |
337 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
338 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
339 | ||
340 | #endif /* CONFIG_PCI */ | |
341 | ||
342 | ||
ccc091aa | 343 | #ifdef CONFIG_TSEC_ENET |
0ac6f8b7 WD |
344 | |
345 | #ifndef CONFIG_NET_MULTI | |
53677ef1 | 346 | #define CONFIG_NET_MULTI 1 |
0ac6f8b7 WD |
347 | #endif |
348 | ||
ccc091aa | 349 | #ifndef CONFIG_MII |
0ac6f8b7 | 350 | #define CONFIG_MII 1 /* MII PHY management */ |
ccc091aa | 351 | #endif |
255a3577 KP |
352 | #define CONFIG_TSEC1 1 |
353 | #define CONFIG_TSEC1_NAME "TSEC0" | |
354 | #define CONFIG_TSEC2 1 | |
355 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
356 | #define TSEC1_PHY_ADDR 0 |
357 | #define TSEC2_PHY_ADDR 1 | |
358 | #define TSEC1_PHYIDX 0 | |
359 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
360 | #define TSEC1_FLAGS TSEC_GIGABIT |
361 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 JL |
362 | |
363 | /* Options are: TSEC[0-1] */ | |
364 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 | 365 | |
ccc091aa AF |
366 | #endif /* CONFIG_TSEC_ENET */ |
367 | ||
53677ef1 | 368 | #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ |
0ac6f8b7 | 369 | |
53677ef1 | 370 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
0ac6f8b7 WD |
371 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
372 | ||
373 | #if (CONFIG_ETHER_INDEX == 2) | |
42d1f039 WD |
374 | /* |
375 | * - Rx-CLK is CLK13 | |
376 | * - Tx-CLK is CLK14 | |
377 | * - Select bus for bd/buffers | |
378 | * - Full duplex | |
379 | */ | |
0ac6f8b7 WD |
380 | #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
381 | #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
382 | #define CFG_CPMFCR_RAMTYPE 0 | |
383 | #define CFG_FCC_PSMR (FCC_PSMR_FDE) | |
42d1f039 | 384 | #define FETH2_RST 0x01 |
0ac6f8b7 | 385 | #elif (CONFIG_ETHER_INDEX == 3) |
42d1f039 WD |
386 | /* need more definitions here for FE3 */ |
387 | #define FETH3_RST 0x80 | |
53677ef1 | 388 | #endif /* CONFIG_ETHER_INDEX */ |
0ac6f8b7 | 389 | |
ccc091aa AF |
390 | #ifndef CONFIG_MII |
391 | #define CONFIG_MII 1 /* MII PHY management */ | |
392 | #endif | |
393 | ||
0ac6f8b7 WD |
394 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
395 | ||
42d1f039 WD |
396 | /* |
397 | * GPIO pins used for bit-banged MII communications | |
398 | */ | |
399 | #define MDIO_PORT 2 /* Port C */ | |
400 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) | |
401 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
402 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
403 | ||
404 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
405 | else iop->pdat &= ~0x00400000 | |
406 | ||
407 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
408 | else iop->pdat &= ~0x00200000 | |
409 | ||
410 | #define MIIDELAY udelay(1) | |
0ac6f8b7 | 411 | |
42d1f039 WD |
412 | #endif |
413 | ||
0ac6f8b7 WD |
414 | |
415 | /* | |
416 | * Environment | |
417 | */ | |
42d1f039 | 418 | #ifndef CFG_RAMBOOT |
42d1f039 WD |
419 | #define CFG_ENV_IS_IN_FLASH 1 |
420 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
0ac6f8b7 | 421 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
42d1f039 WD |
422 | #define CFG_ENV_SIZE 0x2000 |
423 | #else | |
9aea9530 WD |
424 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ |
425 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
426 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
427 | #define CFG_ENV_SIZE 0x2000 | |
42d1f039 WD |
428 | #endif |
429 | ||
0ac6f8b7 WD |
430 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
431 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
42d1f039 | 432 | |
659e2f67 JL |
433 | /* |
434 | * BOOTP options | |
435 | */ | |
436 | #define CONFIG_BOOTP_BOOTFILESIZE | |
437 | #define CONFIG_BOOTP_BOOTPATH | |
438 | #define CONFIG_BOOTP_GATEWAY | |
439 | #define CONFIG_BOOTP_HOSTNAME | |
440 | ||
441 | ||
2835e518 JL |
442 | /* |
443 | * Command line configuration. | |
444 | */ | |
445 | #include <config_cmd_default.h> | |
446 | ||
447 | #define CONFIG_CMD_PING | |
448 | #define CONFIG_CMD_I2C | |
82ac8c97 | 449 | #define CONFIG_CMD_ELF |
2835e518 JL |
450 | |
451 | #if defined(CONFIG_PCI) | |
452 | #define CONFIG_CMD_PCI | |
453 | #endif | |
454 | ||
455 | #if defined(CONFIG_ETHER_ON_FCC) | |
456 | #define CONFIG_CMD_MII | |
457 | #endif | |
458 | ||
9aea9530 | 459 | #if defined(CFG_RAMBOOT) |
2835e518 JL |
460 | #undef CONFIG_CMD_ENV |
461 | #undef CONFIG_CMD_LOADS | |
42d1f039 | 462 | #endif |
0ac6f8b7 | 463 | |
42d1f039 | 464 | |
0ac6f8b7 | 465 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
466 | |
467 | /* | |
468 | * Miscellaneous configurable options | |
469 | */ | |
0ac6f8b7 | 470 | #define CFG_LONGHELP /* undef to save memory */ |
22abb2d2 | 471 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
0ac6f8b7 WD |
472 | #define CFG_LOAD_ADDR 0x1000000 /* default load address */ |
473 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
474 | ||
2835e518 | 475 | #if defined(CONFIG_CMD_KGDB) |
0ac6f8b7 | 476 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 477 | #else |
0ac6f8b7 | 478 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 479 | #endif |
0ac6f8b7 | 480 | |
42d1f039 | 481 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
0ac6f8b7 WD |
482 | #define CFG_MAXARGS 16 /* max number of command args */ |
483 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
484 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
42d1f039 WD |
485 | |
486 | /* | |
487 | * For booting Linux, the board info and command line data | |
488 | * have to be in the first 8 MB of memory, since this is | |
489 | * the maximum mapped by the Linux kernel during initialization. | |
490 | */ | |
0ac6f8b7 | 491 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
42d1f039 | 492 | |
42d1f039 WD |
493 | /* |
494 | * Internal Definitions | |
495 | * | |
496 | * Boot Flags | |
497 | */ | |
498 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
0ac6f8b7 | 499 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
42d1f039 | 500 | |
2835e518 | 501 | #if defined(CONFIG_CMD_KGDB) |
42d1f039 WD |
502 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
503 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
504 | #endif | |
505 | ||
9aea9530 WD |
506 | |
507 | /* | |
508 | * Environment Configuration | |
509 | */ | |
510 | ||
0ac6f8b7 | 511 | /* The mac addresses for all ethernet interface */ |
42d1f039 | 512 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
10327dc5 | 513 | #define CONFIG_HAS_ETH0 |
0ac6f8b7 | 514 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
e2ffd59b | 515 | #define CONFIG_HAS_ETH1 |
0ac6f8b7 | 516 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
e2ffd59b | 517 | #define CONFIG_HAS_ETH2 |
0ac6f8b7 | 518 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
5ce71580 KG |
519 | #define CONFIG_HAS_ETH3 |
520 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
42d1f039 WD |
521 | #endif |
522 | ||
0ac6f8b7 WD |
523 | #define CONFIG_IPADDR 192.168.1.253 |
524 | ||
525 | #define CONFIG_HOSTNAME unknown | |
526 | #define CONFIG_ROOTPATH /nfsroot | |
527 | #define CONFIG_BOOTFILE your.uImage | |
528 | ||
529 | #define CONFIG_SERVERIP 192.168.1.1 | |
530 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
531 | #define CONFIG_NETMASK 255.255.255.0 | |
532 | ||
533 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
534 | ||
9aea9530 | 535 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
0ac6f8b7 WD |
536 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
537 | ||
538 | #define CONFIG_BAUDRATE 115200 | |
539 | ||
9aea9530 | 540 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
6b44a44e AF |
541 | "netdev=eth0\0" \ |
542 | "consoledev=ttyCPM\0" \ | |
543 | "ramdiskaddr=1000000\0" \ | |
544 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
545 | "fdtaddr=400000\0" \ | |
546 | "fdtfile=mpc8560ads.dtb\0" | |
0ac6f8b7 | 547 | |
9aea9530 | 548 | #define CONFIG_NFSBOOTCOMMAND \ |
6b44a44e AF |
549 | "setenv bootargs root=/dev/nfs rw " \ |
550 | "nfsroot=$serverip:$rootpath " \ | |
551 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
552 | "console=$consoledev,$baudrate $othbootargs;" \ | |
553 | "tftp $loadaddr $bootfile;" \ | |
554 | "tftp $fdtaddr $fdtfile;" \ | |
555 | "bootm $loadaddr - $fdtaddr" | |
0ac6f8b7 WD |
556 | |
557 | #define CONFIG_RAMBOOTCOMMAND \ | |
6b44a44e AF |
558 | "setenv bootargs root=/dev/ram rw " \ |
559 | "console=$consoledev,$baudrate $othbootargs;" \ | |
560 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
561 | "tftp $loadaddr $bootfile;" \ | |
562 | "tftp $fdtaddr $fdtfile;" \ | |
563 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
0ac6f8b7 WD |
564 | |
565 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
566 | |
567 | #endif /* __CONFIG_H */ |