[people/ms/u-boot.git] / include / configs / MPC8560ADS.h

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8560ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */

#define CONFIG_PCI
#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef


/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest region */
#define CFG_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */


/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#if defined(CONFIG_SPD_EEPROM)
    /*
     * Determine DDR configuration from I2C interface.
     */
    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

#else
    /*
     * Manually set up DDR parameters
     */
    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
    #define CFG_DDR_CS0_CONFIG	0x80000002
    #define CFG_DDR_TIMING_1	0x37344321
    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
#endif


/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef  CFG_RAMBOOT
#endif

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CFG_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CFG_OR2_PRELIM		0xfc006901

#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

/*
 * LSDMR masks
 */
#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))

#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))

#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_BSMA1516	\
				| CFG_LBC_LSDMR_RFCR5		\
				| CFG_LBC_LSDMR_PRETOACT3	\
				| CFG_LBC_LSDMR_ACTTORW3	\
				| CFG_LBC_LSDMR_BL8		\
				| CFG_LBC_LSDMR_WRC2		\
				| CFG_LBC_LSDMR_CL3		\
				| CFG_LBC_LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_NORMAL)


/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CFG_BR4_PRELIM          0xf8000801
#define CFG_OR4_PRELIM		0xffffe1f1
#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
#undef  CONFIG_CONS_NONE	/* define if console on something else */
#define CONFIG_CONS_INDEX       1  /* which serial channel for console */

#define CONFIG_BAUDRATE	 	115200

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* I2C */
#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */

/* RapidIO MMU */
#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0xe2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MPC85XX_TSEC1	1
#define CONFIG_MPC85XX_TSEC1_NAME	"TSEC0"
#define CONFIG_MPC85XX_TSEC2	1
#define CONFIG_MPC85XX_TSEC2_NAME	"TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

#define CONFIG_ETHER_ON_FCC	/* define if ether on FCC   */
#undef  CONFIG_ETHER_NONE	/* define if ether on something else */
#define CONFIG_ETHER_INDEX      2       /* which channel for ether */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CFG_CPMFCR_RAMTYPE    0
  #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif  				/* CONFIG_ETHER_INDEX */

#define CONFIG_MII			/* MII PHY management */
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */

/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	2		/* Port C */
#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
#define MDIO_READ	((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

#define MIIDELAY	udelay(1)

#endif


/*
 * Environment
 */
#ifndef CFG_RAMBOOT
  #define CFG_ENV_IS_IN_FLASH	1
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CFG_ENV_SIZE		0x2000
#else
  #define CFG_NO_FLASH		1	/* Flash is not usable now */
  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
  #define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#if defined(CFG_RAMBOOT)
  #if defined(CONFIG_PCI)
    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
				 | CFG_CMD_PING		\
				 | CFG_CMD_PCI		\
				 | CFG_CMD_I2C)		\
				&			\
				 ~(CFG_CMD_ENV		\
				  | CFG_CMD_LOADS))
  #elif defined(CONFIG_TSEC_ENET)
    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
				| CFG_CMD_PING		\
				| CFG_CMD_I2C)		\
				& ~(CFG_CMD_ENV))
  #elif defined(CONFIG_ETHER_ON_FCC)
    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
				 | CFG_CMD_MII		\
				 | CFG_CMD_PING		\
				 | CFG_CMD_I2C)		\
				& ~(CFG_CMD_ENV))
  #endif
#else
  #if defined(CONFIG_PCI)
    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
				| CFG_CMD_PCI		\
				| CFG_CMD_PING		\
				| CFG_CMD_I2C)
  #elif defined(CONFIG_TSEC_ENET)
    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
				| CFG_CMD_PING		\
				| CFG_CMD_I2C)
  #elif defined(CONFIG_ETHER_ON_FCC)
    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
				| CFG_CMD_MII		\
				| CFG_CMD_PING		\
				| CFG_CMD_I2C)
  #endif
#endif

#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CFG_LOAD_ADDR	0x1000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_BOOTFILE		your.uImage

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=400000\0"						\
   "ramdiskfile=your.ramdisk.u-boot\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
0ac6f8b7 WD	25	/*
	26	* mpc8560ads board configuration file
	27	*
	28	* Please refer to doc/README.mpc85xx for more info.
	29	*
	30	* Make sure you change the MAC address and other network params first,
	31	* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
42d1f039 WD	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/* High Level Configuration Options */
0ac6f8b7 WD	38	#define CONFIG_BOOKE 1 /* BOOKE */
	39	#define CONFIG_E500 1 /* BOOKE e500 family */
	40	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
9c4c5ae3	41	#define CONFIG_CPM2 1 /* has CPM2 */
0ac6f8b7 WD	42	#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
	43
	44	#define CONFIG_PCI
	45	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	46	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
42d1f039	47	#define CONFIG_ENV_OVERWRITE
9aea9530	48	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
9aea9530 WD	49	#define CONFIG_DDR_DLL /* possible DLL fix needed */
9aea9530 WD	50	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
42d1f039	51
d9b94f28 JL	52	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	53	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	54
42d1f039	55
0ac6f8b7 WD	56	/*
	57	* sysclk for MPC85xx
	58	*
	59	* Two valid values are:
	60	* 33000000
	61	* 66000000
	62	*
	63	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	64	* is likely the desired value here, so that is now the default.
	65	* The board, however, can run at 66MHz. In any event, this value
	66	* must match the settings of some switches. Details can be found
	67	* in the README.mpc85xxads.
0ac6f8b7 WD	68	*/
0ac6f8b7 WD	69
9aea9530 WD	70	#ifndef CONFIG_SYS_CLK_FREQ
9aea9530 WD	71	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	72	#endif
42d1f039 WD	73
9aea9530	74
0ac6f8b7 WD	75	/*
	76	* These can be toggled for performance analysis, otherwise use default.
	77	*/
	78	#define CONFIG_L2_CACHE /* toggle L2 cache */
	79	#define CONFIG_BTB /* toggle branch predition */
	80	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
42d1f039	81
0ac6f8b7	82	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
42d1f039	83
0ac6f8b7 WD	84	#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
0ac6f8b7 WD	85
9aea9530	86	#undef CFG_DRAM_TEST /* memory test, takes time */
0ac6f8b7	87	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
c837dcb1	88	#define CFG_MEMTEST_END 0x00400000
42d1f039	89
42d1f039 WD	90
	91	/*
	92	* Base addresses -- Note these are effective addresses where the
	93	* actual resources get mapped (not physical addresses)
	94	*/
0ac6f8b7	95	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
9aea9530	96	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
0ac6f8b7	97	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
42d1f039	98
9aea9530 WD	99
	100	/*
	101	* DDR Setup
	102	*/
0ac6f8b7	103	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
42d1f039	104	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
9aea9530 WD	105
	106	#if defined(CONFIG_SPD_EEPROM)
	107	/*
	108	* Determine DDR configuration from I2C interface.
	109	*/
	110	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	111
	112	#else
	113	/*
	114	* Manually set up DDR parameters
	115	*/
	116	#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
	117	#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	118	#define CFG_DDR_CS0_CONFIG 0x80000002
	119	#define CFG_DDR_TIMING_1 0x37344321
	120	#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	121	#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	122	#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	123	#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
	124	#endif
	125
42d1f039	126
0ac6f8b7 WD	127	/*
	128	* SDRAM on the Local Bus
	129	*/
0ac6f8b7	130	#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
0ac6f8b7	131	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	132
0ac6f8b7 WD	133	#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
0ac6f8b7 WD	134	#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	135
0ac6f8b7 WD	136	#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	137	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	138	#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
42d1f039	139	#undef CFG_FLASH_CHECKSUM
0ac6f8b7 WD	140	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	141	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	142
	143	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
42d1f039	144
42d1f039 WD	145	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	146	#define CFG_RAMBOOT
	147	#else
0ac6f8b7	148	#undef CFG_RAMBOOT
42d1f039 WD	149	#endif
42d1f039 WD	150
cf33678e WD	151	#define CFG_FLASH_CFI_DRIVER
	152	#define CFG_FLASH_CFI
	153	#define CFG_FLASH_EMPTY_INFO
0ac6f8b7 WD	154
0ac6f8b7 WD	155	#undef CONFIG_CLOCKS_IN_MHZ
42d1f039	156
42d1f039	157
0ac6f8b7 WD	158	/*
	159	* Local Bus Definitions
	160	*/
	161
	162	/*
	163	* Base Register 2 and Option Register 2 configure SDRAM.
	164	* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
	165	*
	166	* For BR2, need:
	167	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	168	* port-size = 32-bits = BR2[19:20] = 11
	169	* no parity checking = BR2[21:22] = 00
	170	* SDRAM for MSEL = BR2[24:26] = 011
	171	* Valid = BR[31] = 1
	172	*
	173	* 0 4 8 12 16 20 24 28
	174	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	175	*
	176	* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
	177	* FIXME: the top 17 bits of BR2.
	178	*/
	179
	180	#define CFG_BR2_PRELIM 0xf0001861
	181
	182	/*
	183	* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
	184	*
	185	* For OR2, need:
	186	* 64MB mask for AM, OR2[0:7] = 1111 1100
	187	* XAM, OR2[17:18] = 11
	188	* 9 columns OR2[19-21] = 010
	189	* 13 rows OR2[23-25] = 100
	190	* EAD set for extra time OR[31] = 1
	191	*
	192	* 0 4 8 12 16 20 24 28
	193	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	194	*/
	195
42d1f039	196	#define CFG_OR2_PRELIM 0xfc006901
0ac6f8b7 WD	197
	198	#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	199	#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
	200	#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	201	#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
	202
	203	/*
	204	* LSDMR masks
	205	*/
	206	#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
	207	#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
	208	#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
	209	#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
	210	#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
	211	#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
	212	#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
	213	#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
	214	#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
	215	#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
	216	#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
	217	#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
	218	#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
	219	#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
	220	#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
	221
	222	#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
	223	#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
	224	#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
	225	#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
	226	#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
	227	#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
	228	#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
	229	#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
	230
	231	#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
	232	\| CFG_LBC_LSDMR_RFCR5 \
	233	\| CFG_LBC_LSDMR_PRETOACT3 \
	234	\| CFG_LBC_LSDMR_ACTTORW3 \
	235	\| CFG_LBC_LSDMR_BL8 \
	236	\| CFG_LBC_LSDMR_WRC2 \
	237	\| CFG_LBC_LSDMR_CL3 \
	238	\| CFG_LBC_LSDMR_RFEN \
	239	)
	240
	241	/*
	242	* SDRAM Controller configuration sequence.
	243	*/
	244	#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
9aea9530	245	\| CFG_LBC_LSDMR_OP_PCHALL)
0ac6f8b7	246	#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
9aea9530	247	\| CFG_LBC_LSDMR_OP_ARFRSH)
0ac6f8b7	248	#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
9aea9530	249	\| CFG_LBC_LSDMR_OP_ARFRSH)
0ac6f8b7	250	#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
9aea9530	251	\| CFG_LBC_LSDMR_OP_MRW)
0ac6f8b7	252	#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
9aea9530	253	\| CFG_LBC_LSDMR_OP_NORMAL)
0ac6f8b7	254
42d1f039	255
9aea9530 WD	256	/*
	257	* 32KB, 8-bit wide for ADS config reg
	258	*/
	259	#define CFG_BR4_PRELIM 0xf8000801
42d1f039 WD	260	#define CFG_OR4_PRELIM 0xffffe1f1
	261	#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
	262
	263	#define CONFIG_L1_INIT_RAM
0ac6f8b7	264	#define CFG_INIT_RAM_LOCK 1
9aea9530	265	#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
0ac6f8b7	266	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
42d1f039	267
0ac6f8b7	268	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
42d1f039 WD	269	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	270	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	271
a1191902	272	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
0ac6f8b7	273	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	274
42d1f039 WD	275	/* Serial Port */
0ac6f8b7 WD	276	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	277	#undef CONFIG_CONS_NONE /* define if console on something else */
	278	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
42d1f039	279
0ac6f8b7	280	#define CONFIG_BAUDRATE 115200
42d1f039 WD	281
	282	#define CFG_BAUDRATE_TABLE \
	283	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	284
	285	/* Use the HUSH parser */
	286	#define CFG_HUSH_PARSER
0ac6f8b7	287	#ifdef CFG_HUSH_PARSER
42d1f039 WD	288	#define CFG_PROMPT_HUSH_PS2 "> "
	289	#endif
	290
	291	/* I2C */
9aea9530	292	#define CONFIG_HARD_I2C /* I2C with hardware support*/
42d1f039	293	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
0ac6f8b7	294	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
42d1f039	295	#define CFG_I2C_SLAVE 0x7F
9aea9530	296	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
42d1f039	297
0ac6f8b7 WD	298	/* RapidIO MMU */
	299	#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
	300	#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
	301	#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
	302
	303	/*
	304	* General PCI
	305	* Addresses are mapped 1-1.
	306	*/
	307	#define CFG_PCI1_MEM_BASE 0x80000000
	308	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	309	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	310	#define CFG_PCI1_IO_BASE 0xe2000000
	311	#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
	312	#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
	313
	314	#if defined(CONFIG_PCI)
42d1f039	315
42d1f039	316	#define CONFIG_NET_MULTI
9aea9530	317	#define CONFIG_PCI_PNP /* do pci plug-and-play */
0ac6f8b7 WD	318
0ac6f8b7 WD	319	#undef CONFIG_EEPRO100
42d1f039	320	#undef CONFIG_TULIP
0ac6f8b7 WD	321
	322	#if !defined(CONFIG_PCI_PNP)
	323	#define PCI_ENET0_IOADDR 0xe0000000
	324	#define PCI_ENET0_MEMADDR 0xe0000000
	325	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	326	#endif
0ac6f8b7 WD	327
	328	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	329	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	330
	331	#endif /* CONFIG_PCI */
	332
	333
	334	#if defined(CONFIG_TSEC_ENET)
	335
	336	#ifndef CONFIG_NET_MULTI
	337	#define CONFIG_NET_MULTI 1
	338	#endif
	339
	340	#define CONFIG_MII 1 /* MII PHY management */
	341	#define CONFIG_MPC85XX_TSEC1 1
d9b94f28	342	#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
0ac6f8b7	343	#define CONFIG_MPC85XX_TSEC2 1
d9b94f28	344	#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	345	#undef CONFIG_MPC85XX_FEC
	346	#define TSEC1_PHY_ADDR 0
	347	#define TSEC2_PHY_ADDR 1
	348	#define TSEC1_PHYIDX 0
	349	#define TSEC2_PHYIDX 0
d9b94f28 JL	350
	351	/* Options are: TSEC[0-1] */
	352	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7	353
42d1f039	354	#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
0ac6f8b7 WD	355
	356	#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
	357	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	358	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
	359
	360	#if (CONFIG_ETHER_INDEX == 2)
42d1f039 WD	361	/*
	362	* - Rx-CLK is CLK13
	363	* - Tx-CLK is CLK14
	364	* - Select bus for bd/buffers
	365	* - Full duplex
	366	*/
0ac6f8b7 WD	367	#define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	368	#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	369	#define CFG_CPMFCR_RAMTYPE 0
	370	#define CFG_FCC_PSMR (FCC_PSMR_FDE)
42d1f039	371	#define FETH2_RST 0x01
0ac6f8b7	372	#elif (CONFIG_ETHER_INDEX == 3)
42d1f039 WD	373	/* need more definitions here for FE3 */
42d1f039 WD	374	#define FETH3_RST 0x80
0ac6f8b7 WD	375	#endif /* CONFIG_ETHER_INDEX */
0ac6f8b7 WD	376
42d1f039	377	#define CONFIG_MII /* MII PHY management */
0ac6f8b7 WD	378	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
0ac6f8b7 WD	379
42d1f039 WD	380	/*
	381	* GPIO pins used for bit-banged MII communications
	382	*/
	383	#define MDIO_PORT 2 /* Port C */
	384	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	385	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	386	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	387
	388	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	389	else iop->pdat &= ~0x00400000
	390
	391	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	392	else iop->pdat &= ~0x00200000
	393
	394	#define MIIDELAY udelay(1)
0ac6f8b7	395
42d1f039 WD	396	#endif
42d1f039 WD	397
0ac6f8b7 WD	398
	399	/*
	400	* Environment
	401	*/
42d1f039	402	#ifndef CFG_RAMBOOT
42d1f039 WD	403	#define CFG_ENV_IS_IN_FLASH 1
42d1f039 WD	404	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
0ac6f8b7	405	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
42d1f039 WD	406	#define CFG_ENV_SIZE 0x2000
42d1f039 WD	407	#else
9aea9530 WD	408	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	409	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	410	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	411	#define CFG_ENV_SIZE 0x2000
42d1f039 WD	412	#endif
42d1f039 WD	413
0ac6f8b7 WD	414	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
0ac6f8b7 WD	415	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	416
9aea9530	417	#if defined(CFG_RAMBOOT)
42d1f039	418	#if defined(CONFIG_PCI)
0ac6f8b7	419	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
0ac6f8b7	420	\| CFG_CMD_PING \
9aea9530	421	\| CFG_CMD_PCI \
0ac6f8b7 WD	422	\| CFG_CMD_I2C) \
0ac6f8b7 WD	423	& \
9aea9530	424	~(CFG_CMD_ENV \
0ac6f8b7	425	\| CFG_CMD_LOADS))
42d1f039	426	#elif defined(CONFIG_TSEC_ENET)
0ac6f8b7 WD	427	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
	428	\| CFG_CMD_PING \
	429	\| CFG_CMD_I2C) \
	430	& ~(CFG_CMD_ENV))
42d1f039	431	#elif defined(CONFIG_ETHER_ON_FCC)
0ac6f8b7 WD	432	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
	433	\| CFG_CMD_MII \
	434	\| CFG_CMD_PING \
	435	\| CFG_CMD_I2C) \
	436	& ~(CFG_CMD_ENV))
42d1f039 WD	437	#endif
	438	#else
	439	#if defined(CONFIG_PCI)
0ac6f8b7 WD	440	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	441	\| CFG_CMD_PCI \
	442	\| CFG_CMD_PING \
	443	\| CFG_CMD_I2C)
42d1f039	444	#elif defined(CONFIG_TSEC_ENET)
0ac6f8b7 WD	445	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	446	\| CFG_CMD_PING \
	447	\| CFG_CMD_I2C)
42d1f039	448	#elif defined(CONFIG_ETHER_ON_FCC)
0ac6f8b7 WD	449	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	450	\| CFG_CMD_MII \
	451	\| CFG_CMD_PING \
	452	\| CFG_CMD_I2C)
42d1f039 WD	453	#endif
42d1f039 WD	454	#endif
0ac6f8b7	455
42d1f039 WD	456	#include <cmd_confdefs.h>
42d1f039 WD	457
0ac6f8b7	458	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	459
	460	/*
	461	* Miscellaneous configurable options
	462	*/
0ac6f8b7 WD	463	#define CFG_LONGHELP /* undef to save memory */
	464	#define CFG_LOAD_ADDR 0x1000000 /* default load address */
	465	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	466
42d1f039	467	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
0ac6f8b7	468	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	469	#else
0ac6f8b7	470	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	471	#endif
0ac6f8b7	472
42d1f039	473	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
0ac6f8b7 WD	474	#define CFG_MAXARGS 16 /* max number of command args */
	475	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	476	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
42d1f039 WD	477
	478	/*
	479	* For booting Linux, the board info and command line data
	480	* have to be in the first 8 MB of memory, since this is
	481	* the maximum mapped by the Linux kernel during initialization.
	482	*/
0ac6f8b7	483	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
42d1f039 WD	484
	485	/* Cache Configuration */
	486	#define CFG_DCACHE_SIZE 32768
	487	#define CFG_CACHELINE_SIZE 32
	488	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
0ac6f8b7	489	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value/
42d1f039 WD	490	#endif
	491
	492	/*
	493	* Internal Definitions
	494	*
	495	* Boot Flags
	496	*/
	497	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
0ac6f8b7	498	#define BOOTFLAG_WARM 0x02 /* Software reboot */
42d1f039 WD	499
	500	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	501	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	502	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	503	#endif
	504
9aea9530 WD	505
	506	/*
	507	* Environment Configuration
	508	*/
	509
0ac6f8b7	510	/* The mac addresses for all ethernet interface */
42d1f039	511	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
0ac6f8b7	512	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
e2ffd59b	513	#define CONFIG_HAS_ETH1
0ac6f8b7	514	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
e2ffd59b	515	#define CONFIG_HAS_ETH2
0ac6f8b7	516	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
42d1f039 WD	517	#endif
42d1f039 WD	518
0ac6f8b7 WD	519	#define CONFIG_IPADDR 192.168.1.253
	520
	521	#define CONFIG_HOSTNAME unknown
	522	#define CONFIG_ROOTPATH /nfsroot
	523	#define CONFIG_BOOTFILE your.uImage
	524
	525	#define CONFIG_SERVERIP 192.168.1.1
	526	#define CONFIG_GATEWAYIP 192.168.1.1
	527	#define CONFIG_NETMASK 255.255.255.0
	528
	529	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	530
9aea9530	531	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
0ac6f8b7 WD	532	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	533
	534	#define CONFIG_BAUDRATE 115200
	535
9aea9530	536	#define CONFIG_EXTRA_ENV_SETTINGS \
0ac6f8b7 WD	537	"netdev=eth0\0" \
	538	"consoledev=ttyS0\0" \
	539	"ramdiskaddr=400000\0" \
	540	"ramdiskfile=your.ramdisk.u-boot\0"
	541
9aea9530	542	#define CONFIG_NFSBOOTCOMMAND \
0ac6f8b7 WD	543	"setenv bootargs root=/dev/nfs rw " \
	544	"nfsroot=$serverip:$rootpath " \
	545	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	546	"console=$consoledev,$baudrate $othbootargs;" \
	547	"tftp $loadaddr $bootfile;" \
	548	"bootm $loadaddr"
	549
	550	#define CONFIG_RAMBOOTCOMMAND \
	551	"setenv bootargs root=/dev/ram rw " \
	552	"console=$consoledev,$baudrate $othbootargs;" \
	553	"tftp $ramdiskaddr $ramdiskfile;" \
	554	"tftp $loadaddr $bootfile;" \
	555	"bootm $loadaddr $ramdiskaddr"
	556
	557	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	558
42d1f039 WD	559	#endif /* __CONFIG_H */