[thirdparty/u-boot.git] / include / configs / MPC8568MDS.h

/*
 * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8568mds board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */

#define CONFIG_PCI1		1	/* PCI controller */
#define CONFIG_PCIE1		1	/* PCIE controller */
#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_QE			/* Enable QE */
#define CONFIG_ENV_OVERWRITE

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
#define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
#define CONFIG_BTB				/* toggle branch predition */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */

#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 */
#define CONFIG_SYS_BCSR_BASE		0xf8000000

#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */

/*Chip select 0 - Flash*/
#define CONFIG_SYS_BR0_PRELIM		0xfe001001
#define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7

/*Chip slelect 1 - BCSR*/
#define CONFIG_SYS_BR1_PRELIM		0xf8000801
#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7

/*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

/*
 * SDRAM on the LocalBus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */

/*Chip select 2 - SDRAM*/
#define CONFIG_SYS_BR2_PRELIM      0xf0001861
#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *                  or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The bcsr registers are connected to CS3 on MDS.
 * The new memory map places bcsr at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL       = BR[24:26] = 000
 *    Valid               = BR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT                OR[20]    = 1
 *    ACS                 OR[21:22] = 11
 *    XACS                OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA                OR[28]    = 0
 *    TRLX                OR[29]    = 1
 *    EHTR                OR[30]    = 1
 *    EAD extra time      OR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */
#define CONFIG_SYS_BCSR (0xf8000000)

/*Chip slelect 4 - PIB*/
#define CONFIG_SYS_BR4_PRELIM   0xf8008801
#define CONFIG_SYS_OR4_PRELIM   0xffffe9f7

/*Chip select 5 - PIB*/
#define CONFIG_SYS_BR5_PRELIM	 0xf8010801
#define CONFIG_SYS_OR5_PRELIM	 0xffff69f7

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52

/*
 * General PCI
 * Memory Addresses are mapped 1-1. I/O is mapped from 0
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */

#define CONFIG_SYS_PCIE1_NAME		"Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */

#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */

#ifdef CONFIG_QE
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#ifndef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME         "UEC0"
#endif
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_eTSEC_MDIO_BUS

#ifdef CONFIG_eTSEC_MDIO_BUS
#define CONFIG_MIIM_ADDRESS	0xE0024520
#endif

#define CONFIG_UEC_ETH1         /* GETH1 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR       7
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
#endif

#define CONFIG_UEC_ETH2         /* GETH2 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR       1
#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
#endif
#endif /* CONFIG_QE */

#if defined(CONFIG_PCI)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"

#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		3

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME  unknown
#define CONFIG_ROOTPATH  "/nfsroot"
#define CONFIG_BOOTFILE  "your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=600000\0"                                               \
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"						\
   "nfsargs=setenv bootargs root=/dev/nfs rw "				\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs\0"			\
   "ramargs=setenv bootargs root=/dev/ram rw "				\
      "console=$consoledev,$baudrate $othbootargs\0"			\

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "run nfsargs;"							\
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "run ramargs;"							\
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
67431059	1	/*
5f7bbd13	2	* Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
67431059	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
67431059 AF	5	*/
	6
	7	/*
	8	* mpc8568mds board configuration file
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
5f7bbd13 KG	13	#define CONFIG_SYS_SRIO
	14	#define CONFIG_SRIO1 /* SRIO port 1 */
	15
1563f56e HW	16	#define CONFIG_PCI1 1 /* PCI controller */
	17	#define CONFIG_PCIE1 1 /* PCIE controller */
	18	#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
842033e6	19	#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
8ff3de61	20	#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
0151cbac	21	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
b96c83d4	22	#define CONFIG_QE /* Enable QE */
67431059	23	#define CONFIG_ENV_OVERWRITE
67431059	24
67431059 AF	25	#ifndef __ASSEMBLY__
	26	extern unsigned long get_clock_freq(void);
	27	#endif /Replace a call to get_clock_freq (after it is implemented)/
	28	#define CONFIG_SYS_CLK_FREQ 66000000 /TODO: restore if wanting to read from BCSR: get_clock_freq()/ /* sysclk for MPC85xx */
	29
	30	/*
	31	* These can be toggled for performance analysis, otherwise use default.
	32	*/
53677ef1	33	#define CONFIG_L2_CACHE /* toggle L2 cache */
7a1ac419	34	#define CONFIG_BTB /* toggle branch predition */
67431059 AF	35
	36	/*
	37	* Only possible on E500 Version 2 or newer cores.
	38	*/
	39	#define CONFIG_ENABLE_36BIT_PHYS 1
	40
6d0f6bcf JCPV	41	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
6d0f6bcf JCPV	42	#define CONFIG_SYS_MEMTEST_END 0x00400000
67431059	43
e46fedfe TT	44	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	45	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
67431059	46
e6f5b35b	47	/* DDR Setup */
e6f5b35b JL	48	#undef CONFIG_FSL_DDR_INTERACTIVE
	49	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	50	#define CONFIG_DDR_SPD
9b0ad1b1	51	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
e6f5b35b JL	52
	53	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	54
6d0f6bcf JCPV	55	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	56	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
67431059	57
e6f5b35b JL	58	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
e6f5b35b JL	59	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
67431059	60
e6f5b35b JL	61	/* I2C addresses of SPD EEPROMs */
	62	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	63
	64	/* Make sure required options are set */
67431059 AF	65	#ifndef CONFIG_SPD_EEPROM
	66	#error ("CONFIG_SPD_EEPROM is required")
	67	#endif
	68
	69	#undef CONFIG_CLOCKS_IN_MHZ
	70
67431059 AF	71	/*
	72	* Local Bus Definitions
	73	*/
	74
	75	/*
	76	* FLASH on the Local Bus
	77	* Two banks, 8M each, using the CFI driver.
	78	* Boot from BR0/OR0 bank at 0xff00_0000
	79	* Alternate BR1/OR1 bank at 0xff80_0000
	80	*
	81	* BR0, BR1:
	82	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	83	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	84	* Port Size = 16 bits = BRx[19:20] = 10
	85	* Use GPCM = BRx[24:26] = 000
	86	* Valid = BRx[31] = 1
	87	*
	88	* 0 4 8 12 16 20 24 28
	89	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	90	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
	91	*
	92	* OR0, OR1:
	93	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	94	* Reserved ORx[17:18] = 11, confusion here?
	95	* CSNT = ORx[20] = 1
	96	* ACS = half cycle delay = ORx[21:22] = 11
	97	* SCY = 6 = ORx[24:27] = 0110
	98	* TRLX = use relaxed timing = ORx[29] = 1
	99	* EAD = use external address latch delay = OR[31] = 1
	100	*
	101	* 0 4 8 12 16 20 24 28
	102	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
	103	*/
6d0f6bcf	104	#define CONFIG_SYS_BCSR_BASE 0xf8000000
67431059	105
6d0f6bcf	106	#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
67431059 AF	107
67431059 AF	108	/Chip select 0 - Flash/
6d0f6bcf JCPV	109	#define CONFIG_SYS_BR0_PRELIM 0xfe001001
6d0f6bcf JCPV	110	#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
67431059 AF	111
67431059 AF	112	/Chip slelect 1 - BCSR/
6d0f6bcf JCPV	113	#define CONFIG_SYS_BR1_PRELIM 0xf8000801
6d0f6bcf JCPV	114	#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
67431059	115
6d0f6bcf JCPV	116	/#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} /
	117	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	118	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
	119	#undef CONFIG_SYS_FLASH_CHECKSUM
	120	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	121	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
67431059	122
14d0a02a	123	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
67431059	124
00b1883a	125	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	126	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	127	#define CONFIG_SYS_FLASH_EMPTY_INFO
67431059	128
67431059 AF	129	/*
	130	* SDRAM on the LocalBus
	131	*/
6d0f6bcf JCPV	132	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	133	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
67431059	134
67431059	135	/Chip select 2 - SDRAM/
6d0f6bcf JCPV	136	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
6d0f6bcf JCPV	137	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
67431059	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	140	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	141	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	142	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
67431059	143
67431059 AF	144	/*
	145	* Common settings for all Local Bus SDRAM commands.
	146	* At run time, either BSMA1516 (for CPU 1.1)
	147	* or BSMA1617 (for CPU 1.0) (old)
	148	* is OR'ed in too.
	149	*/
b0fe93ed KG	150	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	151	\| LSDMR_PRETOACT7 \
	152	\| LSDMR_ACTTORW7 \
	153	\| LSDMR_BL8 \
	154	\| LSDMR_WRC4 \
	155	\| LSDMR_CL3 \
	156	\| LSDMR_RFEN \
67431059 AF	157	)
	158
	159	/*
	160	* The bcsr registers are connected to CS3 on MDS.
	161	* The new memory map places bcsr at 0xf8000000.
	162	*
	163	* For BR3, need:
	164	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	165	* port-size = 8-bits = BR[19:20] = 01
	166	* no parity checking = BR[21:22] = 00
	167	* GPMC for MSEL = BR[24:26] = 000
	168	* Valid = BR[31] = 1
	169	*
	170	* 0 4 8 12 16 20 24 28
	171	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	172	*
	173	* For OR3, need:
	174	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
	175	* disable buffer ctrl OR[19] = 0
	176	* CSNT OR[20] = 1
	177	* ACS OR[21:22] = 11
	178	* XACS OR[23] = 1
	179	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
	180	* SETA OR[28] = 0
	181	* TRLX OR[29] = 1
	182	* EHTR OR[30] = 1
	183	* EAD extra time OR[31] = 1
	184	*
	185	* 0 4 8 12 16 20 24 28
	186	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	187	*/
6d0f6bcf	188	#define CONFIG_SYS_BCSR (0xf8000000)
67431059 AF	189
67431059 AF	190	/Chip slelect 4 - PIB/
6d0f6bcf JCPV	191	#define CONFIG_SYS_BR4_PRELIM 0xf8008801
6d0f6bcf JCPV	192	#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
67431059 AF	193
67431059 AF	194	/Chip select 5 - PIB/
6d0f6bcf JCPV	195	#define CONFIG_SYS_BR5_PRELIM 0xf8010801
6d0f6bcf JCPV	196	#define CONFIG_SYS_OR5_PRELIM 0xffff69f7
67431059	197
6d0f6bcf JCPV	198	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	199	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	200	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
67431059	201
25ddd1fb	202	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	203	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
67431059	204
6d0f6bcf	205	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
cdab5e90	206	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
67431059 AF	207
67431059 AF	208	/* Serial Port */
6d0f6bcf JCPV	209	#define CONFIG_SYS_NS16550_SERIAL
	210	#define CONFIG_SYS_NS16550_REG_SIZE 1
	211	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
67431059	212
6d0f6bcf	213	#define CONFIG_SYS_BAUDRATE_TABLE \
67431059 AF	214	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
67431059 AF	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	217	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
67431059	218
67431059 AF	219	/*
	220	* I2C
	221	*/
00f792e0 HS	222	#define CONFIG_SYS_I2C
	223	#define CONFIG_SYS_I2C_FSL
	224	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	225	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	226	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	227	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	228	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	229	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
	230	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
6d0f6bcf	231	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
67431059 AF	232
	233	/*
	234	* General PCI
	235	* Memory Addresses are mapped 1-1. I/O is mapped from 0
	236	*/
5af0fdd8	237	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	238	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	239	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	240	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	241	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	242	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	243	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
	244	#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
	245
3f6f9d76	246	#define CONFIG_SYS_PCIE1_NAME "Slot"
5af0fdd8	247	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
10795f42	248	#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
5af0fdd8	249	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
6d0f6bcf	250	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	251	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
5f91ef6a	252	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
6d0f6bcf JCPV	253	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
	254	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
	255
5f7bbd13 KG	256	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
	257	#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
	258	#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
	259	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
67431059	260
da9d4610 AF	261	#ifdef CONFIG_QE
	262	/*
	263	* QE UEC ethernet configuration
	264	*/
	265	#define CONFIG_UEC_ETH
	266	#ifndef CONFIG_TSEC_ENET
78b7a8ef	267	#define CONFIG_ETHPRIME "UEC0"
da9d4610 AF	268	#endif
	269	#define CONFIG_PHY_MODE_NEED_CHANGE
	270	#define CONFIG_eTSEC_MDIO_BUS
	271
	272	#ifdef CONFIG_eTSEC_MDIO_BUS
53677ef1	273	#define CONFIG_MIIM_ADDRESS 0xE0024520
da9d4610 AF	274	#endif
	275
	276	#define CONFIG_UEC_ETH1 /* GETH1 */
	277
	278	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	279	#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
	280	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
	281	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
	282	#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
	283	#define CONFIG_SYS_UEC1_PHY_ADDR 7
865ff856	284	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
582c55a0	285	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
da9d4610 AF	286	#endif
	287
	288	#define CONFIG_UEC_ETH2 /* GETH2 */
	289
	290	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	291	#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
	292	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
	293	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
	294	#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
	295	#define CONFIG_SYS_UEC2_PHY_ADDR 1
865ff856	296	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
582c55a0	297	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
da9d4610 AF	298	#endif
	299	#endif /* CONFIG_QE */
	300
f30ad49b	301	#if defined(CONFIG_PCI)
67431059 AF	302	#undef CONFIG_EEPRO100
	303	#undef CONFIG_TULIP
	304
	305	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	306	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
67431059 AF	307
	308	#endif /* CONFIG_PCI */
	309
da9d4610 AF	310	#if defined(CONFIG_TSEC_ENET)
da9d4610 AF	311
67431059	312	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	313	#define CONFIG_TSEC1 1
	314	#define CONFIG_TSEC1_NAME "eTSEC0"
	315	#define CONFIG_TSEC2 1
	316	#define CONFIG_TSEC2_NAME "eTSEC1"
67431059 AF	317
	318	#define TSEC1_PHY_ADDR 2
	319	#define TSEC2_PHY_ADDR 3
	320
	321	#define TSEC1_PHYIDX 0
	322	#define TSEC2_PHYIDX 0
	323
3a79013e AF	324	#define TSEC1_FLAGS TSEC_GIGABIT
	325	#define TSEC2_FLAGS TSEC_GIGABIT
	326
b96c83d4	327	/* Options are: eTSEC[0-1] */
67431059 AF	328	#define CONFIG_ETHPRIME "eTSEC0"
	329
	330	#endif /* CONFIG_TSEC_ENET */
	331
	332	/*
	333	* Environment
	334	*/
cdab5e90	335	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
0e8d1586	336	#define CONFIG_ENV_SIZE 0x2000
cdab5e90	337	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
67431059 AF	338
67431059 AF	339	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	340	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
67431059	341
079a136c JL	342	/*
	343	* BOOTP options
	344	*/
	345	#define CONFIG_BOOTP_BOOTFILESIZE
079a136c	346
67431059 AF	347	#undef CONFIG_WATCHDOG /* watchdog disabled */
	348
	349	/*
	350	* Miscellaneous configurable options
	351	*/
6d0f6bcf	352	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
67431059 AF	353
	354	/*
	355	* For booting Linux, the board info and command line data
a832ac41	356	* have to be in the first 64 MB of memory, since this is
67431059 AF	357	* the maximum mapped by the Linux kernel during initialization.
67431059 AF	358	*/
a832ac41 KG	359	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	360	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
67431059	361
2835e518	362	#if defined(CONFIG_CMD_KGDB)
67431059	363	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
67431059 AF	364	#endif
	365
	366	/*
	367	* Environment Configuration
	368	*/
	369
	370	/* The mac addresses for all ethernet interface */
da9d4610 AF	371	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_UEC_ETH)
da9d4610 AF	372	#define CONFIG_HAS_ETH0
67431059	373	#define CONFIG_HAS_ETH1
67431059	374	#define CONFIG_HAS_ETH2
da9d4610	375	#define CONFIG_HAS_ETH3
67431059 AF	376	#endif
	377
	378	#define CONFIG_IPADDR 192.168.1.253
	379
	380	#define CONFIG_HOSTNAME unknown
8b3637c6	381	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	382	#define CONFIG_BOOTFILE "your.uImage"
67431059 AF	383
	384	#define CONFIG_SERVERIP 192.168.1.1
	385	#define CONFIG_GATEWAYIP 192.168.1.1
	386	#define CONFIG_NETMASK 255.255.255.0
	387
	388	#define CONFIG_LOADADDR 200000 /default location for tftp and bootm/
	389
67431059 AF	390	#define CONFIG_EXTRA_ENV_SETTINGS \
	391	"netdev=eth0\0" \
	392	"consoledev=ttyS0\0" \
	393	"ramdiskaddr=600000\0" \
	394	"ramdiskfile=your.ramdisk.u-boot\0" \
	395	"fdtaddr=400000\0" \
	396	"fdtfile=your.fdt.dtb\0" \
	397	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	398	"nfsroot=$serverip:$rootpath " \
	399	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	400	"console=$consoledev,$baudrate $othbootargs\0" \
	401	"ramargs=setenv bootargs root=/dev/ram rw " \
	402	"console=$consoledev,$baudrate $othbootargs\0" \
	403
67431059 AF	404	#define CONFIG_NFSBOOTCOMMAND \
	405	"run nfsargs;" \
	406	"tftp $loadaddr $bootfile;" \
	407	"tftp $fdtaddr $fdtfile;" \
	408	"bootm $loadaddr - $fdtaddr"
	409
67431059 AF	410	#define CONFIG_RAMBOOTCOMMAND \
	411	"run ramargs;" \
	412	"tftp $ramdiskaddr $ramdiskfile;" \
	413	"tftp $loadaddr $bootfile;" \
	414	"bootm $loadaddr $ramdiskaddr"
	415
	416	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	417
	418	#endif /* __CONFIG_H */