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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
67431059 | 2 | /* |
5f7bbd13 | 3 | * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. |
67431059 AF |
4 | */ |
5 | ||
6 | /* | |
7 | * mpc8568mds board configuration file | |
8 | */ | |
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
5f7bbd13 KG |
12 | #define CONFIG_SYS_SRIO |
13 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
14 | ||
1563f56e HW |
15 | #define CONFIG_PCI1 1 /* PCI controller */ |
16 | #define CONFIG_PCIE1 1 /* PCIE controller */ | |
17 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ | |
842033e6 | 18 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ff3de61 | 19 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 20 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
67431059 | 21 | #define CONFIG_ENV_OVERWRITE |
67431059 | 22 | |
67431059 AF |
23 | #ifndef __ASSEMBLY__ |
24 | extern unsigned long get_clock_freq(void); | |
25 | #endif /*Replace a call to get_clock_freq (after it is implemented)*/ | |
26 | #define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ | |
27 | ||
28 | /* | |
29 | * These can be toggled for performance analysis, otherwise use default. | |
30 | */ | |
53677ef1 | 31 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
7a1ac419 | 32 | #define CONFIG_BTB /* toggle branch predition */ |
67431059 AF |
33 | |
34 | /* | |
35 | * Only possible on E500 Version 2 or newer cores. | |
36 | */ | |
37 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
38 | ||
6d0f6bcf JCPV |
39 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
40 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
67431059 | 41 | |
e46fedfe TT |
42 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
43 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
67431059 | 44 | |
e6f5b35b | 45 | /* DDR Setup */ |
e6f5b35b JL |
46 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
47 | #define CONFIG_DDR_SPD | |
9b0ad1b1 | 48 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
e6f5b35b JL |
49 | |
50 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
51 | ||
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
53 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
67431059 | 54 | |
e6f5b35b JL |
55 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
56 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
67431059 | 57 | |
e6f5b35b JL |
58 | /* I2C addresses of SPD EEPROMs */ |
59 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
60 | ||
61 | /* Make sure required options are set */ | |
67431059 AF |
62 | #ifndef CONFIG_SPD_EEPROM |
63 | #error ("CONFIG_SPD_EEPROM is required") | |
64 | #endif | |
65 | ||
66 | #undef CONFIG_CLOCKS_IN_MHZ | |
67 | ||
67431059 AF |
68 | /* |
69 | * Local Bus Definitions | |
70 | */ | |
71 | ||
72 | /* | |
73 | * FLASH on the Local Bus | |
74 | * Two banks, 8M each, using the CFI driver. | |
75 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
76 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
77 | * | |
78 | * BR0, BR1: | |
79 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
80 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
81 | * Port Size = 16 bits = BRx[19:20] = 10 | |
82 | * Use GPCM = BRx[24:26] = 000 | |
83 | * Valid = BRx[31] = 1 | |
84 | * | |
85 | * 0 4 8 12 16 20 24 28 | |
86 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
87 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
88 | * | |
89 | * OR0, OR1: | |
90 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
91 | * Reserved ORx[17:18] = 11, confusion here? | |
92 | * CSNT = ORx[20] = 1 | |
93 | * ACS = half cycle delay = ORx[21:22] = 11 | |
94 | * SCY = 6 = ORx[24:27] = 0110 | |
95 | * TRLX = use relaxed timing = ORx[29] = 1 | |
96 | * EAD = use external address latch delay = OR[31] = 1 | |
97 | * | |
98 | * 0 4 8 12 16 20 24 28 | |
99 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
100 | */ | |
6d0f6bcf | 101 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 |
67431059 | 102 | |
6d0f6bcf | 103 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ |
67431059 AF |
104 | |
105 | /*Chip select 0 - Flash*/ | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_BR0_PRELIM 0xfe001001 |
107 | #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 | |
67431059 AF |
108 | |
109 | /*Chip slelect 1 - BCSR*/ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
111 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 | |
67431059 | 112 | |
6d0f6bcf JCPV |
113 | /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ |
114 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
115 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
116 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
117 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
118 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
67431059 | 119 | |
14d0a02a | 120 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
67431059 | 121 | |
6d0f6bcf | 122 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
67431059 | 123 | |
67431059 AF |
124 | /* |
125 | * SDRAM on the LocalBus | |
126 | */ | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
128 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
67431059 | 129 | |
67431059 | 130 | /*Chip select 2 - SDRAM*/ |
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
132 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 | |
67431059 | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
135 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
136 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
137 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
67431059 | 138 | |
67431059 AF |
139 | /* |
140 | * Common settings for all Local Bus SDRAM commands. | |
141 | * At run time, either BSMA1516 (for CPU 1.1) | |
142 | * or BSMA1617 (for CPU 1.0) (old) | |
143 | * is OR'ed in too. | |
144 | */ | |
b0fe93ed KG |
145 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
146 | | LSDMR_PRETOACT7 \ | |
147 | | LSDMR_ACTTORW7 \ | |
148 | | LSDMR_BL8 \ | |
149 | | LSDMR_WRC4 \ | |
150 | | LSDMR_CL3 \ | |
151 | | LSDMR_RFEN \ | |
67431059 AF |
152 | ) |
153 | ||
154 | /* | |
155 | * The bcsr registers are connected to CS3 on MDS. | |
156 | * The new memory map places bcsr at 0xf8000000. | |
157 | * | |
158 | * For BR3, need: | |
159 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
160 | * port-size = 8-bits = BR[19:20] = 01 | |
161 | * no parity checking = BR[21:22] = 00 | |
162 | * GPMC for MSEL = BR[24:26] = 000 | |
163 | * Valid = BR[31] = 1 | |
164 | * | |
165 | * 0 4 8 12 16 20 24 28 | |
166 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 | |
167 | * | |
168 | * For OR3, need: | |
169 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 | |
170 | * disable buffer ctrl OR[19] = 0 | |
171 | * CSNT OR[20] = 1 | |
172 | * ACS OR[21:22] = 11 | |
173 | * XACS OR[23] = 1 | |
174 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe | |
175 | * SETA OR[28] = 0 | |
176 | * TRLX OR[29] = 1 | |
177 | * EHTR OR[30] = 1 | |
178 | * EAD extra time OR[31] = 1 | |
179 | * | |
180 | * 0 4 8 12 16 20 24 28 | |
181 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 | |
182 | */ | |
6d0f6bcf | 183 | #define CONFIG_SYS_BCSR (0xf8000000) |
67431059 AF |
184 | |
185 | /*Chip slelect 4 - PIB*/ | |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 |
187 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 | |
67431059 AF |
188 | |
189 | /*Chip select 5 - PIB*/ | |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 |
191 | #define CONFIG_SYS_OR5_PRELIM 0xffff69f7 | |
67431059 | 192 | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
194 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 195 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
67431059 | 196 | |
25ddd1fb | 197 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 198 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
67431059 | 199 | |
6d0f6bcf | 200 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
cdab5e90 | 201 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
67431059 AF |
202 | |
203 | /* Serial Port */ | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_NS16550_SERIAL |
205 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
206 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
67431059 | 207 | |
6d0f6bcf | 208 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
67431059 AF |
209 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
210 | ||
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
212 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
67431059 | 213 | |
67431059 AF |
214 | /* |
215 | * I2C | |
216 | */ | |
00f792e0 HS |
217 | #define CONFIG_SYS_I2C |
218 | #define CONFIG_SYS_I2C_FSL | |
219 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
220 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
221 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
222 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
223 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
224 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
225 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
6d0f6bcf | 226 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 |
67431059 AF |
227 | |
228 | /* | |
229 | * General PCI | |
230 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
231 | */ | |
5af0fdd8 | 232 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 233 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 234 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 235 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 236 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 237 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
239 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ | |
240 | ||
3f6f9d76 | 241 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
5af0fdd8 | 242 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
10795f42 | 243 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 244 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
6d0f6bcf | 245 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 246 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 |
5f91ef6a | 247 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 |
249 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
250 | ||
5f7bbd13 KG |
251 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
252 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 | |
253 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS | |
254 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
67431059 | 255 | |
da9d4610 AF |
256 | #ifdef CONFIG_QE |
257 | /* | |
258 | * QE UEC ethernet configuration | |
259 | */ | |
260 | #define CONFIG_UEC_ETH | |
261 | #ifndef CONFIG_TSEC_ENET | |
78b7a8ef | 262 | #define CONFIG_ETHPRIME "UEC0" |
da9d4610 AF |
263 | #endif |
264 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
265 | #define CONFIG_eTSEC_MDIO_BUS | |
266 | ||
267 | #ifdef CONFIG_eTSEC_MDIO_BUS | |
53677ef1 | 268 | #define CONFIG_MIIM_ADDRESS 0xE0024520 |
da9d4610 AF |
269 | #endif |
270 | ||
271 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
272 | ||
273 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
275 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
276 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 | |
277 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
278 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 | |
865ff856 | 279 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 280 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
da9d4610 AF |
281 | #endif |
282 | ||
283 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
284 | ||
285 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
287 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
288 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 | |
289 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
290 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
865ff856 | 291 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 292 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
da9d4610 AF |
293 | #endif |
294 | #endif /* CONFIG_QE */ | |
295 | ||
f30ad49b | 296 | #if defined(CONFIG_PCI) |
67431059 AF |
297 | #undef CONFIG_EEPRO100 |
298 | #undef CONFIG_TULIP | |
299 | ||
300 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 301 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
67431059 AF |
302 | |
303 | #endif /* CONFIG_PCI */ | |
304 | ||
da9d4610 AF |
305 | #if defined(CONFIG_TSEC_ENET) |
306 | ||
255a3577 KP |
307 | #define CONFIG_TSEC1 1 |
308 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
309 | #define CONFIG_TSEC2 1 | |
310 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
67431059 AF |
311 | |
312 | #define TSEC1_PHY_ADDR 2 | |
313 | #define TSEC2_PHY_ADDR 3 | |
314 | ||
315 | #define TSEC1_PHYIDX 0 | |
316 | #define TSEC2_PHYIDX 0 | |
317 | ||
3a79013e AF |
318 | #define TSEC1_FLAGS TSEC_GIGABIT |
319 | #define TSEC2_FLAGS TSEC_GIGABIT | |
320 | ||
b96c83d4 | 321 | /* Options are: eTSEC[0-1] */ |
67431059 AF |
322 | #define CONFIG_ETHPRIME "eTSEC0" |
323 | ||
324 | #endif /* CONFIG_TSEC_ENET */ | |
325 | ||
326 | /* | |
327 | * Environment | |
328 | */ | |
cdab5e90 | 329 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
0e8d1586 | 330 | #define CONFIG_ENV_SIZE 0x2000 |
cdab5e90 | 331 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
67431059 AF |
332 | |
333 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 334 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
67431059 | 335 | |
079a136c JL |
336 | /* |
337 | * BOOTP options | |
338 | */ | |
339 | #define CONFIG_BOOTP_BOOTFILESIZE | |
079a136c | 340 | |
67431059 AF |
341 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
342 | ||
343 | /* | |
344 | * Miscellaneous configurable options | |
345 | */ | |
6d0f6bcf | 346 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
67431059 AF |
347 | |
348 | /* | |
349 | * For booting Linux, the board info and command line data | |
a832ac41 | 350 | * have to be in the first 64 MB of memory, since this is |
67431059 AF |
351 | * the maximum mapped by the Linux kernel during initialization. |
352 | */ | |
a832ac41 KG |
353 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
354 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
67431059 | 355 | |
2835e518 | 356 | #if defined(CONFIG_CMD_KGDB) |
67431059 | 357 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
67431059 AF |
358 | #endif |
359 | ||
360 | /* | |
361 | * Environment Configuration | |
362 | */ | |
363 | ||
364 | /* The mac addresses for all ethernet interface */ | |
da9d4610 AF |
365 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) |
366 | #define CONFIG_HAS_ETH0 | |
67431059 | 367 | #define CONFIG_HAS_ETH1 |
67431059 | 368 | #define CONFIG_HAS_ETH2 |
da9d4610 | 369 | #define CONFIG_HAS_ETH3 |
67431059 AF |
370 | #endif |
371 | ||
372 | #define CONFIG_IPADDR 192.168.1.253 | |
373 | ||
5bc0543d | 374 | #define CONFIG_HOSTNAME "unknown" |
8b3637c6 | 375 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 376 | #define CONFIG_BOOTFILE "your.uImage" |
67431059 AF |
377 | |
378 | #define CONFIG_SERVERIP 192.168.1.1 | |
379 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
380 | #define CONFIG_NETMASK 255.255.255.0 | |
381 | ||
382 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
383 | ||
67431059 AF |
384 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
385 | "netdev=eth0\0" \ | |
386 | "consoledev=ttyS0\0" \ | |
387 | "ramdiskaddr=600000\0" \ | |
388 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
389 | "fdtaddr=400000\0" \ | |
390 | "fdtfile=your.fdt.dtb\0" \ | |
391 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
392 | "nfsroot=$serverip:$rootpath " \ | |
393 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
394 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
395 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
396 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
397 | ||
67431059 AF |
398 | #define CONFIG_NFSBOOTCOMMAND \ |
399 | "run nfsargs;" \ | |
400 | "tftp $loadaddr $bootfile;" \ | |
401 | "tftp $fdtaddr $fdtfile;" \ | |
402 | "bootm $loadaddr - $fdtaddr" | |
403 | ||
67431059 AF |
404 | #define CONFIG_RAMBOOTCOMMAND \ |
405 | "run ramargs;" \ | |
406 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
407 | "tftp $loadaddr $bootfile;" \ | |
408 | "bootm $loadaddr $ramdiskaddr" | |
409 | ||
410 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
411 | ||
412 | #endif /* __CONFIG_H */ |