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Commit | Line | Data |
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765547dc | 1 | /* |
e5fe96b1 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
765547dc | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
765547dc HW |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8569mds board configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
e5fe96b1 KG |
13 | #define CONFIG_SYS_SRIO |
14 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
15 | ||
765547dc HW |
16 | #define CONFIG_PCIE1 1 /* PCIE controller */ |
17 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ | |
842033e6 | 18 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
765547dc HW |
19 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
20 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
21 | #define CONFIG_QE /* Enable QE */ | |
22 | #define CONFIG_ENV_OVERWRITE | |
765547dc | 23 | |
765547dc HW |
24 | #ifndef __ASSEMBLY__ |
25 | extern unsigned long get_clock_freq(void); | |
26 | #endif | |
27 | /* Replace a call to get_clock_freq (after it is implemented)*/ | |
67351049 DL |
28 | #define CONFIG_SYS_CLK_FREQ 66666666 |
29 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
765547dc | 30 | |
d24f2d32 | 31 | #ifdef CONFIG_ATM |
c95d541e LY |
32 | #define CONFIG_PQ_MDS_PIB |
33 | #define CONFIG_PQ_MDS_PIB_ATM | |
34 | #endif | |
35 | ||
765547dc HW |
36 | /* |
37 | * These can be toggled for performance analysis, otherwise use default. | |
38 | */ | |
39 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
40 | #define CONFIG_BTB /* toggle branch predition */ | |
41 | ||
96196a1f HW |
42 | #ifndef CONFIG_SYS_MONITOR_BASE |
43 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
44 | #endif | |
45 | ||
765547dc HW |
46 | /* |
47 | * Only possible on E500 Version 2 or newer cores. | |
48 | */ | |
49 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
50 | ||
3aed5507 | 51 | #define CONFIG_BOARD_EARLY_INIT_R 1 |
7f52ed5e | 52 | #define CONFIG_HWCONFIG |
765547dc HW |
53 | |
54 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
55 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
56 | ||
674ef7bd LY |
57 | /* |
58 | * Config the L2 Cache as L2 SRAM | |
59 | */ | |
60 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
61 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
62 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
63 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
64 | ||
e46fedfe TT |
65 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
66 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
765547dc | 67 | |
8d22ddca | 68 | #if defined(CONFIG_NAND_SPL) |
e46fedfe | 69 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
674ef7bd LY |
70 | #endif |
71 | ||
765547dc | 72 | /* DDR Setup */ |
765547dc HW |
73 | #undef CONFIG_FSL_DDR_INTERACTIVE |
74 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
75 | #define CONFIG_DDR_SPD | |
765547dc HW |
76 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
77 | ||
78 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
79 | ||
80 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
81 | /* DDR is system memory*/ | |
82 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
83 | ||
765547dc HW |
84 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
85 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
86 | ||
87 | /* I2C addresses of SPD EEPROMs */ | |
c39f44dc | 88 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
765547dc HW |
89 | |
90 | /* These are used when DDR doesn't use SPD. */ | |
91 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ | |
92 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
93 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
94 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
95 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
96 | #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 | |
97 | #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 | |
98 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 | |
99 | #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 | |
100 | #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 | |
101 | #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 | |
102 | #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 | |
103 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
104 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 | |
105 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
106 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
107 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
108 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 | |
109 | #define CONFIG_SYS_DDR_CDR_1 0x80040000 | |
110 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 | |
111 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
112 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
113 | #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ | |
114 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
115 | ||
116 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
117 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
118 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
119 | ||
120 | #undef CONFIG_CLOCKS_IN_MHZ | |
121 | ||
122 | /* | |
123 | * Local Bus Definitions | |
124 | */ | |
125 | ||
126 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ | |
127 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
128 | ||
129 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 | |
130 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE | |
131 | ||
132 | /*Chip select 0 - Flash*/ | |
674ef7bd LY |
133 | #define CONFIG_FLASH_BR_PRELIM 0xfe000801 |
134 | #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 | |
765547dc | 135 | |
399b53cb | 136 | /*Chip select 1 - BCSR*/ |
765547dc HW |
137 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
138 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 | |
139 | ||
399b53cb HW |
140 | /*Chip select 4 - PIB*/ |
141 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 | |
142 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 | |
143 | ||
144 | /*Chip select 5 - PIB*/ | |
145 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 | |
146 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 | |
147 | ||
765547dc HW |
148 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
149 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
150 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
151 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
152 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
153 | ||
674ef7bd | 154 | #undef CONFIG_SYS_RAMBOOT |
674ef7bd | 155 | |
765547dc HW |
156 | #define CONFIG_FLASH_CFI_DRIVER |
157 | #define CONFIG_SYS_FLASH_CFI | |
158 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
159 | ||
a29155e1 | 160 | /* Chip select 3 - NAND */ |
674ef7bd | 161 | #ifndef CONFIG_NAND_SPL |
a29155e1 | 162 | #define CONFIG_SYS_NAND_BASE 0xFC000000 |
674ef7bd LY |
163 | #else |
164 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
165 | #endif | |
166 | ||
167 | /* NAND boot: 4K NAND loader config */ | |
168 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
169 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
170 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
171 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
172 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
173 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
174 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
175 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
176 | ||
a29155e1 AV |
177 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
178 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } | |
179 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
a29155e1 AV |
180 | #define CONFIG_NAND_FSL_ELBC 1 |
181 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
a3055c58 | 182 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ |
a29155e1 AV |
183 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
184 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
185 | | BR_MS_FCM /* MSEL = FCM */ \ | |
186 | | BR_V) /* valid */ | |
a3055c58 | 187 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
a29155e1 AV |
188 | | OR_FCM_CSCT \ |
189 | | OR_FCM_CST \ | |
190 | | OR_FCM_CHT \ | |
191 | | OR_FCM_SCY_1 \ | |
192 | | OR_FCM_TRLX \ | |
193 | | OR_FCM_EHTR) | |
674ef7bd | 194 | |
674ef7bd LY |
195 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
196 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
197 | #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
198 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
765547dc | 199 | |
765547dc HW |
200 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ |
201 | #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ | |
202 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
203 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
204 | ||
205 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
206 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 207 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
765547dc | 208 | |
765547dc | 209 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 210 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
765547dc HW |
211 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
212 | ||
213 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
fb279490 | 214 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
765547dc HW |
215 | |
216 | /* Serial Port */ | |
217 | #define CONFIG_CONS_INDEX 1 | |
765547dc HW |
218 | #define CONFIG_SYS_NS16550_SERIAL |
219 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
220 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
93341909 KG |
221 | #ifdef CONFIG_NAND_SPL |
222 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
223 | #endif | |
765547dc HW |
224 | |
225 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
226 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
227 | ||
228 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
229 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
230 | ||
765547dc HW |
231 | /* |
232 | * I2C | |
233 | */ | |
00f792e0 HS |
234 | #define CONFIG_SYS_I2C |
235 | #define CONFIG_SYS_I2C_FSL | |
236 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
237 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
238 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
239 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
240 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
241 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
242 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
765547dc HW |
243 | |
244 | /* | |
245 | * I2C2 EEPROM | |
246 | */ | |
247 | #define CONFIG_ID_EEPROM | |
248 | #ifdef CONFIG_ID_EEPROM | |
249 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
250 | #endif | |
251 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
252 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
253 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
254 | ||
255 | #define PLPPAR1_I2C_BIT_MASK 0x0000000F | |
256 | #define PLPPAR1_I2C2_VAL 0x00000000 | |
7f52ed5e | 257 | #define PLPPAR1_ESDHC_VAL 0x0000000A |
765547dc HW |
258 | #define PLPDIR1_I2C_BIT_MASK 0x0000000F |
259 | #define PLPDIR1_I2C2_VAL 0x0000000F | |
7f52ed5e | 260 | #define PLPDIR1_ESDHC_VAL 0x00000006 |
c4ca10f1 AV |
261 | #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 |
262 | #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 | |
263 | #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 | |
264 | #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 | |
765547dc HW |
265 | |
266 | /* | |
267 | * General PCI | |
268 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
269 | */ | |
94f2bc48 | 270 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
765547dc HW |
271 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
272 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
273 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
274 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
275 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 | |
276 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
277 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
278 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
279 | ||
e5fe96b1 KG |
280 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
281 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 | |
282 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS | |
283 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
765547dc HW |
284 | |
285 | #ifdef CONFIG_QE | |
286 | /* | |
287 | * QE UEC ethernet configuration | |
288 | */ | |
f82107f6 HW |
289 | #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ |
290 | #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ | |
765547dc HW |
291 | |
292 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
293 | #define CONFIG_UEC_ETH | |
78b7a8ef | 294 | #define CONFIG_ETHPRIME "UEC0" |
765547dc HW |
295 | #define CONFIG_PHY_MODE_NEED_CHANGE |
296 | ||
297 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
298 | #define CONFIG_HAS_ETH0 | |
299 | ||
300 | #ifdef CONFIG_UEC_ETH1 | |
301 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
302 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
f82107f6 | 303 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
304 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
305 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
306 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 | |
865ff856 | 307 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 308 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
f82107f6 HW |
309 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
310 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
311 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
312 | #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ | |
865ff856 | 313 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 314 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
f82107f6 HW |
315 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
316 | #endif /* CONFIG_UEC_ETH1 */ | |
765547dc HW |
317 | |
318 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
319 | #define CONFIG_HAS_ETH1 | |
320 | ||
321 | #ifdef CONFIG_UEC_ETH2 | |
322 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ | |
323 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
f82107f6 | 324 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
325 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
326 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
327 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
865ff856 | 328 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 329 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
f82107f6 HW |
330 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
331 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ | |
332 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
333 | #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ | |
865ff856 | 334 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 335 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
f82107f6 HW |
336 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
337 | #endif /* CONFIG_UEC_ETH2 */ | |
765547dc | 338 | |
750098d3 HW |
339 | #define CONFIG_UEC_ETH3 /* GETH3 */ |
340 | #define CONFIG_HAS_ETH2 | |
341 | ||
342 | #ifdef CONFIG_UEC_ETH3 | |
343 | #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ | |
344 | #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE | |
f82107f6 | 345 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
346 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 |
347 | #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH | |
348 | #define CONFIG_SYS_UEC3_PHY_ADDR 2 | |
865ff856 | 349 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 350 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 |
f82107f6 HW |
351 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
352 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ | |
353 | #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH | |
354 | #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ | |
865ff856 | 355 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 356 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 |
f82107f6 HW |
357 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
358 | #endif /* CONFIG_UEC_ETH3 */ | |
750098d3 HW |
359 | |
360 | #define CONFIG_UEC_ETH4 /* GETH4 */ | |
361 | #define CONFIG_HAS_ETH3 | |
362 | ||
363 | #ifdef CONFIG_UEC_ETH4 | |
364 | #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ | |
365 | #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE | |
f82107f6 | 366 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
367 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 |
368 | #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH | |
369 | #define CONFIG_SYS_UEC4_PHY_ADDR 3 | |
865ff856 | 370 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 371 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 |
f82107f6 HW |
372 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
373 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
374 | #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH | |
375 | #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ | |
865ff856 | 376 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 377 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 |
f82107f6 HW |
378 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
379 | #endif /* CONFIG_UEC_ETH4 */ | |
3bd8e532 HW |
380 | |
381 | #undef CONFIG_UEC_ETH6 /* GETH6 */ | |
382 | #define CONFIG_HAS_ETH5 | |
383 | ||
384 | #ifdef CONFIG_UEC_ETH6 | |
385 | #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ | |
386 | #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE | |
387 | #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE | |
388 | #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH | |
389 | #define CONFIG_SYS_UEC6_PHY_ADDR 4 | |
865ff856 | 390 | #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
582c55a0 | 391 | #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 |
3bd8e532 HW |
392 | #endif /* CONFIG_UEC_ETH6 */ |
393 | ||
394 | #undef CONFIG_UEC_ETH8 /* GETH8 */ | |
395 | #define CONFIG_HAS_ETH7 | |
396 | ||
397 | #ifdef CONFIG_UEC_ETH8 | |
398 | #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ | |
399 | #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE | |
400 | #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE | |
401 | #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH | |
402 | #define CONFIG_SYS_UEC8_PHY_ADDR 6 | |
865ff856 | 403 | #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
582c55a0 | 404 | #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 |
3bd8e532 HW |
405 | #endif /* CONFIG_UEC_ETH8 */ |
406 | ||
765547dc HW |
407 | #endif /* CONFIG_QE */ |
408 | ||
409 | #if defined(CONFIG_PCI) | |
765547dc HW |
410 | #undef CONFIG_EEPRO100 |
411 | #undef CONFIG_TULIP | |
412 | ||
413 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
414 | ||
415 | #endif /* CONFIG_PCI */ | |
416 | ||
765547dc HW |
417 | /* |
418 | * Environment | |
419 | */ | |
674ef7bd | 420 | #if defined(CONFIG_SYS_RAMBOOT) |
674ef7bd | 421 | #else |
fb279490 | 422 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
1b8e4fa1 HW |
423 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
424 | #define CONFIG_ENV_SIZE 0x2000 | |
674ef7bd | 425 | #endif |
765547dc HW |
426 | |
427 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
428 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
429 | ||
430 | /* QE microcode/firmware address */ | |
f2717b47 | 431 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
dcf1d774 | 432 | #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 |
765547dc HW |
433 | |
434 | /* | |
435 | * BOOTP options | |
436 | */ | |
437 | #define CONFIG_BOOTP_BOOTFILESIZE | |
765547dc | 438 | |
765547dc HW |
439 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
440 | ||
7f52ed5e AV |
441 | #ifdef CONFIG_MMC |
442 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 443 | #define CONFIG_FSL_ESDHC_PIN_MUX |
7f52ed5e | 444 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
7f52ed5e AV |
445 | #endif |
446 | ||
765547dc HW |
447 | /* |
448 | * Miscellaneous configurable options | |
449 | */ | |
765547dc | 450 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
765547dc HW |
451 | #if defined(CONFIG_CMD_KGDB) |
452 | #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ | |
453 | #else | |
454 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
455 | #endif | |
765547dc HW |
456 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
457 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
458 | /* Boot Argument Buffer Size */ | |
765547dc HW |
459 | |
460 | /* | |
461 | * For booting Linux, the board info and command line data | |
a832ac41 | 462 | * have to be in the first 64 MB of memory, since this is |
765547dc HW |
463 | * the maximum mapped by the Linux kernel during initialization. |
464 | */ | |
a832ac41 KG |
465 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
466 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
765547dc | 467 | |
765547dc HW |
468 | #if defined(CONFIG_CMD_KGDB) |
469 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
765547dc HW |
470 | #endif |
471 | ||
472 | /* | |
473 | * Environment Configuration | |
474 | */ | |
475 | #define CONFIG_HOSTNAME mpc8569mds | |
8b3637c6 | 476 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 477 | #define CONFIG_BOOTFILE "your.uImage" |
765547dc HW |
478 | |
479 | #define CONFIG_SERVERIP 192.168.1.1 | |
480 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
481 | #define CONFIG_NETMASK 255.255.255.0 | |
482 | ||
483 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
484 | ||
765547dc HW |
485 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
486 | "netdev=eth0\0" \ | |
487 | "consoledev=ttyS0\0" \ | |
488 | "ramdiskaddr=600000\0" \ | |
489 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
490 | "fdtaddr=400000\0" \ | |
491 | "fdtfile=your.fdt.dtb\0" \ | |
492 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
493 | "nfsroot=$serverip:$rootpath " \ | |
494 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
495 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
496 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
497 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
498 | ||
499 | #define CONFIG_NFSBOOTCOMMAND \ | |
500 | "run nfsargs;" \ | |
501 | "tftp $loadaddr $bootfile;" \ | |
502 | "tftp $fdtaddr $fdtfile;" \ | |
503 | "bootm $loadaddr - $fdtaddr" | |
504 | ||
505 | #define CONFIG_RAMBOOTCOMMAND \ | |
506 | "run ramargs;" \ | |
507 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
508 | "tftp $loadaddr $bootfile;" \ | |
509 | "bootm $loadaddr $ramdiskaddr" | |
510 | ||
511 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
512 | ||
513 | #endif /* __CONFIG_H */ |