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9553df86 | 1 | /* |
ba8e76bd | 2 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
9553df86 JL |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | /* | |
10 | * MPC8610HPCD board configuration file | |
9553df86 JL |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* High Level Configuration Options */ | |
17 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
18 | #define CONFIG_MPC8610 1 /* MPC8610 specific */ | |
19 | #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ | |
9553df86 JL |
20 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
21 | ||
2ae18241 WD |
22 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
23 | ||
070ba561 YS |
24 | |
25 | /* video */ | |
ba8e76bd TT |
26 | #define CONFIG_FSL_DIU_FB |
27 | ||
7d3053fb TT |
28 | #ifdef CONFIG_FSL_DIU_FB |
29 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) | |
30 | #define CONFIG_VIDEO | |
e69e520f | 31 | #define CONFIG_CMD_BMP |
070ba561 | 32 | #define CONFIG_CFB_CONSOLE |
7d3053fb | 33 | #define CONFIG_VIDEO_SW_CURSOR |
070ba561 | 34 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
e69e520f TT |
35 | #define CONFIG_VIDEO_LOGO |
36 | #define CONFIG_VIDEO_BMP_LOGO | |
070ba561 YS |
37 | #endif |
38 | ||
9553df86 | 39 | #ifdef RUN_DIAG |
6d0f6bcf | 40 | #define CONFIG_SYS_DIAG_ADDR 0xff800000 |
9553df86 JL |
41 | #endif |
42 | ||
1266df88 BB |
43 | /* |
44 | * virtual address to be used for temporary mappings. There | |
45 | * should be 128k free at this VA. | |
46 | */ | |
47 | #define CONFIG_SYS_SCRATCH_VA 0xc0000000 | |
48 | ||
9553df86 JL |
49 | #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ |
50 | #define CONFIG_PCI1 1 /* PCI controler 1 */ | |
51 | #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ | |
52 | #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ | |
53 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 54 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ba93f68 | 55 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
031976f6 | 56 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
9553df86 JL |
57 | |
58 | #define CONFIG_ENV_OVERWRITE | |
9553df86 JL |
59 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
60 | ||
4bbfd3e2 | 61 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
31d82672 | 62 | #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ |
9553df86 JL |
63 | #define CONFIG_ALTIVEC 1 |
64 | ||
65 | /* | |
66 | * L2CR setup -- make sure this is right for your board! | |
67 | */ | |
6d0f6bcf | 68 | #define CONFIG_SYS_L2 |
9553df86 | 69 | #define L2_INIT 0 |
a877880c | 70 | #define L2_ENABLE (L2CR_L2E |0x00100000 ) |
9553df86 JL |
71 | |
72 | #ifndef CONFIG_SYS_CLK_FREQ | |
73 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
74 | #endif | |
75 | ||
76 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
a877880c | 77 | #define CONFIG_MISC_INIT_R 1 |
9553df86 | 78 | |
6d0f6bcf JCPV |
79 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
80 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
9553df86 JL |
81 | |
82 | /* | |
83 | * Base addresses -- Note these are effective addresses where the | |
84 | * actual resources get mapped (not physical addresses) | |
85 | */ | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
87 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
88 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
9553df86 | 89 | |
f698738e JL |
90 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
91 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
ad19e7a5 | 92 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
f698738e | 93 | |
39aa1a73 | 94 | /* DDR Setup */ |
5614e71b | 95 | #define CONFIG_SYS_FSL_DDR2 |
39aa1a73 JL |
96 | #undef CONFIG_FSL_DDR_INTERACTIVE |
97 | #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ | |
98 | #define CONFIG_DDR_SPD | |
99 | ||
100 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
101 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
102 | ||
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
104 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1266df88 | 105 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
9553df86 JL |
106 | #define CONFIG_VERY_BIG_RAM |
107 | ||
39aa1a73 JL |
108 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
109 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
110 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
111 | ||
c39f44dc | 112 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
9553df86 | 113 | |
39aa1a73 | 114 | /* These are used when DDR doesn't use SPD. */ |
6d0f6bcf | 115 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
9553df86 JL |
116 | |
117 | #if 0 /* TODO */ | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F |
119 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
120 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
121 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
122 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
123 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
124 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
125 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
126 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
127 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
128 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
129 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
130 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
131 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
132 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 | |
133 | ||
134 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 | |
135 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
136 | #define CONFIG_SYS_DDR_SBE 0x000f0000 | |
39aa1a73 | 137 | |
9553df86 | 138 | #endif |
39aa1a73 | 139 | |
9553df86 | 140 | |
ad8f8687 | 141 | #define CONFIG_ID_EEPROM |
6d0f6bcf | 142 | #define CONFIG_SYS_I2C_EEPROM_NXID |
32628c50 | 143 | #define CONFIG_ID_EEPROM |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
145 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
9553df86 JL |
146 | |
147 | ||
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ |
149 | #define CONFIG_SYS_FLASH_BASE2 0xf8000000 | |
9553df86 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} |
9553df86 | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ |
154 | #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ | |
9553df86 | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ |
157 | #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ | |
9553df86 | 158 | #if 0 /* TODO */ |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_BR2_PRELIM 0xf0000000 |
160 | #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ | |
9553df86 | 161 | #endif |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ |
163 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
9553df86 JL |
164 | |
165 | ||
761421cc | 166 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
9553df86 JL |
167 | #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ |
168 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
169 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
170 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
171 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
172 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ | |
173 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
a877880c | 174 | #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ |
9553df86 JL |
175 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
176 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
177 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
178 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
179 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
180 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
181 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
182 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
2feb4af0 | 183 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ |
9553df86 | 184 | |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
186 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
9553df86 | 187 | |
6d0f6bcf JCPV |
188 | #undef CONFIG_SYS_FLASH_CHECKSUM |
189 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
190 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
14d0a02a | 191 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
bf9a8c34 | 192 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
9553df86 | 193 | |
00b1883a | 194 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_CFI |
196 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
9553df86 | 197 | |
6d0f6bcf JCPV |
198 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
199 | #define CONFIG_SYS_RAMBOOT | |
9553df86 | 200 | #else |
6d0f6bcf | 201 | #undef CONFIG_SYS_RAMBOOT |
9553df86 JL |
202 | #endif |
203 | ||
6d0f6bcf | 204 | #if defined(CONFIG_SYS_RAMBOOT) |
9553df86 | 205 | #undef CONFIG_SPD_EEPROM |
6d0f6bcf | 206 | #define CONFIG_SYS_SDRAM_SIZE 256 |
9553df86 JL |
207 | #endif |
208 | ||
209 | #undef CONFIG_CLOCKS_IN_MHZ | |
210 | ||
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
212 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
213 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
9553df86 | 214 | #else |
6d0f6bcf | 215 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ |
9553df86 | 216 | #endif |
553f0982 | 217 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
9553df86 | 218 | |
25ddd1fb | 219 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 220 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9553df86 | 221 | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ |
223 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ | |
9553df86 JL |
224 | |
225 | /* Serial Port */ | |
226 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_NS16550 |
228 | #define CONFIG_SYS_NS16550_SERIAL | |
229 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
230 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
9553df86 | 231 | |
6d0f6bcf | 232 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9553df86 JL |
233 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
234 | ||
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
236 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
9553df86 JL |
237 | |
238 | /* Use the HUSH parser */ | |
6d0f6bcf | 239 | #define CONFIG_SYS_HUSH_PARSER |
9553df86 JL |
240 | |
241 | /* | |
242 | * Pass open firmware flat tree to kernel | |
243 | */ | |
1df170f8 JL |
244 | #define CONFIG_OF_LIBFDT 1 |
245 | #define CONFIG_OF_BOARD_SETUP 1 | |
246 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
247 | ||
9553df86 JL |
248 | |
249 | /* maximum size of the flat tree (8K) */ | |
250 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
251 | ||
9553df86 JL |
252 | /* |
253 | * I2C | |
254 | */ | |
00f792e0 HS |
255 | #define CONFIG_SYS_I2C |
256 | #define CONFIG_SYS_I2C_FSL | |
257 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
258 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
259 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
260 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
9553df86 JL |
261 | |
262 | /* | |
263 | * General PCI | |
264 | * Addresses are mapped 1-1. | |
265 | */ | |
3e3fffe3 BB |
266 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
267 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS | |
268 | #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS | |
6d0f6bcf | 269 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
3e3fffe3 | 270 | #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 |
6d0f6bcf | 271 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 |
3e3fffe3 | 272 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 |
6d0f6bcf | 273 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
9553df86 | 274 | |
9553df86 | 275 | /* controller 1, Base address 0xa000 */ |
b8526212 | 276 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
3e3fffe3 BB |
277 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
278 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
6d0f6bcf | 279 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
3e3fffe3 | 280 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
282 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
9553df86 JL |
283 | |
284 | /* controller 2, Base Address 0x9000 */ | |
b8526212 | 285 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
3e3fffe3 BB |
286 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 |
287 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS | |
6d0f6bcf | 288 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
3e3fffe3 | 289 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 |
291 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ | |
9553df86 JL |
292 | |
293 | ||
294 | #if defined(CONFIG_PCI) | |
295 | ||
296 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
297 | ||
1d8a49ec | 298 | #define CONFIG_CMD_NET |
9553df86 | 299 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
4f93f8b1 | 300 | #define CONFIG_CMD_REGINFO |
9553df86 | 301 | |
7c2221eb RZ |
302 | #define CONFIG_ULI526X |
303 | #ifdef CONFIG_ULI526X | |
1d8a49ec RZ |
304 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 |
305 | #endif | |
9553df86 | 306 | |
9553df86 JL |
307 | /************************************************************ |
308 | * USB support | |
309 | ************************************************************/ | |
070ba561 YS |
310 | #define CONFIG_PCI_OHCI 1 |
311 | #define CONFIG_USB_OHCI_NEW 1 | |
9553df86 | 312 | #define CONFIG_USB_KEYBOARD 1 |
52cb4d4f | 313 | #define CONFIG_SYS_STDIO_DEREGISTER |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_USB_EVENT_POLL 1 |
315 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
316 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
317 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
9553df86 JL |
318 | |
319 | #if !defined(CONFIG_PCI_PNP) | |
320 | #define PCI_ENET0_IOADDR 0xe0000000 | |
321 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
322 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
323 | #endif | |
324 | ||
325 | #define CONFIG_DOS_PARTITION | |
326 | #define CONFIG_SCSI_AHCI | |
327 | ||
328 | #ifdef CONFIG_SCSI_AHCI | |
344ca0b4 | 329 | #define CONFIG_LIBATA |
9553df86 | 330 | #define CONFIG_SATA_ULI5288 |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
332 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
333 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
334 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
9553df86 JL |
335 | #endif |
336 | ||
337 | #endif /* CONFIG_PCI */ | |
338 | ||
339 | /* | |
340 | * BAT0 2G Cacheable, non-guarded | |
341 | * 0x0000_0000 2G DDR | |
342 | */ | |
9ff32d8c TT |
343 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW) |
344 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW) | |
9553df86 JL |
345 | |
346 | /* | |
347 | * BAT1 1G Cache-inhibited, guarded | |
348 | * 0x8000_0000 256M PCI-1 Memory | |
349 | * 0xa000_0000 256M PCI-Express 1 Memory | |
350 | * 0x9000_0000 256M PCI-Express 2 Memory | |
351 | */ | |
352 | ||
6d0f6bcf | 353 | #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 354 | | BATL_GUARDEDSTORAGE) |
3e3fffe3 | 355 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
357 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U | |
9553df86 JL |
358 | |
359 | /* | |
f3bceaab | 360 | * BAT2 16M Cache-inhibited, guarded |
9553df86 | 361 | * 0xe100_0000 1M PCI-1 I/O |
9553df86 JL |
362 | */ |
363 | ||
6d0f6bcf | 364 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 365 | | BATL_GUARDEDSTORAGE) |
3e3fffe3 | 366 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
368 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
9553df86 JL |
369 | |
370 | /* | |
104992fc BB |
371 | * BAT3 4M Cache-inhibited, guarded |
372 | * 0xe000_0000 4M CCSR | |
9553df86 JL |
373 | */ |
374 | ||
104992fc | 375 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 376 | | BATL_GUARDEDSTORAGE) |
104992fc BB |
377 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) |
378 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
6d0f6bcf | 379 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
9553df86 | 380 | |
f698738e JL |
381 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
382 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
383 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
384 | | BATL_GUARDEDSTORAGE) | |
385 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
386 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
387 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
388 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
389 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
390 | #endif | |
391 | ||
9553df86 | 392 | /* |
104992fc BB |
393 | * BAT4 32M Cache-inhibited, guarded |
394 | * 0xe200_0000 1M PCI-Express 2 I/O | |
395 | * 0xe300_0000 1M PCI-Express 1 I/O | |
9553df86 | 396 | */ |
104992fc BB |
397 | |
398 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
9553df86 | 399 | | BATL_GUARDEDSTORAGE) |
104992fc BB |
400 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) |
401 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
6d0f6bcf | 402 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
9553df86 | 403 | |
104992fc | 404 | |
9553df86 JL |
405 | /* |
406 | * BAT5 128K Cacheable, non-guarded | |
407 | * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
408 | */ | |
6d0f6bcf JCPV |
409 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
410 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
411 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
412 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
9553df86 JL |
413 | |
414 | /* | |
415 | * BAT6 256M Cache-inhibited, guarded | |
416 | * 0xf000_0000 256M FLASH | |
417 | */ | |
6d0f6bcf | 418 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 419 | | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
420 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
421 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) | |
422 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U | |
9553df86 | 423 | |
bf9a8c34 BB |
424 | /* Map the last 1M of flash where we're running from reset */ |
425 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
426 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
14d0a02a | 427 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
bf9a8c34 BB |
428 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
429 | | BATL_MEMCOHERENCE) | |
430 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
431 | ||
9553df86 JL |
432 | /* |
433 | * BAT7 4M Cache-inhibited, guarded | |
434 | * 0xe800_0000 4M PIXIS | |
435 | */ | |
6d0f6bcf | 436 | #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 437 | | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
438 | #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
439 | #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
440 | #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U | |
9553df86 JL |
441 | |
442 | ||
443 | /* | |
444 | * Environment | |
445 | */ | |
6d0f6bcf | 446 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 447 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 448 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
449 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ |
450 | #define CONFIG_ENV_SIZE 0x2000 | |
9553df86 | 451 | #else |
93f6d725 | 452 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 453 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 454 | #define CONFIG_ENV_SIZE 0x2000 |
9553df86 JL |
455 | #endif |
456 | ||
457 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 458 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9553df86 JL |
459 | |
460 | ||
461 | /* | |
462 | * BOOTP options | |
463 | */ | |
464 | #define CONFIG_BOOTP_BOOTFILESIZE | |
465 | #define CONFIG_BOOTP_BOOTPATH | |
466 | #define CONFIG_BOOTP_GATEWAY | |
467 | #define CONFIG_BOOTP_HOSTNAME | |
468 | ||
469 | ||
470 | /* | |
471 | * Command line configuration. | |
472 | */ | |
473 | #include <config_cmd_default.h> | |
474 | ||
475 | #define CONFIG_CMD_PING | |
476 | #define CONFIG_CMD_I2C | |
477 | #define CONFIG_CMD_MII | |
478 | ||
6d0f6bcf | 479 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 480 | #undef CONFIG_CMD_SAVEENV |
9553df86 JL |
481 | #endif |
482 | ||
483 | #if defined(CONFIG_PCI) | |
484 | #define CONFIG_CMD_PCI | |
485 | #define CONFIG_CMD_SCSI | |
486 | #define CONFIG_CMD_EXT2 | |
070ba561 | 487 | #define CONFIG_CMD_USB |
9553df86 JL |
488 | #endif |
489 | ||
490 | ||
3473ab73 | 491 | #define CONFIG_WATCHDOG /* watchdog enabled */ |
6d0f6bcf | 492 | #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ |
9553df86 JL |
493 | |
494 | /* | |
495 | * Miscellaneous configurable options | |
496 | */ | |
6d0f6bcf | 497 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6bee764b | 498 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf | 499 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
9553df86 JL |
500 | |
501 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 502 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9553df86 | 503 | #else |
6d0f6bcf | 504 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9553df86 JL |
505 | #endif |
506 | ||
6d0f6bcf JCPV |
507 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
508 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
509 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
9553df86 JL |
510 | |
511 | /* | |
512 | * For booting Linux, the board info and command line data | |
513 | * have to be in the first 8 MB of memory, since this is | |
514 | * the maximum mapped by the Linux kernel during initialization. | |
515 | */ | |
6d0f6bcf | 516 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
9553df86 | 517 | |
9553df86 JL |
518 | #if defined(CONFIG_CMD_KGDB) |
519 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
9553df86 JL |
520 | #endif |
521 | ||
522 | /* | |
523 | * Environment Configuration | |
524 | */ | |
525 | #define CONFIG_IPADDR 192.168.1.100 | |
526 | ||
527 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 528 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 529 | #define CONFIG_BOOTFILE "uImage" |
9553df86 JL |
530 | #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin |
531 | ||
532 | #define CONFIG_SERVERIP 192.168.1.1 | |
533 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
534 | #define CONFIG_NETMASK 255.255.255.0 | |
535 | ||
536 | /* default location for tftp and bootm */ | |
537 | #define CONFIG_LOADADDR 1000000 | |
538 | ||
539 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
540 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
541 | ||
542 | #define CONFIG_BAUDRATE 115200 | |
543 | ||
544 | #if defined(CONFIG_PCI1) | |
545 | #define PCI_ENV \ | |
546 | "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ | |
547 | "echo e;md ${a}e00 9\0" \ | |
548 | "pci1regs=setenv a e0008; run pcireg\0" \ | |
549 | "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ | |
550 | "pci d.w $b.0 56 1\0" \ | |
551 | "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ | |
552 | "pci w.w $b.0 56 ffff\0" \ | |
553 | "pci1err=setenv a e0008; run pcierr\0" \ | |
554 | "pci1errc=setenv a e0008; run pcierrc\0" | |
555 | #else | |
556 | #define PCI_ENV "" | |
557 | #endif | |
558 | ||
559 | #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) | |
560 | #define PCIE_ENV \ | |
561 | "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ | |
562 | "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ | |
563 | "pcie1regs=setenv a e000a; run pciereg\0" \ | |
564 | "pcie2regs=setenv a e0009; run pciereg\0" \ | |
565 | "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ | |
566 | "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ | |
567 | "pci d $b.0 130 1\0" \ | |
568 | "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ | |
569 | "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ | |
570 | "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ | |
571 | "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ | |
572 | "pcie1err=setenv a e000a; run pcieerr\0" \ | |
573 | "pcie2err=setenv a e0009; run pcieerr\0" \ | |
574 | "pcie1errc=setenv a e000a; run pcieerrc\0" \ | |
575 | "pcie2errc=setenv a e0009; run pcieerrc\0" | |
576 | #else | |
577 | #define PCIE_ENV "" | |
578 | #endif | |
579 | ||
580 | #define DMA_ENV \ | |
581 | "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ | |
582 | "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ | |
583 | "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ | |
584 | "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ | |
585 | "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ | |
586 | "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ | |
587 | "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ | |
588 | "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" | |
589 | ||
1815338f | 590 | #ifdef ENV_DEBUG |
9553df86 | 591 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
592 | "netdev=eth0\0" \ |
593 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
594 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
595 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
596 | " +$filesize; " \ | |
597 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
598 | " +$filesize; " \ | |
599 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
600 | " $filesize; " \ | |
601 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
602 | " +$filesize; " \ | |
603 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
604 | " $filesize\0" \ | |
605 | "consoledev=ttyS0\0" \ | |
606 | "ramdiskaddr=2000000\0" \ | |
607 | "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ | |
608 | "fdtaddr=c00000\0" \ | |
609 | "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ | |
610 | "bdev=sda3\0" \ | |
611 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ | |
612 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
613 | "maxcpus=1" \ | |
614 | "eoi=mw e00400b0 0\0" \ | |
615 | "iack=md e00400a0 1\0" \ | |
616 | "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ | |
9553df86 JL |
617 | "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ |
618 | "md ${a}f00 5\0" \ | |
5368c55d MV |
619 | "ddr1regs=setenv a e0002; run ddrreg\0" \ |
620 | "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ | |
9553df86 JL |
621 | "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ |
622 | "md ${a}e60 1; md ${a}ef0 1d\0" \ | |
5368c55d MV |
623 | "guregs=setenv a e00e0; run gureg\0" \ |
624 | "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ | |
625 | "mcmregs=setenv a e0001; run mcmreg\0" \ | |
626 | "diuregs=md e002c000 1d\0" \ | |
627 | "dium=mw e002c01c\0" \ | |
628 | "diuerr=md e002c014 1\0" \ | |
629 | "pmregs=md e00e1000 2b\0" \ | |
630 | "lawregs=md e0000c08 4b\0" \ | |
631 | "lbcregs=md e0005000 36\0" \ | |
632 | "dma0regs=md e0021100 12\0" \ | |
633 | "dma1regs=md e0021180 12\0" \ | |
634 | "dma2regs=md e0021200 12\0" \ | |
635 | "dma3regs=md e0021280 12\0" \ | |
9553df86 JL |
636 | PCI_ENV \ |
637 | PCIE_ENV \ | |
638 | DMA_ENV | |
1815338f | 639 | #else |
5368c55d MV |
640 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
641 | "netdev=eth0\0" \ | |
642 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
643 | "consoledev=ttyS0\0" \ | |
644 | "ramdiskaddr=2000000\0" \ | |
645 | "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ | |
646 | "fdtaddr=c00000\0" \ | |
647 | "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ | |
648 | "bdev=sda3\0" | |
1815338f | 649 | #endif |
9553df86 JL |
650 | |
651 | #define CONFIG_NFSBOOTCOMMAND \ | |
652 | "setenv bootargs root=/dev/nfs rw " \ | |
653 | "nfsroot=$serverip:$rootpath " \ | |
654 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
655 | "console=$consoledev,$baudrate $othbootargs;" \ | |
656 | "tftp $loadaddr $bootfile;" \ | |
1df170f8 JL |
657 | "tftp $fdtaddr $fdtfile;" \ |
658 | "bootm $loadaddr - $fdtaddr" | |
9553df86 JL |
659 | |
660 | #define CONFIG_RAMBOOTCOMMAND \ | |
661 | "setenv bootargs root=/dev/ram rw " \ | |
662 | "console=$consoledev,$baudrate $othbootargs;" \ | |
663 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
664 | "tftp $loadaddr $bootfile;" \ | |
1df170f8 JL |
665 | "tftp $fdtaddr $fdtfile;" \ |
666 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
9553df86 JL |
667 | |
668 | #define CONFIG_BOOTCOMMAND \ | |
669 | "setenv bootargs root=/dev/$bdev rw " \ | |
670 | "console=$consoledev,$baudrate $othbootargs;" \ | |
671 | "tftp $loadaddr $bootfile;" \ | |
1df170f8 JL |
672 | "tftp $fdtaddr $fdtfile;" \ |
673 | "bootm $loadaddr - $fdtaddr" | |
9553df86 JL |
674 | |
675 | #endif /* __CONFIG_H */ |