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5c9efb36 JL |
1 | /* |
2 | * Copyright 2006 Freescale Semiconductor. | |
3 | * | |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
5c9efb36 | 26 | * MPC8641HPCN board configuration file |
debb7354 JL |
27 | * |
28 | * Make sure you change the MAC address and other network params first, | |
29 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
30 | */ | |
31 | ||
32 | #ifndef __CONFIG_H | |
33 | #define __CONFIG_H | |
34 | ||
35 | /* High Level Configuration Options */ | |
36 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
37 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
38 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
39 | #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ | |
40 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
5c9efb36 | 41 | #undef DEBUG |
debb7354 | 42 | |
debb7354 JL |
43 | #ifdef RUN_DIAG |
44 | #define CFG_DIAG_ADDR 0xff800000 | |
45 | #endif | |
5c9efb36 | 46 | |
debb7354 JL |
47 | #define CFG_RESET_ADDRESS 0xfff00100 |
48 | ||
fa7db9c3 JZR |
49 | /*#undef CONFIG_PCI*/ |
50 | #define CONFIG_PCI | |
5c9efb36 | 51 | |
debb7354 JL |
52 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
53 | #define CONFIG_ENV_OVERWRITE | |
debb7354 | 54 | |
18b6c8cd | 55 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
5c9efb36 JL |
56 | #undef CONFIG_DDR_DLL /* possible DLL fix needed */ |
57 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
debb7354 JL |
58 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ |
59 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
60 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9a655876 JL |
61 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
62 | /* #define CONFIG_DDR_INTERLEAVE 1 */ | |
63 | #define CACHE_LINE_INTERLEAVING 0x20000000 | |
64 | #define PAGE_INTERLEAVING 0x21000000 | |
65 | #define BANK_INTERLEAVING 0x22000000 | |
66 | #define SUPER_BANK_INTERLEAVING 0x23000000 | |
67 | ||
debb7354 | 68 | |
5c9efb36 | 69 | #define CONFIG_ALTIVEC 1 |
debb7354 | 70 | |
5c9efb36 | 71 | /* |
debb7354 JL |
72 | * L2CR setup -- make sure this is right for your board! |
73 | */ | |
5c9efb36 | 74 | #define CFG_L2 |
debb7354 JL |
75 | #define L2_INIT 0 |
76 | #define L2_ENABLE (L2CR_L2E) | |
77 | ||
78 | #ifndef CONFIG_SYS_CLK_FREQ | |
debb7354 JL |
79 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
80 | #endif | |
81 | ||
debb7354 JL |
82 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
83 | ||
84 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
85 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
86 | #define CFG_MEMTEST_END 0x00400000 | |
87 | ||
debb7354 JL |
88 | /* |
89 | * Base addresses -- Note these are effective addresses where the | |
90 | * actual resources get mapped (not physical addresses) | |
91 | */ | |
92 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
93 | #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ | |
94 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
95 | ||
debb7354 JL |
96 | /* |
97 | * DDR Setup | |
98 | */ | |
99 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
100 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
fcb28e76 | 101 | #define CONFIG_VERY_BIG_RAM |
debb7354 JL |
102 | |
103 | #define MPC86xx_DDR_SDRAM_CLK_CNTL | |
104 | ||
105 | #if defined(CONFIG_SPD_EEPROM) | |
106 | /* | |
107 | * Determine DDR configuration from I2C interface. | |
108 | */ | |
9a655876 JL |
109 | #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ |
110 | #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ | |
111 | #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ | |
112 | #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ | |
debb7354 JL |
113 | |
114 | #else | |
115 | /* | |
18b6c8cd | 116 | * Manually set up DDR1 parameters |
debb7354 JL |
117 | */ |
118 | ||
debb7354 JL |
119 | #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ |
120 | ||
121 | #define CFG_DDR_CS0_BNDS 0x0000000F | |
122 | #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
123 | #define CFG_DDR_EXT_REFRESH 0x00000000 | |
124 | #define CFG_DDR_TIMING_0 0x00260802 | |
125 | #define CFG_DDR_TIMING_1 0x39357322 | |
126 | #define CFG_DDR_TIMING_2 0x14904cc8 | |
127 | #define CFG_DDR_MODE_1 0x00480432 | |
128 | #define CFG_DDR_MODE_2 0x00000000 | |
129 | #define CFG_DDR_INTERVAL 0x06090100 | |
130 | #define CFG_DDR_DATA_INIT 0xdeadbeef | |
131 | #define CFG_DDR_CLK_CTRL 0x03800000 | |
5c9efb36 JL |
132 | #define CFG_DDR_OCD_CTRL 0x00000000 |
133 | #define CFG_DDR_OCD_STATUS 0x00000000 | |
debb7354 | 134 | #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ |
5c9efb36 | 135 | #define CFG_DDR_CONTROL2 0x04400000 |
debb7354 | 136 | |
18b6c8cd | 137 | /* Not used in fixed_sdram function */ |
debb7354 JL |
138 | |
139 | #define CFG_DDR_MODE 0x00000022 | |
140 | #define CFG_DDR_CS1_BNDS 0x00000000 | |
18b6c8cd JL |
141 | #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ |
142 | #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ | |
143 | #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ | |
144 | #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ | |
debb7354 JL |
145 | #endif |
146 | ||
bea3f28d HW |
147 | #define CFG_ID_EEPROM 1 |
148 | #define ID_EEPROM_ADDR 0x57 | |
debb7354 JL |
149 | |
150 | /* | |
586d1d5a JL |
151 | * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. |
152 | * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff | |
debb7354 JL |
153 | * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. |
154 | * However, when u-boot comes up, the flash_init needs hard start addresses | |
586d1d5a JL |
155 | * to build its info table. For user convenience, the flash addresses is |
156 | * fe800000 and ff800000. That way, u-boot knows where the flash is | |
157 | * and the user can download u-boot code from promjet to fef00000, a | |
158 | * more intuitive location than fe700000. | |
159 | * | |
160 | * Note that, on switching the boot location, fef00000 becomes fff00000. | |
5c9efb36 | 161 | */ |
debb7354 | 162 | #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ |
5c9efb36 | 163 | #define CFG_FLASH_BASE2 0xff800000 |
debb7354 JL |
164 | |
165 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} | |
166 | ||
debb7354 JL |
167 | #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ |
168 | #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ | |
169 | ||
170 | #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ | |
171 | #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ | |
172 | ||
173 | #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ | |
174 | #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
175 | ||
176 | #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ | |
177 | #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
178 | ||
debb7354 | 179 | |
5c9efb36 JL |
180 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
181 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
182 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
183 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
184 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
185 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
186 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
187 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
188 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
189 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
190 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
191 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
192 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
193 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
194 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
debb7354 JL |
195 | |
196 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
debb7354 JL |
197 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
198 | ||
199 | #undef CFG_FLASH_CHECKSUM | |
200 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
201 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
202 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
203 | ||
18b6c8cd | 204 | #define CFG_FLASH_CFI_DRIVER |
debb7354 JL |
205 | #define CFG_FLASH_CFI |
206 | #define CFG_FLASH_EMPTY_INFO | |
207 | ||
debb7354 JL |
208 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
209 | #define CFG_RAMBOOT | |
210 | #else | |
211 | #undef CFG_RAMBOOT | |
212 | #endif | |
213 | ||
fa7db9c3 | 214 | #if defined(CFG_RAMBOOT) |
fa7db9c3 JZR |
215 | #undef CONFIG_SPD_EEPROM |
216 | #define CFG_SDRAM_SIZE 256 | |
debb7354 JL |
217 | #endif |
218 | ||
219 | #undef CONFIG_CLOCKS_IN_MHZ | |
220 | ||
221 | #define CONFIG_L1_INIT_RAM | |
18b6c8cd | 222 | #define CFG_INIT_RAM_LOCK 1 |
debb7354 JL |
223 | #ifndef CFG_INIT_RAM_LOCK |
224 | #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
225 | #else | |
226 | #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ | |
227 | #endif | |
228 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
229 | ||
230 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
231 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
232 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
233 | ||
234 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
235 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
236 | ||
237 | /* Serial Port */ | |
238 | #define CONFIG_CONS_INDEX 1 | |
239 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
240 | #define CFG_NS16550 | |
241 | #define CFG_NS16550_SERIAL | |
242 | #define CFG_NS16550_REG_SIZE 1 | |
243 | #define CFG_NS16550_CLK get_bus_freq(0) | |
244 | ||
245 | #define CFG_BAUDRATE_TABLE \ | |
246 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
247 | ||
248 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
249 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
250 | ||
251 | /* Use the HUSH parser */ | |
252 | #define CFG_HUSH_PARSER | |
253 | #ifdef CFG_HUSH_PARSER | |
254 | #define CFG_PROMPT_HUSH_PS2 "> " | |
255 | #endif | |
256 | ||
5c9efb36 JL |
257 | /* |
258 | * Pass open firmware flat tree to kernel | |
259 | */ | |
260 | #define CONFIG_OF_FLAT_TREE 1 | |
261 | #define CONFIG_OF_BOARD_SETUP 1 | |
debb7354 JL |
262 | |
263 | /* maximum size of the flat tree (8K) */ | |
5c9efb36 | 264 | #define OF_FLAT_TREE_MAX_SIZE 8192 |
debb7354 | 265 | |
5c9efb36 JL |
266 | #define OF_CPU "PowerPC,8641@0" |
267 | #define OF_SOC "soc8641@f8000000" | |
515ab8a6 | 268 | #define OF_TBCLK (bd->bi_busfreq / 4) |
5c9efb36 | 269 | #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" |
debb7354 | 270 | |
5c9efb36 JL |
271 | #define CFG_64BIT_VSPRINTF 1 |
272 | #define CFG_64BIT_STRTOUL 1 | |
debb7354 | 273 | |
586d1d5a JL |
274 | /* |
275 | * I2C | |
276 | */ | |
20476726 JL |
277 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
278 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
debb7354 JL |
279 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
280 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
281 | #define CFG_I2C_SLAVE 0x7F | |
282 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
20476726 | 283 | #define CFG_I2C_OFFSET 0x3100 |
debb7354 | 284 | |
586d1d5a JL |
285 | /* |
286 | * RapidIO MMU | |
287 | */ | |
debb7354 JL |
288 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ |
289 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
290 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
291 | ||
292 | /* | |
293 | * General PCI | |
294 | * Addresses are mapped 1-1. | |
295 | */ | |
296 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
debb7354 JL |
297 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
298 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
299 | #define CFG_PCI1_IO_BASE 0xe2000000 | |
debb7354 | 300 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
debb7354 JL |
301 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
302 | ||
fa7db9c3 JZR |
303 | /* PCI view of System Memory */ |
304 | #define CFG_PCI_MEMORY_BUS 0x00000000 | |
305 | #define CFG_PCI_MEMORY_PHYS 0x00000000 | |
306 | #define CFG_PCI_MEMORY_SIZE 0x80000000 | |
307 | ||
debb7354 | 308 | /* For RTL8139 */ |
bc09cf3c | 309 | #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) |
debb7354 JL |
310 | #define _IO_BASE 0x00000000 |
311 | ||
312 | #define CFG_PCI2_MEM_BASE 0xa0000000 | |
313 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
314 | #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
315 | #define CFG_PCI2_IO_BASE 0xe3000000 | |
316 | #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE | |
317 | #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ | |
318 | ||
debb7354 JL |
319 | #if defined(CONFIG_PCI) |
320 | ||
debb7354 JL |
321 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
322 | ||
5c9efb36 | 323 | #undef CFG_SCSI_SCAN_BUS_REVERSE |
debb7354 JL |
324 | |
325 | #define CONFIG_NET_MULTI | |
326 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
327 | ||
328 | #define CONFIG_RTL8139 | |
329 | ||
debb7354 JL |
330 | #undef CONFIG_EEPRO100 |
331 | #undef CONFIG_TULIP | |
332 | ||
333 | #if !defined(CONFIG_PCI_PNP) | |
334 | #define PCI_ENET0_IOADDR 0xe0000000 | |
335 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
336 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
337 | #endif | |
338 | ||
339 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
debb7354 | 340 | |
dabf9ef8 JZ |
341 | #define CONFIG_DOS_PARTITION |
342 | #define CONFIG_SCSI_AHCI | |
343 | ||
344 | #ifdef CONFIG_SCSI_AHCI | |
345 | #define CONFIG_SATA_ULI5288 | |
346 | #define CFG_SCSI_MAX_SCSI_ID 4 | |
347 | #define CFG_SCSI_MAX_LUN 1 | |
348 | #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) | |
349 | #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE | |
350 | #endif | |
351 | ||
debb7354 JL |
352 | #endif /* CONFIG_PCI */ |
353 | ||
debb7354 JL |
354 | #if defined(CONFIG_TSEC_ENET) |
355 | ||
356 | #ifndef CONFIG_NET_MULTI | |
357 | #define CONFIG_NET_MULTI 1 | |
358 | #endif | |
359 | ||
360 | #define CONFIG_MII 1 /* MII PHY management */ | |
361 | ||
362 | #define CONFIG_MPC86XX_TSEC1 1 | |
363 | #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" | |
364 | #define CONFIG_MPC86XX_TSEC2 1 | |
365 | #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" | |
366 | #define CONFIG_MPC86XX_TSEC3 1 | |
367 | #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" | |
368 | #define CONFIG_MPC86XX_TSEC4 1 | |
369 | #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" | |
370 | ||
debb7354 JL |
371 | #define TSEC1_PHY_ADDR 0 |
372 | #define TSEC2_PHY_ADDR 1 | |
373 | #define TSEC3_PHY_ADDR 2 | |
374 | #define TSEC4_PHY_ADDR 3 | |
375 | #define TSEC1_PHYIDX 0 | |
376 | #define TSEC2_PHYIDX 0 | |
377 | #define TSEC3_PHYIDX 0 | |
378 | #define TSEC4_PHYIDX 0 | |
379 | ||
380 | #define CONFIG_ETHPRIME "eTSEC1" | |
381 | ||
382 | #endif /* CONFIG_TSEC_ENET */ | |
383 | ||
586d1d5a JL |
384 | /* |
385 | * BAT0 2G Cacheable, non-guarded | |
debb7354 JL |
386 | * 0x0000_0000 2G DDR |
387 | */ | |
fecf1c7e JL |
388 | #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
389 | #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
390 | #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) | |
debb7354 JL |
391 | #define CFG_IBAT0U CFG_DBAT0U |
392 | ||
586d1d5a JL |
393 | /* |
394 | * BAT1 1G Cache-inhibited, guarded | |
debb7354 JL |
395 | * 0x8000_0000 512M PCI-Express 1 Memory |
396 | * 0xa000_0000 512M PCI-Express 2 Memory | |
586d1d5a | 397 | * Changed it for operating from 0xd0000000 |
debb7354 | 398 | */ |
5c9efb36 JL |
399 | #define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ |
400 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
debb7354 JL |
401 | #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
402 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
403 | #define CFG_IBAT1U CFG_DBAT1U | |
404 | ||
586d1d5a JL |
405 | /* |
406 | * BAT2 512M Cache-inhibited, guarded | |
debb7354 JL |
407 | * 0xc000_0000 512M RapidIO Memory |
408 | */ | |
5c9efb36 JL |
409 | #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ |
410 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
debb7354 JL |
411 | #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) |
412 | #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
413 | #define CFG_IBAT2U CFG_DBAT2U | |
414 | ||
586d1d5a JL |
415 | /* |
416 | * BAT3 4M Cache-inhibited, guarded | |
debb7354 JL |
417 | * 0xf800_0000 4M CCSR |
418 | */ | |
5c9efb36 JL |
419 | #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ |
420 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
debb7354 JL |
421 | #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
422 | #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
423 | #define CFG_IBAT3U CFG_DBAT3U | |
424 | ||
586d1d5a JL |
425 | /* |
426 | * BAT4 32M Cache-inhibited, guarded | |
debb7354 JL |
427 | * 0xe200_0000 16M PCI-Express 1 I/O |
428 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
586d1d5a | 429 | * Note that this is at 0xe0000000 |
debb7354 | 430 | */ |
5c9efb36 JL |
431 | #define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ |
432 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
debb7354 JL |
433 | #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) |
434 | #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
435 | #define CFG_IBAT4U CFG_DBAT4U | |
436 | ||
586d1d5a JL |
437 | /* |
438 | * BAT5 128K Cacheable, non-guarded | |
debb7354 JL |
439 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) |
440 | */ | |
441 | #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
442 | #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
443 | #define CFG_IBAT5L CFG_DBAT5L | |
444 | #define CFG_IBAT5U CFG_DBAT5U | |
445 | ||
586d1d5a JL |
446 | /* |
447 | * BAT6 32M Cache-inhibited, guarded | |
debb7354 JL |
448 | * 0xfe00_0000 32M FLASH |
449 | */ | |
fa7db9c3 | 450 | #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ |
5c9efb36 | 451 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
fa7db9c3 JZR |
452 | #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) |
453 | #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) | |
debb7354 JL |
454 | #define CFG_IBAT6U CFG_DBAT6U |
455 | ||
debb7354 JL |
456 | #define CFG_DBAT7L 0x00000000 |
457 | #define CFG_DBAT7U 0x00000000 | |
458 | #define CFG_IBAT7L 0x00000000 | |
459 | #define CFG_IBAT7U 0x00000000 | |
460 | ||
debb7354 JL |
461 | /* |
462 | * Environment | |
463 | */ | |
5c9efb36 JL |
464 | #ifndef CFG_RAMBOOT |
465 | #define CFG_ENV_IS_IN_FLASH 1 | |
466 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
586d1d5a | 467 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
5c9efb36 JL |
468 | #define CFG_ENV_SIZE 0x2000 |
469 | #else | |
5c9efb36 JL |
470 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
471 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
472 | #define CFG_ENV_SIZE 0x2000 | |
473 | #endif | |
debb7354 JL |
474 | |
475 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
476 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
477 | ||
478 | #if defined(CFG_RAMBOOT) | |
479 | #if defined(CONFIG_PCI) | |
480 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | |
481 | | CFG_CMD_PING \ | |
482 | | CFG_CMD_PCI \ | |
dabf9ef8 JZ |
483 | | CFG_CMD_I2C \ |
484 | | CFG_CMD_SCSI \ | |
485 | | CFG_CMD_EXT2) \ | |
debb7354 | 486 | & \ |
5a58a73c | 487 | ~(CFG_CMD_ENV)) |
debb7354 JL |
488 | #else |
489 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | |
490 | | CFG_CMD_PING \ | |
5a58a73c | 491 | | CFG_CMD_I2C) \ |
debb7354 | 492 | & \ |
5a58a73c | 493 | ~(CFG_CMD_ENV)) |
debb7354 JL |
494 | #endif |
495 | #else | |
496 | #if defined(CONFIG_PCI) | |
497 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
498 | | CFG_CMD_PCI \ | |
499 | | CFG_CMD_PING \ | |
dabf9ef8 JZ |
500 | | CFG_CMD_I2C \ |
501 | | CFG_CMD_SCSI \ | |
502 | | CFG_CMD_EXT2) | |
debb7354 JL |
503 | #else |
504 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
505 | | CFG_CMD_PING \ | |
506 | | CFG_CMD_I2C) | |
507 | #endif | |
508 | #endif | |
509 | ||
510 | #include <cmd_confdefs.h> | |
511 | ||
512 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
513 | ||
514 | /* | |
515 | * Miscellaneous configurable options | |
516 | */ | |
517 | #define CFG_LONGHELP /* undef to save memory */ | |
518 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
519 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
520 | ||
521 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
522 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
523 | #else | |
524 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
525 | #endif | |
526 | ||
527 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
528 | #define CFG_MAXARGS 16 /* max number of command args */ | |
529 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
530 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
531 | ||
532 | /* | |
533 | * For booting Linux, the board info and command line data | |
534 | * have to be in the first 8 MB of memory, since this is | |
535 | * the maximum mapped by the Linux kernel during initialization. | |
536 | */ | |
537 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
538 | ||
539 | /* Cache Configuration */ | |
540 | #define CFG_DCACHE_SIZE 32768 | |
541 | #define CFG_CACHELINE_SIZE 32 | |
542 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
543 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ | |
544 | #endif | |
545 | ||
546 | /* | |
547 | * Internal Definitions | |
548 | * | |
549 | * Boot Flags | |
550 | */ | |
551 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
552 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
553 | ||
554 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
555 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
556 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
557 | #endif | |
558 | ||
debb7354 JL |
559 | /* |
560 | * Environment Configuration | |
561 | */ | |
562 | ||
563 | /* The mac addresses for all ethernet interface */ | |
564 | #if defined(CONFIG_TSEC_ENET) | |
565 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 | |
566 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD | |
567 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
568 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
569 | #endif | |
570 | ||
5c9efb36 JL |
571 | #define CONFIG_HAS_ETH1 1 |
572 | #define CONFIG_HAS_ETH2 1 | |
573 | #define CONFIG_HAS_ETH3 1 | |
debb7354 | 574 | |
18b6c8cd | 575 | #define CONFIG_IPADDR 192.168.1.100 |
debb7354 JL |
576 | |
577 | #define CONFIG_HOSTNAME unknown | |
578 | #define CONFIG_ROOTPATH /opt/nfsroot | |
579 | #define CONFIG_BOOTFILE uImage | |
580 | ||
5c9efb36 | 581 | #define CONFIG_SERVERIP 192.168.1.1 |
18b6c8cd | 582 | #define CONFIG_GATEWAYIP 192.168.1.1 |
5c9efb36 | 583 | #define CONFIG_NETMASK 255.255.255.0 |
debb7354 | 584 | |
5c9efb36 JL |
585 | /* default location for tftp and bootm */ |
586 | #define CONFIG_LOADADDR 1000000 | |
debb7354 JL |
587 | |
588 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
18b6c8cd | 589 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
debb7354 JL |
590 | |
591 | #define CONFIG_BAUDRATE 115200 | |
592 | ||
593 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
594 | "netdev=eth0\0" \ | |
595 | "consoledev=ttyS0\0" \ | |
5567806b | 596 | "ramdiskaddr=2000000\0" \ |
debb7354 | 597 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
5567806b | 598 | "dtbaddr=400000\0" \ |
d8ea2acf | 599 | "dtbfile=mpc8641_hpcn.dtb\0" \ |
debb7354 JL |
600 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ |
601 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
602 | "maxcpus=2" | |
603 | ||
604 | ||
605 | #define CONFIG_NFSBOOTCOMMAND \ | |
606 | "setenv bootargs root=/dev/nfs rw " \ | |
607 | "nfsroot=$serverip:$rootpath " \ | |
608 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
609 | "console=$consoledev,$baudrate $othbootargs;" \ | |
610 | "tftp $loadaddr $bootfile;" \ | |
d8ea2acf ZW |
611 | "tftp $dtbaddr $dtbfile;" \ |
612 | "bootm $loadaddr - $dtbaddr" | |
debb7354 JL |
613 | |
614 | #define CONFIG_RAMBOOTCOMMAND \ | |
615 | "setenv bootargs root=/dev/ram rw " \ | |
616 | "console=$consoledev,$baudrate $othbootargs;" \ | |
617 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
618 | "tftp $loadaddr $bootfile;" \ | |
d8ea2acf ZW |
619 | "tftp $dtbaddr $dtbfile;" \ |
620 | "bootm $loadaddr $ramdiskaddr $dtbaddr" | |
debb7354 JL |
621 | |
622 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
623 | ||
624 | #endif /* __CONFIG_H */ |