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5c9efb36 JL |
1 | /* |
2 | * Copyright 2006 Freescale Semiconductor. | |
3 | * | |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
5c9efb36 | 26 | * MPC8641HPCN board configuration file |
debb7354 JL |
27 | * |
28 | * Make sure you change the MAC address and other network params first, | |
29 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
30 | */ | |
31 | ||
32 | #ifndef __CONFIG_H | |
33 | #define __CONFIG_H | |
34 | ||
35 | /* High Level Configuration Options */ | |
36 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
37 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
38 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
39 | #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ | |
40 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
debb7354 | 41 | |
debb7354 JL |
42 | #ifdef RUN_DIAG |
43 | #define CFG_DIAG_ADDR 0xff800000 | |
44 | #endif | |
5c9efb36 | 45 | |
debb7354 JL |
46 | #define CFG_RESET_ADDRESS 0xfff00100 |
47 | ||
63cec581 ES |
48 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
49 | #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ | |
50 | #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ | |
51 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
4933b91f | 52 | #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ |
5c9efb36 | 53 | |
debb7354 JL |
54 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
55 | #define CONFIG_ENV_OVERWRITE | |
debb7354 | 56 | |
18b6c8cd | 57 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
5c9efb36 JL |
58 | #undef CONFIG_DDR_DLL /* possible DLL fix needed */ |
59 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
debb7354 JL |
60 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ |
61 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
62 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9a655876 JL |
63 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
64 | /* #define CONFIG_DDR_INTERLEAVE 1 */ | |
65 | #define CACHE_LINE_INTERLEAVING 0x20000000 | |
66 | #define PAGE_INTERLEAVING 0x21000000 | |
67 | #define BANK_INTERLEAVING 0x22000000 | |
68 | #define SUPER_BANK_INTERLEAVING 0x23000000 | |
69 | ||
debb7354 | 70 | |
5c9efb36 | 71 | #define CONFIG_ALTIVEC 1 |
debb7354 | 72 | |
5c9efb36 | 73 | /* |
debb7354 JL |
74 | * L2CR setup -- make sure this is right for your board! |
75 | */ | |
5c9efb36 | 76 | #define CFG_L2 |
debb7354 JL |
77 | #define L2_INIT 0 |
78 | #define L2_ENABLE (L2CR_L2E) | |
79 | ||
80 | #ifndef CONFIG_SYS_CLK_FREQ | |
63cec581 ES |
81 | #ifndef __ASSEMBLY__ |
82 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
83 | #endif | |
debb7354 JL |
84 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
85 | #endif | |
86 | ||
debb7354 JL |
87 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
88 | ||
89 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
90 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
91 | #define CFG_MEMTEST_END 0x00400000 | |
92 | ||
debb7354 JL |
93 | /* |
94 | * Base addresses -- Note these are effective addresses where the | |
95 | * actual resources get mapped (not physical addresses) | |
96 | */ | |
97 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
98 | #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ | |
99 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
100 | ||
63cec581 ES |
101 | #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) |
102 | #define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) | |
103 | ||
debb7354 JL |
104 | /* |
105 | * DDR Setup | |
106 | */ | |
107 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
108 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
fcb28e76 | 109 | #define CONFIG_VERY_BIG_RAM |
debb7354 JL |
110 | |
111 | #define MPC86xx_DDR_SDRAM_CLK_CNTL | |
112 | ||
113 | #if defined(CONFIG_SPD_EEPROM) | |
114 | /* | |
115 | * Determine DDR configuration from I2C interface. | |
116 | */ | |
9a655876 JL |
117 | #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ |
118 | #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ | |
119 | #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ | |
120 | #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ | |
debb7354 JL |
121 | |
122 | #else | |
123 | /* | |
18b6c8cd | 124 | * Manually set up DDR1 parameters |
debb7354 JL |
125 | */ |
126 | ||
debb7354 JL |
127 | #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ |
128 | ||
129 | #define CFG_DDR_CS0_BNDS 0x0000000F | |
130 | #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
131 | #define CFG_DDR_EXT_REFRESH 0x00000000 | |
132 | #define CFG_DDR_TIMING_0 0x00260802 | |
133 | #define CFG_DDR_TIMING_1 0x39357322 | |
134 | #define CFG_DDR_TIMING_2 0x14904cc8 | |
135 | #define CFG_DDR_MODE_1 0x00480432 | |
136 | #define CFG_DDR_MODE_2 0x00000000 | |
137 | #define CFG_DDR_INTERVAL 0x06090100 | |
138 | #define CFG_DDR_DATA_INIT 0xdeadbeef | |
139 | #define CFG_DDR_CLK_CTRL 0x03800000 | |
5c9efb36 JL |
140 | #define CFG_DDR_OCD_CTRL 0x00000000 |
141 | #define CFG_DDR_OCD_STATUS 0x00000000 | |
debb7354 | 142 | #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ |
5c9efb36 | 143 | #define CFG_DDR_CONTROL2 0x04400000 |
debb7354 | 144 | |
18b6c8cd | 145 | /* Not used in fixed_sdram function */ |
debb7354 JL |
146 | |
147 | #define CFG_DDR_MODE 0x00000022 | |
148 | #define CFG_DDR_CS1_BNDS 0x00000000 | |
18b6c8cd JL |
149 | #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ |
150 | #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ | |
151 | #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ | |
152 | #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ | |
debb7354 JL |
153 | #endif |
154 | ||
bea3f28d | 155 | #define CFG_ID_EEPROM 1 |
ad8f8687 JL |
156 | #ifdef CFG_ID_EEPROM |
157 | #define CONFIG_ID_EEPROM | |
158 | #endif | |
bea3f28d | 159 | #define ID_EEPROM_ADDR 0x57 |
debb7354 JL |
160 | |
161 | /* | |
586d1d5a JL |
162 | * In MPC8641HPCN, allocate 16MB flash spaces at fe000000 and ff000000. |
163 | * There is an 8MB flash. In effect, the addresses from fe000000 to fe7fffff | |
debb7354 JL |
164 | * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. |
165 | * However, when u-boot comes up, the flash_init needs hard start addresses | |
586d1d5a JL |
166 | * to build its info table. For user convenience, the flash addresses is |
167 | * fe800000 and ff800000. That way, u-boot knows where the flash is | |
168 | * and the user can download u-boot code from promjet to fef00000, a | |
169 | * more intuitive location than fe700000. | |
170 | * | |
171 | * Note that, on switching the boot location, fef00000 becomes fff00000. | |
5c9efb36 | 172 | */ |
debb7354 | 173 | #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ |
5c9efb36 | 174 | #define CFG_FLASH_BASE2 0xff800000 |
debb7354 JL |
175 | |
176 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} | |
177 | ||
debb7354 JL |
178 | #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ |
179 | #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ | |
180 | ||
181 | #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ | |
182 | #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ | |
183 | ||
184 | #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ | |
185 | #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
186 | ||
187 | #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ | |
188 | #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
189 | ||
debb7354 | 190 | |
7608d75f | 191 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
5c9efb36 JL |
192 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ |
193 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
194 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
195 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
196 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
197 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
198 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
199 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
200 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
201 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
202 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
203 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
204 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
205 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
206 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
9f23ca33 | 207 | #define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
debb7354 JL |
208 | |
209 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
debb7354 JL |
210 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
211 | ||
212 | #undef CFG_FLASH_CHECKSUM | |
213 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
214 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
215 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
216 | ||
18b6c8cd | 217 | #define CFG_FLASH_CFI_DRIVER |
debb7354 JL |
218 | #define CFG_FLASH_CFI |
219 | #define CFG_FLASH_EMPTY_INFO | |
220 | ||
debb7354 JL |
221 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
222 | #define CFG_RAMBOOT | |
223 | #else | |
224 | #undef CFG_RAMBOOT | |
225 | #endif | |
226 | ||
fa7db9c3 | 227 | #if defined(CFG_RAMBOOT) |
fa7db9c3 JZR |
228 | #undef CONFIG_SPD_EEPROM |
229 | #define CFG_SDRAM_SIZE 256 | |
debb7354 JL |
230 | #endif |
231 | ||
232 | #undef CONFIG_CLOCKS_IN_MHZ | |
233 | ||
234 | #define CONFIG_L1_INIT_RAM | |
18b6c8cd | 235 | #define CFG_INIT_RAM_LOCK 1 |
debb7354 JL |
236 | #ifndef CFG_INIT_RAM_LOCK |
237 | #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
238 | #else | |
239 | #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ | |
240 | #endif | |
241 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
242 | ||
243 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
244 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
245 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
246 | ||
247 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
0f460a1e | 248 | #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
debb7354 JL |
249 | |
250 | /* Serial Port */ | |
251 | #define CONFIG_CONS_INDEX 1 | |
252 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
253 | #define CFG_NS16550 | |
254 | #define CFG_NS16550_SERIAL | |
255 | #define CFG_NS16550_REG_SIZE 1 | |
256 | #define CFG_NS16550_CLK get_bus_freq(0) | |
257 | ||
258 | #define CFG_BAUDRATE_TABLE \ | |
259 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
260 | ||
261 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
262 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
263 | ||
264 | /* Use the HUSH parser */ | |
265 | #define CFG_HUSH_PARSER | |
266 | #ifdef CFG_HUSH_PARSER | |
267 | #define CFG_PROMPT_HUSH_PS2 "> " | |
268 | #endif | |
269 | ||
5c9efb36 JL |
270 | /* |
271 | * Pass open firmware flat tree to kernel | |
272 | */ | |
ea9f7395 JL |
273 | #define CONFIG_OF_LIBFDT 1 |
274 | #define CONFIG_OF_BOARD_SETUP 1 | |
275 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
debb7354 | 276 | |
debb7354 | 277 | |
5c9efb36 JL |
278 | #define CFG_64BIT_VSPRINTF 1 |
279 | #define CFG_64BIT_STRTOUL 1 | |
debb7354 | 280 | |
586d1d5a JL |
281 | /* |
282 | * I2C | |
283 | */ | |
20476726 JL |
284 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
285 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
debb7354 JL |
286 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
287 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
288 | #define CFG_I2C_SLAVE 0x7F | |
289 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
20476726 | 290 | #define CFG_I2C_OFFSET 0x3100 |
debb7354 | 291 | |
586d1d5a JL |
292 | /* |
293 | * RapidIO MMU | |
294 | */ | |
debb7354 JL |
295 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ |
296 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
297 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
298 | ||
299 | /* | |
300 | * General PCI | |
301 | * Addresses are mapped 1-1. | |
302 | */ | |
303 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
debb7354 JL |
304 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
305 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
63cec581 ES |
306 | #define CFG_PCI1_IO_BASE 0x00000000 |
307 | #define CFG_PCI1_IO_PHYS 0xe2000000 | |
308 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
debb7354 | 309 | |
fa7db9c3 JZR |
310 | /* PCI view of System Memory */ |
311 | #define CFG_PCI_MEMORY_BUS 0x00000000 | |
312 | #define CFG_PCI_MEMORY_PHYS 0x00000000 | |
313 | #define CFG_PCI_MEMORY_SIZE 0x80000000 | |
314 | ||
debb7354 | 315 | /* For RTL8139 */ |
bc09cf3c | 316 | #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) |
debb7354 JL |
317 | #define _IO_BASE 0x00000000 |
318 | ||
319 | #define CFG_PCI2_MEM_BASE 0xa0000000 | |
320 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
63cec581 ES |
321 | #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
322 | #define CFG_PCI2_IO_BASE 0x00000000 | |
323 | #define CFG_PCI2_IO_PHYS 0xe3000000 | |
324 | #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
debb7354 | 325 | |
debb7354 JL |
326 | #if defined(CONFIG_PCI) |
327 | ||
debb7354 JL |
328 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
329 | ||
5c9efb36 | 330 | #undef CFG_SCSI_SCAN_BUS_REVERSE |
debb7354 JL |
331 | |
332 | #define CONFIG_NET_MULTI | |
333 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
334 | ||
335 | #define CONFIG_RTL8139 | |
336 | ||
debb7354 JL |
337 | #undef CONFIG_EEPRO100 |
338 | #undef CONFIG_TULIP | |
339 | ||
a81d1c0b ZW |
340 | /************************************************************ |
341 | * USB support | |
342 | ************************************************************/ | |
343 | #define CONFIG_PCI_OHCI 1 | |
344 | #define CONFIG_USB_OHCI_NEW 1 | |
345 | #define CONFIG_USB_KEYBOARD 1 | |
346 | #define CFG_DEVICE_DEREGISTER | |
347 | #define CFG_USB_EVENT_POLL 1 | |
348 | #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" | |
349 | #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 | |
bbf4796f | 350 | #define CFG_OHCI_SWAP_REG_ACCESS 1 |
a81d1c0b | 351 | |
debb7354 JL |
352 | #if !defined(CONFIG_PCI_PNP) |
353 | #define PCI_ENET0_IOADDR 0xe0000000 | |
354 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
355 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
356 | #endif | |
357 | ||
0f460a1e JJ |
358 | /*PCIE video card used*/ |
359 | #define VIDEO_IO_OFFSET CFG_PCI2_IO_PHYS | |
360 | ||
361 | /*PCI video card used*/ | |
362 | /*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ | |
363 | ||
364 | /* video */ | |
365 | #define CONFIG_VIDEO | |
366 | ||
367 | #if defined(CONFIG_VIDEO) | |
368 | #define CONFIG_BIOSEMU | |
369 | #define CONFIG_CFB_CONSOLE | |
370 | #define CONFIG_VIDEO_SW_CURSOR | |
371 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
372 | #define CONFIG_ATI_RADEON_FB | |
373 | #define CONFIG_VIDEO_LOGO | |
374 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
375 | #define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS | |
376 | #endif | |
377 | ||
debb7354 | 378 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
debb7354 | 379 | |
dabf9ef8 JZ |
380 | #define CONFIG_DOS_PARTITION |
381 | #define CONFIG_SCSI_AHCI | |
382 | ||
383 | #ifdef CONFIG_SCSI_AHCI | |
384 | #define CONFIG_SATA_ULI5288 | |
385 | #define CFG_SCSI_MAX_SCSI_ID 4 | |
386 | #define CFG_SCSI_MAX_LUN 1 | |
387 | #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) | |
388 | #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE | |
389 | #endif | |
390 | ||
0f460a1e JJ |
391 | #define CONFIG_MPC86XX_PCI2 |
392 | ||
debb7354 JL |
393 | #endif /* CONFIG_PCI */ |
394 | ||
debb7354 JL |
395 | #if defined(CONFIG_TSEC_ENET) |
396 | ||
397 | #ifndef CONFIG_NET_MULTI | |
398 | #define CONFIG_NET_MULTI 1 | |
399 | #endif | |
400 | ||
401 | #define CONFIG_MII 1 /* MII PHY management */ | |
402 | ||
255a3577 KP |
403 | #define CONFIG_TSEC1 1 |
404 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
405 | #define CONFIG_TSEC2 1 | |
406 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
407 | #define CONFIG_TSEC3 1 | |
408 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
409 | #define CONFIG_TSEC4 1 | |
410 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
debb7354 | 411 | |
debb7354 JL |
412 | #define TSEC1_PHY_ADDR 0 |
413 | #define TSEC2_PHY_ADDR 1 | |
414 | #define TSEC3_PHY_ADDR 2 | |
415 | #define TSEC4_PHY_ADDR 3 | |
416 | #define TSEC1_PHYIDX 0 | |
417 | #define TSEC2_PHYIDX 0 | |
418 | #define TSEC3_PHYIDX 0 | |
419 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
420 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
421 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
422 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
423 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
debb7354 JL |
424 | |
425 | #define CONFIG_ETHPRIME "eTSEC1" | |
426 | ||
427 | #endif /* CONFIG_TSEC_ENET */ | |
428 | ||
586d1d5a JL |
429 | /* |
430 | * BAT0 2G Cacheable, non-guarded | |
debb7354 JL |
431 | * 0x0000_0000 2G DDR |
432 | */ | |
fecf1c7e JL |
433 | #define CFG_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
434 | #define CFG_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
435 | #define CFG_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) | |
debb7354 JL |
436 | #define CFG_IBAT0U CFG_DBAT0U |
437 | ||
586d1d5a JL |
438 | /* |
439 | * BAT1 1G Cache-inhibited, guarded | |
debb7354 JL |
440 | * 0x8000_0000 512M PCI-Express 1 Memory |
441 | * 0xa000_0000 512M PCI-Express 2 Memory | |
586d1d5a | 442 | * Changed it for operating from 0xd0000000 |
debb7354 | 443 | */ |
63cec581 | 444 | #define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ |
5c9efb36 | 445 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
63cec581 ES |
446 | #define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) |
447 | #define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
debb7354 JL |
448 | #define CFG_IBAT1U CFG_DBAT1U |
449 | ||
586d1d5a JL |
450 | /* |
451 | * BAT2 512M Cache-inhibited, guarded | |
debb7354 JL |
452 | * 0xc000_0000 512M RapidIO Memory |
453 | */ | |
63cec581 | 454 | #define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ |
5c9efb36 | 455 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
63cec581 ES |
456 | #define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) |
457 | #define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
debb7354 JL |
458 | #define CFG_IBAT2U CFG_DBAT2U |
459 | ||
586d1d5a JL |
460 | /* |
461 | * BAT3 4M Cache-inhibited, guarded | |
debb7354 JL |
462 | * 0xf800_0000 4M CCSR |
463 | */ | |
5c9efb36 JL |
464 | #define CFG_DBAT3L ( CFG_CCSRBAR | BATL_PP_RW \ |
465 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
debb7354 JL |
466 | #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
467 | #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
468 | #define CFG_IBAT3U CFG_DBAT3U | |
469 | ||
586d1d5a JL |
470 | /* |
471 | * BAT4 32M Cache-inhibited, guarded | |
debb7354 JL |
472 | * 0xe200_0000 16M PCI-Express 1 I/O |
473 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
586d1d5a | 474 | * Note that this is at 0xe0000000 |
debb7354 | 475 | */ |
63cec581 | 476 | #define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ |
5c9efb36 | 477 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
63cec581 ES |
478 | #define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) |
479 | #define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
debb7354 JL |
480 | #define CFG_IBAT4U CFG_DBAT4U |
481 | ||
586d1d5a JL |
482 | /* |
483 | * BAT5 128K Cacheable, non-guarded | |
debb7354 JL |
484 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) |
485 | */ | |
486 | #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
487 | #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
488 | #define CFG_IBAT5L CFG_DBAT5L | |
489 | #define CFG_IBAT5U CFG_DBAT5U | |
490 | ||
586d1d5a JL |
491 | /* |
492 | * BAT6 32M Cache-inhibited, guarded | |
debb7354 JL |
493 | * 0xfe00_0000 32M FLASH |
494 | */ | |
fa7db9c3 | 495 | #define CFG_DBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ |
5c9efb36 | 496 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
fa7db9c3 JZR |
497 | #define CFG_DBAT6U ((CFG_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) |
498 | #define CFG_IBAT6L ((CFG_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) | |
debb7354 JL |
499 | #define CFG_IBAT6U CFG_DBAT6U |
500 | ||
debb7354 JL |
501 | #define CFG_DBAT7L 0x00000000 |
502 | #define CFG_DBAT7U 0x00000000 | |
503 | #define CFG_IBAT7L 0x00000000 | |
504 | #define CFG_IBAT7U 0x00000000 | |
505 | ||
debb7354 JL |
506 | /* |
507 | * Environment | |
508 | */ | |
5c9efb36 JL |
509 | #ifndef CFG_RAMBOOT |
510 | #define CFG_ENV_IS_IN_FLASH 1 | |
0f460a1e JJ |
511 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) |
512 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ | |
5c9efb36 JL |
513 | #define CFG_ENV_SIZE 0x2000 |
514 | #else | |
5c9efb36 JL |
515 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
516 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
517 | #define CFG_ENV_SIZE 0x2000 | |
518 | #endif | |
debb7354 JL |
519 | |
520 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
521 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
522 | ||
2f9c19e4 | 523 | |
659e2f67 JL |
524 | /* |
525 | * BOOTP options | |
526 | */ | |
527 | #define CONFIG_BOOTP_BOOTFILESIZE | |
528 | #define CONFIG_BOOTP_BOOTPATH | |
529 | #define CONFIG_BOOTP_GATEWAY | |
530 | #define CONFIG_BOOTP_HOSTNAME | |
531 | ||
532 | ||
2f9c19e4 JL |
533 | /* |
534 | * Command line configuration. | |
535 | */ | |
536 | #include <config_cmd_default.h> | |
537 | ||
538 | #define CONFIG_CMD_PING | |
539 | #define CONFIG_CMD_I2C | |
4f93f8b1 | 540 | #define CONFIG_CMD_REGINFO |
2f9c19e4 | 541 | |
debb7354 | 542 | #if defined(CFG_RAMBOOT) |
2f9c19e4 JL |
543 | #undef CONFIG_CMD_ENV |
544 | #endif | |
545 | ||
546 | #if defined(CONFIG_PCI) | |
547 | #define CONFIG_CMD_PCI | |
548 | #define CONFIG_CMD_SCSI | |
549 | #define CONFIG_CMD_EXT2 | |
bbf4796f | 550 | #define CONFIG_CMD_USB |
debb7354 JL |
551 | #endif |
552 | ||
debb7354 JL |
553 | |
554 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
555 | ||
556 | /* | |
557 | * Miscellaneous configurable options | |
558 | */ | |
559 | #define CFG_LONGHELP /* undef to save memory */ | |
6bee764b | 560 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
debb7354 JL |
561 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
562 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
563 | ||
2f9c19e4 | 564 | #if defined(CONFIG_CMD_KGDB) |
debb7354 JL |
565 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
566 | #else | |
567 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
568 | #endif | |
569 | ||
570 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
571 | #define CFG_MAXARGS 16 /* max number of command args */ | |
572 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
573 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
574 | ||
575 | /* | |
576 | * For booting Linux, the board info and command line data | |
577 | * have to be in the first 8 MB of memory, since this is | |
578 | * the maximum mapped by the Linux kernel during initialization. | |
579 | */ | |
580 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
581 | ||
debb7354 JL |
582 | /* |
583 | * Internal Definitions | |
584 | * | |
585 | * Boot Flags | |
586 | */ | |
587 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
588 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
589 | ||
2f9c19e4 JL |
590 | #if defined(CONFIG_CMD_KGDB) |
591 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
592 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
debb7354 JL |
593 | #endif |
594 | ||
debb7354 JL |
595 | /* |
596 | * Environment Configuration | |
597 | */ | |
598 | ||
599 | /* The mac addresses for all ethernet interface */ | |
600 | #if defined(CONFIG_TSEC_ENET) | |
601 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 | |
602 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD | |
603 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
604 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
605 | #endif | |
606 | ||
10327dc5 | 607 | #define CONFIG_HAS_ETH0 1 |
5c9efb36 JL |
608 | #define CONFIG_HAS_ETH1 1 |
609 | #define CONFIG_HAS_ETH2 1 | |
610 | #define CONFIG_HAS_ETH3 1 | |
debb7354 | 611 | |
18b6c8cd | 612 | #define CONFIG_IPADDR 192.168.1.100 |
debb7354 JL |
613 | |
614 | #define CONFIG_HOSTNAME unknown | |
615 | #define CONFIG_ROOTPATH /opt/nfsroot | |
616 | #define CONFIG_BOOTFILE uImage | |
32922cdc | 617 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
debb7354 | 618 | |
5c9efb36 | 619 | #define CONFIG_SERVERIP 192.168.1.1 |
18b6c8cd | 620 | #define CONFIG_GATEWAYIP 192.168.1.1 |
5c9efb36 | 621 | #define CONFIG_NETMASK 255.255.255.0 |
debb7354 | 622 | |
5c9efb36 JL |
623 | /* default location for tftp and bootm */ |
624 | #define CONFIG_LOADADDR 1000000 | |
debb7354 JL |
625 | |
626 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
18b6c8cd | 627 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
debb7354 JL |
628 | |
629 | #define CONFIG_BAUDRATE 115200 | |
630 | ||
631 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
632 | "netdev=eth0\0" \ | |
32922cdc ES |
633 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
634 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
635 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
636 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
637 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
638 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
639 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
debb7354 | 640 | "consoledev=ttyS0\0" \ |
5567806b | 641 | "ramdiskaddr=2000000\0" \ |
debb7354 | 642 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
ea9f7395 JL |
643 | "fdtaddr=c00000\0" \ |
644 | "fdtfile=mpc8641_hpcn.dtb\0" \ | |
debb7354 JL |
645 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ |
646 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
647 | "maxcpus=2" | |
648 | ||
649 | ||
650 | #define CONFIG_NFSBOOTCOMMAND \ | |
651 | "setenv bootargs root=/dev/nfs rw " \ | |
652 | "nfsroot=$serverip:$rootpath " \ | |
653 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
654 | "console=$consoledev,$baudrate $othbootargs;" \ | |
655 | "tftp $loadaddr $bootfile;" \ | |
ea9f7395 JL |
656 | "tftp $fdtaddr $fdtfile;" \ |
657 | "bootm $loadaddr - $fdtaddr" | |
debb7354 JL |
658 | |
659 | #define CONFIG_RAMBOOTCOMMAND \ | |
660 | "setenv bootargs root=/dev/ram rw " \ | |
661 | "console=$consoledev,$baudrate $othbootargs;" \ | |
662 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
663 | "tftp $loadaddr $bootfile;" \ | |
ea9f7395 JL |
664 | "tftp $fdtaddr $fdtfile;" \ |
665 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
debb7354 JL |
666 | |
667 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
668 | ||
669 | #endif /* __CONFIG_H */ |