projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 5c9efb36 | 2 | /* |
| 1b77ca8a | 3 | * Copyright 2006, 2010-2011 Freescale Semiconductor. |
| 5c9efb36 | 4 | * |
| debb7354 | 5 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| debb7354 JL |
6 | */ |
| 7 | ||
| 8 | /* | |
| 5c9efb36 | 9 | * MPC8641HPCN board configuration file |
| debb7354 JL |
10 | * |
| 11 | * Make sure you change the MAC address and other network params first, | |
| 92ac5208 | 12 | * search for CONFIG_SERVERIP, etc. in this file. |
| debb7354 JL |
13 | */ |
| 14 | ||
| 15 | #ifndef __CONFIG_H | |
| 16 | #define __CONFIG_H | |
| 17 | ||
| 18 | /* High Level Configuration Options */ | |
| 53677ef1 | 19 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
| d591a80e | 20 | #define CONFIG_ADDR_MAP 1 /* Use addr map */ |
| debb7354 | 21 | |
| 2ae18241 WD |
22 | /* |
| 23 | * default CCSRBAR is at 0xff700000 | |
| 24 | * assume U-Boot is less than 0.5MB | |
| 25 | */ | |
| 2ae18241 | 26 | |
| debb7354 | 27 | #ifdef RUN_DIAG |
| 6bf98b13 | 28 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
| debb7354 | 29 | #endif |
| 5c9efb36 | 30 | |
| 1266df88 BB |
31 | /* |
| 32 | * virtual address to be used for temporary mappings. There | |
| 33 | * should be 128k free at this VA. | |
| 34 | */ | |
| 35 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
| 36 | ||
| 1b77ca8a KG |
37 | #define CONFIG_SYS_SRIO |
| 38 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
| af5d100e | 39 | |
| b38eaec5 RD |
40 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ |
| 41 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ | |
| 63cec581 | 42 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 8ba93f68 | 43 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 5c9efb36 | 44 | |
| debb7354 | 45 | #define CONFIG_ENV_OVERWRITE |
| debb7354 | 46 | |
| 4bbfd3e2 | 47 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
| d591a80e | 48 | #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ |
| debb7354 | 49 | |
| 53677ef1 | 50 | #define CONFIG_ALTIVEC 1 |
| debb7354 | 51 | |
| 5c9efb36 | 52 | /* |
| debb7354 JL |
53 | * L2CR setup -- make sure this is right for your board! |
| 54 | */ | |
| 6d0f6bcf | 55 | #define CONFIG_SYS_L2 |
| debb7354 JL |
56 | #define L2_INIT 0 |
| 57 | #define L2_ENABLE (L2CR_L2E) | |
| 58 | ||
| 59 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 63cec581 ES |
60 | #ifndef __ASSEMBLY__ |
| 61 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 62 | #endif | |
| 53677ef1 | 63 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
| debb7354 JL |
64 | #endif |
| 65 | ||
| 3111d32c BB |
66 | /* |
| 67 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
| 68 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
| 69 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
| 70 | */ | |
| 71 | #ifdef CONFIG_PHYS_64BIT | |
| 1605cc9e | 72 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f |
| 3111d32c | 73 | #else |
| 1605cc9e | 74 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 |
| 3111d32c BB |
75 | #endif |
| 76 | ||
| debb7354 JL |
77 | /* |
| 78 | * Base addresses -- Note these are effective addresses where the | |
| 79 | * actual resources get mapped (not physical addresses) | |
| 80 | */ | |
| c759a01a | 81 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 6d0f6bcf | 82 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| debb7354 | 83 | |
| 3111d32c BB |
84 | /* Physical addresses */ |
| 85 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 1605cc9e BB |
86 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH |
| 87 | #define CONFIG_SYS_CCSRBAR_PHYS \ | |
| 88 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ | |
| 89 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) | |
| 3111d32c | 90 | |
| 076bff8f YS |
91 | #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ |
| 92 | ||
| debb7354 JL |
93 | /* |
| 94 | * DDR Setup | |
| 95 | */ | |
| 6a8e5692 KG |
96 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 97 | #define CONFIG_DDR_SPD | |
| 98 | ||
| 99 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 100 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 101 | ||
| 6d0f6bcf JCPV |
102 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 103 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 1266df88 | 104 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
| fcb28e76 | 105 | #define CONFIG_VERY_BIG_RAM |
| debb7354 | 106 | |
| 6a8e5692 KG |
107 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
| 108 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 109 | ||
| 110 | /* | |
| 111 | * I2C addresses of SPD EEPROMs | |
| 112 | */ | |
| 113 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
| 114 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
| 115 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
| 116 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
| 117 | ||
| 6a8e5692 KG |
118 | /* |
| 119 | * These are used when DDR doesn't use SPD. | |
| 120 | */ | |
| 6d0f6bcf JCPV |
121 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 122 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
| 123 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
| 124 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 125 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 126 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
| 127 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
| 128 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
| 129 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 130 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
| 131 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 132 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 133 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 134 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
| 135 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
| 136 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
| 6a8e5692 | 137 | |
| ad8f8687 | 138 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf | 139 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 32628c50 | 140 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf JCPV |
141 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 142 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| debb7354 | 143 | |
| c759a01a | 144 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
| 1605cc9e BB |
145 | #define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE |
| 146 | #define CONFIG_SYS_FLASH_BASE_PHYS \ | |
| 147 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ | |
| 148 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| 3111d32c | 149 | |
| b81b773e | 150 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| debb7354 | 151 | |
| 3111d32c BB |
152 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 153 | | 0x00001001) /* port size 16bit */ | |
| 154 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
| debb7354 | 155 | |
| 3111d32c BB |
156 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
| 157 | | 0x00001001) /* port size 16bit */ | |
| 158 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
| debb7354 | 159 | |
| 3111d32c BB |
160 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
| 161 | | 0x00000801) /* port size 8bit */ | |
| 162 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
| debb7354 | 163 | |
| c759a01a BB |
164 | /* |
| 165 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
| 166 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
| 167 | * required for the smallest BAT mapping, so there's a 64k hole. | |
| 168 | */ | |
| 169 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
| 1605cc9e | 170 | #define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE |
| debb7354 | 171 | |
| 7608d75f | 172 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| c759a01a | 173 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
| 1605cc9e BB |
174 | #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) |
| 175 | #define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ | |
| 176 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| c759a01a | 177 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
| 5c9efb36 JL |
178 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 179 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 180 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 181 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 182 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
| 183 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 184 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 185 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 186 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 187 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 9af9c6bd KG |
188 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
| 189 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
| 5c9efb36 JL |
190 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 191 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 192 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 193 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 194 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
| debb7354 | 195 | |
| b5431560 | 196 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
| c759a01a | 197 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
| 3111d32c | 198 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
| b5431560 | 199 | |
| 170deacb | 200 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 6d0f6bcf | 201 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| debb7354 | 202 | |
| 6d0f6bcf JCPV |
203 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 204 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 205 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 14d0a02a | 206 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| bf9a8c34 | 207 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
| debb7354 | 208 | |
| 6d0f6bcf | 209 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| debb7354 | 210 | |
| 6d0f6bcf JCPV |
211 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 212 | #define CONFIG_SYS_RAMBOOT | |
| debb7354 | 213 | #else |
| 6d0f6bcf | 214 | #undef CONFIG_SYS_RAMBOOT |
| debb7354 JL |
215 | #endif |
| 216 | ||
| 6d0f6bcf | 217 | #if defined(CONFIG_SYS_RAMBOOT) |
| fa7db9c3 | 218 | #undef CONFIG_SPD_EEPROM |
| 6d0f6bcf | 219 | #define CONFIG_SYS_SDRAM_SIZE 256 |
| debb7354 JL |
220 | #endif |
| 221 | ||
| 222 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 223 | ||
| 6d0f6bcf JCPV |
224 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 225 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
| 226 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| debb7354 | 227 | #else |
| 6d0f6bcf | 228 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
| debb7354 | 229 | #endif |
| 553f0982 | 230 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
| debb7354 | 231 | |
| 25ddd1fb | 232 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 233 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| debb7354 | 234 | |
| 221fbd22 | 235 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
| 6d0f6bcf | 236 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| debb7354 JL |
237 | |
| 238 | /* Serial Port */ | |
| 6d0f6bcf JCPV |
239 | #define CONFIG_SYS_NS16550_SERIAL |
| 240 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 241 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| debb7354 | 242 | |
| 6d0f6bcf | 243 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| debb7354 JL |
244 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 245 | ||
| 6d0f6bcf JCPV |
246 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 247 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| debb7354 | 248 | |
| 586d1d5a JL |
249 | /* |
| 250 | * I2C | |
| 251 | */ | |
| 00f792e0 HS |
252 | #define CONFIG_SYS_I2C |
| 253 | #define CONFIG_SYS_I2C_FSL | |
| 254 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 255 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 256 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
| 257 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
| debb7354 | 258 | |
| 586d1d5a JL |
259 | /* |
| 260 | * RapidIO MMU | |
| 261 | */ | |
| 1b77ca8a | 262 | #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ |
| 3111d32c | 263 | #ifdef CONFIG_PHYS_64BIT |
| 1605cc9e BB |
264 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 |
| 265 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c | |
| 3111d32c | 266 | #else |
| 1605cc9e BB |
267 | #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE |
| 268 | #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 | |
| 3111d32c | 269 | #endif |
| 1605cc9e BB |
270 | #define CONFIG_SYS_SRIO1_MEM_PHYS \ |
| 271 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ | |
| 272 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) | |
| 1b77ca8a | 273 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ |
| debb7354 JL |
274 | |
| 275 | /* | |
| 276 | * General PCI | |
| 277 | * Addresses are mapped 1-1. | |
| 278 | */ | |
| 49f46f3b | 279 | |
| 64e55d5e | 280 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
| 46f3e385 | 281 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 3111d32c | 282 | #ifdef CONFIG_PHYS_64BIT |
| 46f3e385 | 283 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 1605cc9e BB |
284 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 |
| 285 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c | |
| 3111d32c | 286 | #else |
| 46f3e385 | 287 | #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT |
| 1605cc9e BB |
288 | #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT |
| 289 | #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 | |
| 3111d32c | 290 | #endif |
| 1605cc9e BB |
291 | #define CONFIG_SYS_PCIE1_MEM_PHYS \ |
| 292 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ | |
| 293 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) | |
| 46f3e385 KG |
294 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 295 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 296 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
| 1605cc9e BB |
297 | #define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT |
| 298 | #define CONFIG_SYS_PCIE1_IO_PHYS \ | |
| 299 | PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ | |
| 300 | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| 46f3e385 | 301 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ |
| debb7354 | 302 | |
| 4c78d4a6 BB |
303 | #ifdef CONFIG_PHYS_64BIT |
| 304 | /* | |
| 46f3e385 | 305 | * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. |
| 4c78d4a6 BB |
306 | * This will increase the amount of PCI address space available for |
| 307 | * for mapping RAM. | |
| 308 | */ | |
| 46f3e385 | 309 | #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS |
| 4c78d4a6 | 310 | #else |
| 46f3e385 KG |
311 | #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ |
| 312 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 4c78d4a6 | 313 | #endif |
| 46f3e385 KG |
314 | #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ |
| 315 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 1605cc9e BB |
316 | #define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ |
| 317 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 318 | #define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH | |
| 46f3e385 KG |
319 | #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ |
| 320 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 321 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 322 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 323 | #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ | |
| 324 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 1605cc9e BB |
325 | #define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ |
| 326 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 46f3e385 KG |
327 | #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ |
| 328 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 329 | #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE | |
| debb7354 | 330 | |
| debb7354 JL |
331 | #if defined(CONFIG_PCI) |
| 332 | ||
| 53677ef1 | 333 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 334 | |
| debb7354 JL |
335 | #undef CONFIG_EEPRO100 |
| 336 | #undef CONFIG_TULIP | |
| 337 | ||
| a81d1c0b ZW |
338 | /************************************************************ |
| 339 | * USB support | |
| 340 | ************************************************************/ | |
| 53677ef1 | 341 | #define CONFIG_PCI_OHCI 1 |
| a81d1c0b | 342 | #define CONFIG_USB_OHCI_NEW 1 |
| 6d0f6bcf JCPV |
343 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" |
| 344 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 345 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
| a81d1c0b | 346 | |
| 0f460a1e | 347 | /*PCIE video card used*/ |
| 46f3e385 | 348 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
| 0f460a1e JJ |
349 | |
| 350 | /*PCI video card used*/ | |
| 46f3e385 | 351 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ |
| 0f460a1e JJ |
352 | |
| 353 | /* video */ | |
| 0f460a1e JJ |
354 | |
| 355 | #if defined(CONFIG_VIDEO) | |
| 356 | #define CONFIG_BIOSEMU | |
| 0f460a1e JJ |
357 | #define CONFIG_ATI_RADEON_FB |
| 358 | #define CONFIG_VIDEO_LOGO | |
| 46f3e385 | 359 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT |
| 0f460a1e JJ |
360 | #endif |
| 361 | ||
| debb7354 | 362 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 363 | |
| dabf9ef8 JZ |
364 | #ifdef CONFIG_SCSI_AHCI |
| 365 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
366 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 367 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 368 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| dabf9ef8 JZ |
369 | #endif |
| 370 | ||
| debb7354 JL |
371 | #endif /* CONFIG_PCI */ |
| 372 | ||
| debb7354 | 373 | #if defined(CONFIG_TSEC_ENET) |
| 53677ef1 WD |
374 | #define CONFIG_TSEC1 1 |
| 375 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 376 | #define CONFIG_TSEC2 1 | |
| 377 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 378 | #define CONFIG_TSEC3 1 | |
| 379 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 380 | #define CONFIG_TSEC4 1 | |
| 381 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| debb7354 | 382 | |
| debb7354 JL |
383 | #define TSEC1_PHY_ADDR 0 |
| 384 | #define TSEC2_PHY_ADDR 1 | |
| 385 | #define TSEC3_PHY_ADDR 2 | |
| 386 | #define TSEC4_PHY_ADDR 3 | |
| 387 | #define TSEC1_PHYIDX 0 | |
| 388 | #define TSEC2_PHYIDX 0 | |
| 389 | #define TSEC3_PHYIDX 0 | |
| 390 | #define TSEC4_PHYIDX 0 | |
| 3a79013e AF |
391 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 392 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 393 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 394 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| debb7354 JL |
395 | |
| 396 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 397 | ||
| 398 | #endif /* CONFIG_TSEC_ENET */ | |
| 399 | ||
| 1605cc9e | 400 | #ifdef CONFIG_PHYS_64BIT |
| 3111d32c BB |
401 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) |
| 402 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
| 403 | ||
| 1605cc9e BB |
404 | /* Put physical address into the BAT format */ |
| 405 | #define BAT_PHYS_ADDR(low, high) \ | |
| 406 | (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) | |
| 407 | /* Convert high/low pairs to actual 64-bit value */ | |
| 408 | #define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) | |
| 409 | #else | |
| 410 | /* 32-bit systems just ignore the "high" bits */ | |
| 411 | #define BAT_PHYS_ADDR(low, high) (low) | |
| 412 | #define PAIRED_PHYS_TO_PHYS(low, high) (low) | |
| 413 | #endif | |
| 414 | ||
| 586d1d5a | 415 | /* |
| c759a01a | 416 | * BAT0 DDR |
| debb7354 | 417 | */ |
| 6d0f6bcf | 418 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 9ff32d8c | 419 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| debb7354 | 420 | |
| 586d1d5a | 421 | /* |
| c759a01a | 422 | * BAT1 LBC (PIXIS/CF) |
| af5d100e | 423 | */ |
| 1605cc9e BB |
424 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
| 425 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c BB |
426 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
| 427 | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
428 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
| 429 | | BATU_VS | BATU_VP) | |
| 1605cc9e BB |
430 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ |
| 431 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c | 432 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
| c759a01a | 433 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
| af5d100e BB |
434 | |
| 435 | /* if CONFIG_PCI: | |
| 46f3e385 | 436 | * BAT2 PCIE1 and PCIE1 MEM |
| af5d100e | 437 | * if CONFIG_RIO |
| c759a01a | 438 | * BAT2 Rapidio Memory |
| debb7354 | 439 | */ |
| af5d100e | 440 | #ifdef CONFIG_PCI |
| 842033e6 | 441 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 1605cc9e BB |
442 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
| 443 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
| 3111d32c BB |
444 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 445 | | BATL_GUARDEDSTORAGE) | |
| 46f3e385 | 446 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ |
| af5d100e | 447 | | BATU_VS | BATU_VP) |
| 1605cc9e BB |
448 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ |
| 449 | CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ | |
| 3111d32c | 450 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| af5d100e BB |
451 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| 452 | #else /* CONFIG_RIO */ | |
| 1605cc9e BB |
453 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
| 454 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
| 3111d32c BB |
455 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ |
| 456 | BATL_GUARDEDSTORAGE) | |
| 1b77ca8a | 457 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ |
| 3111d32c | 458 | | BATU_VS | BATU_VP) |
| 1605cc9e BB |
459 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ |
| 460 | CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ | |
| 3111d32c | 461 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 6d0f6bcf | 462 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| af5d100e | 463 | #endif |
| debb7354 | 464 | |
| 586d1d5a | 465 | /* |
| c759a01a | 466 | * BAT3 CCSR Space |
| debb7354 | 467 | */ |
| 1605cc9e BB |
468 | #define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
| 469 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 3111d32c BB |
470 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 471 | | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
472 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
| 473 | | BATU_VP) | |
| 1605cc9e BB |
474 | #define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ |
| 475 | CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 3111d32c | 476 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 6d0f6bcf | 477 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
| debb7354 | 478 | |
| 3111d32c BB |
479 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 480 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 481 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 482 | | BATL_GUARDEDSTORAGE) | |
| 483 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 484 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 485 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 486 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 487 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
| 488 | #endif | |
| 489 | ||
| 586d1d5a | 490 | /* |
| 46f3e385 | 491 | * BAT4 PCIE1_IO and PCIE2_IO |
| debb7354 | 492 | */ |
| 1605cc9e BB |
493 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
| 494 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c BB |
495 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 496 | | BATL_GUARDEDSTORAGE) | |
| 46f3e385 | 497 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ |
| c759a01a | 498 | | BATU_VS | BATU_VP) |
| 1605cc9e BB |
499 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ |
| 500 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c | 501 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 6d0f6bcf | 502 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
| debb7354 | 503 | |
| 586d1d5a | 504 | /* |
| c759a01a | 505 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
| debb7354 | 506 | */ |
| 6d0f6bcf JCPV |
507 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 508 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 509 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
| 510 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
| debb7354 | 511 | |
| 586d1d5a | 512 | /* |
| c759a01a | 513 | * BAT6 FLASH |
| debb7354 | 514 | */ |
| 1605cc9e BB |
515 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
| 516 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c BB |
517 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 518 | | BATL_GUARDEDSTORAGE) | |
| 170deacb BB |
519 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
| 520 | | BATU_VP) | |
| 1605cc9e BB |
521 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ |
| 522 | CONFIG_SYS_PHYS_ADDR_HIGH) \ | |
| 3111d32c | 523 | | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 6d0f6bcf | 524 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
| debb7354 | 525 | |
| bf9a8c34 BB |
526 | /* Map the last 1M of flash where we're running from reset */ |
| 527 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 528 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 14d0a02a | 529 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
| bf9a8c34 BB |
530 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 531 | | BATL_MEMCOHERENCE) | |
| 532 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
| 533 | ||
| c759a01a BB |
534 | /* |
| 535 | * BAT7 FREE - used later for tmp mappings | |
| 536 | */ | |
| 6d0f6bcf JCPV |
537 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 538 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
| 539 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
| 540 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
| debb7354 | 541 | |
| debb7354 JL |
542 | /* |
| 543 | * Environment | |
| 544 | */ | |
| debb7354 JL |
545 | |
| 546 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 547 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| debb7354 | 548 | |
| 659e2f67 JL |
549 | /* |
| 550 | * BOOTP options | |
| 551 | */ | |
| 552 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 659e2f67 | 553 | |
| debb7354 JL |
554 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 555 | ||
| 556 | /* | |
| 557 | * Miscellaneous configurable options | |
| 558 | */ | |
| 6d0f6bcf | 559 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| debb7354 | 560 | |
| debb7354 JL |
561 | /* |
| 562 | * For booting Linux, the board info and command line data | |
| 563 | * have to be in the first 8 MB of memory, since this is | |
| 564 | * the maximum mapped by the Linux kernel during initialization. | |
| 565 | */ | |
| e1efe43c SW |
566 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
| 567 | #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ | |
| debb7354 | 568 | |
| 2f9c19e4 JL |
569 | #if defined(CONFIG_CMD_KGDB) |
| 570 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| debb7354 JL |
571 | #endif |
| 572 | ||
| debb7354 JL |
573 | /* |
| 574 | * Environment Configuration | |
| 575 | */ | |
| 576 | ||
| 10327dc5 | 577 | #define CONFIG_HAS_ETH0 1 |
| 5c9efb36 JL |
578 | #define CONFIG_HAS_ETH1 1 |
| 579 | #define CONFIG_HAS_ETH2 1 | |
| 580 | #define CONFIG_HAS_ETH3 1 | |
| debb7354 | 581 | |
| 18b6c8cd | 582 | #define CONFIG_IPADDR 192.168.1.100 |
| debb7354 | 583 | |
| 5bc0543d | 584 | #define CONFIG_HOSTNAME "unknown" |
| 8b3637c6 | 585 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| b3f44c21 | 586 | #define CONFIG_BOOTFILE "uImage" |
| 32922cdc | 587 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| debb7354 | 588 | |
| 5c9efb36 | 589 | #define CONFIG_SERVERIP 192.168.1.1 |
| 18b6c8cd | 590 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 5c9efb36 | 591 | #define CONFIG_NETMASK 255.255.255.0 |
| debb7354 | 592 | |
| 5c9efb36 | 593 | /* default location for tftp and bootm */ |
| e1efe43c | 594 | #define CONFIG_LOADADDR 0x10000000 |
| debb7354 | 595 | |
| 53677ef1 WD |
596 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 597 | "netdev=eth0\0" \ | |
| 5368c55d | 598 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
| 53677ef1 | 599 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 5368c55d MV |
600 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
| 601 | " +$filesize; " \ | |
| 602 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 603 | " +$filesize; " \ | |
| 604 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 605 | " $filesize; " \ | |
| 606 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 607 | " +$filesize; " \ | |
| 608 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
| 609 | " $filesize\0" \ | |
| 53677ef1 | 610 | "consoledev=ttyS0\0" \ |
| e1efe43c | 611 | "ramdiskaddr=0x18000000\0" \ |
| 53677ef1 | 612 | "ramdiskfile=your.ramdisk.u-boot\0" \ |
| e1efe43c | 613 | "fdtaddr=0x17c00000\0" \ |
| 53677ef1 | 614 | "fdtfile=mpc8641_hpcn.dtb\0" \ |
| 3111d32c BB |
615 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
| 616 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
| 53677ef1 WD |
617 | "maxcpus=2" |
| 618 | ||
| 53677ef1 WD |
619 | #define CONFIG_NFSBOOTCOMMAND \ |
| 620 | "setenv bootargs root=/dev/nfs rw " \ | |
| 621 | "nfsroot=$serverip:$rootpath " \ | |
| 622 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 623 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 624 | "tftp $loadaddr $bootfile;" \ | |
| 625 | "tftp $fdtaddr $fdtfile;" \ | |
| 626 | "bootm $loadaddr - $fdtaddr" | |
| 627 | ||
| 628 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 629 | "setenv bootargs root=/dev/ram rw " \ | |
| 630 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 631 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 632 | "tftp $loadaddr $bootfile;" \ | |
| 633 | "tftp $fdtaddr $fdtfile;" \ | |
| 634 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| debb7354 JL |
635 | |
| 636 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 637 | ||
| 638 | #endif /* __CONFIG_H */ |