projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| debb7354 JL |
1 | /* |
| 2 | * Copyright 2004 Freescale Semiconductor. | |
| 3 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * mpc8641hpc3 board configuration file | |
| 26 | * | |
| 27 | * | |
| 28 | * Make sure you change the MAC address and other network params first, | |
| 29 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
| 30 | */ | |
| 31 | ||
| 32 | #ifndef __CONFIG_H | |
| 33 | #define __CONFIG_H | |
| 34 | ||
| 35 | /* High Level Configuration Options */ | |
| 36 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
| 37 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
| 38 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
| 39 | #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ | |
| 40 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ | |
| 41 | #undef DEBUG | |
| 42 | ||
| 43 | //#define RUN_DIAG 1 | |
| 44 | #ifdef RUN_DIAG | |
| 45 | #define CFG_DIAG_ADDR 0xff800000 | |
| 46 | #endif | |
| 47 | #define CFG_RESET_ADDRESS 0xfff00100 | |
| 48 | ||
| 49 | //#define CONFIG_PCI | |
| 50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 51 | #define CONFIG_ENV_OVERWRITE | |
| 52 | /*#define CONFIG_DDR_ECC */ /* only for ECC DDR module */ | |
| 53 | /*#define CONFIG_DDR_DLL */ /* possible DLL fix needed */ | |
| 54 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
| 55 | ||
| 56 | ||
| 57 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
| 58 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 59 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 60 | ||
| 61 | ||
| 62 | #define CONFIG_ALTIVEC 1 | |
| 63 | /*----------------------------------------------------------------------- | |
| 64 | * L2CR setup -- make sure this is right for your board! | |
| 65 | */ | |
| 66 | ||
| 67 | #define CFG_L2 | |
| 68 | #define L2_INIT 0 | |
| 69 | #define L2_ENABLE (L2CR_L2E) | |
| 70 | ||
| 71 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 72 | //#define CONFIG_SYS_CLK_FREQ 33000000 | |
| 73 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
| 74 | #endif | |
| 75 | ||
| 76 | /* | |
| 77 | * These can be toggled for performance analysis, otherwise use default. | |
| 78 | */ | |
| 79 | /* JB - XXX - Are these available on 86xx? */ | |
| 80 | #define CONFIG_BTB /* toggle branch predition */ | |
| 81 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
| 82 | ||
| 83 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 84 | ||
| 85 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
| 86 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
| 87 | #define CFG_MEMTEST_END 0x00400000 | |
| 88 | ||
| 89 | ||
| 90 | /* | |
| 91 | * Base addresses -- Note these are effective addresses where the | |
| 92 | * actual resources get mapped (not physical addresses) | |
| 93 | */ | |
| 94 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 95 | #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ | |
| 96 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
| 97 | ||
| 98 | ||
| 99 | /* | |
| 100 | * DDR Setup | |
| 101 | */ | |
| 102 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
| 103 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
| 104 | ||
| 105 | #define MPC86xx_DDR_SDRAM_CLK_CNTL | |
| 106 | ||
| 107 | #if defined(CONFIG_SPD_EEPROM) | |
| 108 | /* | |
| 109 | * Determine DDR configuration from I2C interface. | |
| 110 | */ | |
| 111 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
| 112 | ||
| 113 | #else | |
| 114 | /* | |
| 115 | * Manually set up DDR parameters | |
| 116 | */ | |
| 117 | ||
| 118 | /* DDR I */ | |
| 119 | #if 1 | |
| 120 | #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ | |
| 121 | ||
| 122 | #define CFG_DDR_CS0_BNDS 0x0000000F | |
| 123 | #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
| 124 | #define CFG_DDR_EXT_REFRESH 0x00000000 | |
| 125 | #define CFG_DDR_TIMING_0 0x00260802 | |
| 126 | #define CFG_DDR_TIMING_1 0x39357322 | |
| 127 | #define CFG_DDR_TIMING_2 0x14904cc8 | |
| 128 | #define CFG_DDR_MODE_1 0x00480432 | |
| 129 | #define CFG_DDR_MODE_2 0x00000000 | |
| 130 | #define CFG_DDR_INTERVAL 0x06090100 | |
| 131 | #define CFG_DDR_DATA_INIT 0xdeadbeef | |
| 132 | #define CFG_DDR_CLK_CTRL 0x03800000 | |
| 133 | #define CFG_DDR_OCD_CTRL 0x00000000 | |
| 134 | #define CFG_DDR_OCD_STATUS 0x00000000 | |
| 135 | #define CFG_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
| 136 | #define CFG_DDR_CONTROL2 0x04400000 | |
| 137 | ||
| 138 | //Not used in fixed_sdram function | |
| 139 | ||
| 140 | #define CFG_DDR_MODE 0x00000022 | |
| 141 | #define CFG_DDR_CS1_BNDS 0x00000000 | |
| 142 | #define CFG_DDR_CS2_BNDS 0x00000FFF //Not done | |
| 143 | #define CFG_DDR_CS3_BNDS 0x00000FFF //Not done | |
| 144 | #define CFG_DDR_CS4_BNDS 0x00000FFF //Not done | |
| 145 | #define CFG_DDR_CS5_BNDS 0x00000FFF //Not done | |
| 146 | ||
| 147 | ||
| 148 | ||
| 149 | #endif | |
| 150 | #endif | |
| 151 | ||
| 152 | ||
| 153 | /* | |
| 154 | * SDRAM on the Local Bus | |
| 155 | */ | |
| 156 | //#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
| 157 | //#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
| 158 | ||
| 159 | /* In MPC8641HPCN, we allocate 16MB flash spaces at fe000000 and ff000000 | |
| 160 | * We only have an 8MB flash. In effect, the addresses from fe000000 to fe7fffff | |
| 161 | * map to fe800000 to ffffffff, and ff000000 to ff7fffff map to ffffffff. | |
| 162 | * However, when u-boot comes up, the flash_init needs hard start addresses | |
| 163 | * to build its info table. For user convenience, we have the flash addresses | |
| 164 | * as fe800000 and ff800000. That way, when we do flash operations, u-boot | |
| 165 | * knows where the flash is and the user can download u-boot code from promjet to | |
| 166 | * fef00000 <- more intuitive than fe700000. Note that, on switching the boot | |
| 167 | * location, fef00000 becomes fff00000. | |
| 168 | */ | |
| 169 | #define CFG_FLASH_BASE 0xfe800000 /* start of FLASH 32M */ | |
| 170 | #define CFG_FLASH_BASE2 0xff800000 | |
| 171 | ||
| 172 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} | |
| 173 | ||
| 174 | ||
| 175 | /*Sri: This looks like a good place to init all the Local Bus chip selects*/ | |
| 176 | ||
| 177 | #define CFG_BR0_PRELIM 0xff001001 /* port size 16bit */ | |
| 178 | #define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Boot Flash area*/ | |
| 179 | ||
| 180 | #define CFG_BR1_PRELIM 0xfe001001 /* port size 16bit */ | |
| 181 | #define CFG_OR1_PRELIM 0xff006ff7 /* 16MB Alternate Boot Flash area*/ | |
| 182 | ||
| 183 | #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ | |
| 184 | #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
| 185 | ||
| 186 | #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ | |
| 187 | #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
| 188 | ||
| 189 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers*/ | |
| 190 | #define PIXIS_ID 0x0 /* MPC8641HPCN Board ID at offset 0*/ | |
| 191 | #define PIXIS_VER 0x1 /* MPC8641HPCN board version version at offset 1*/ | |
| 192 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2*/ | |
| 193 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register*/ | |
| 194 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
| 195 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 196 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 197 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 198 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 199 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 200 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
| 201 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 202 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 203 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 204 | ||
| 205 | ||
| 206 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 207 | //#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ | |
| 208 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ | |
| 209 | ||
| 210 | #undef CFG_FLASH_CHECKSUM | |
| 211 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 212 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 213 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 214 | ||
| 215 | /*#define CFG_HPCN_FLASH_CFI_DRIVER */ | |
| 216 | #define CFG_FLASH_CFI | |
| 217 | #define CFG_FLASH_EMPTY_INFO | |
| 218 | ||
| 219 | ||
| 220 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 221 | #define CFG_RAMBOOT | |
| 222 | #else | |
| 223 | #undef CFG_RAMBOOT | |
| 224 | #endif | |
| 225 | ||
| 226 | #if !defined(CFG_RAMBOOT) | |
| 227 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
| 228 | #endif | |
| 229 | ||
| 230 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 231 | ||
| 232 | #define CONFIG_L1_INIT_RAM | |
| 233 | #undef CFG_INIT_RAM_LOCK | |
| 234 | #ifndef CFG_INIT_RAM_LOCK | |
| 235 | #define CFG_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| 236 | #else | |
| 237 | #define CFG_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ | |
| 238 | #endif | |
| 239 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
| 240 | ||
| 241 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 242 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 243 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 244 | ||
| 245 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 246 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 247 | ||
| 248 | /* Serial Port */ | |
| 249 | #define CONFIG_CONS_INDEX 1 | |
| 250 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 251 | #define CFG_NS16550 | |
| 252 | #define CFG_NS16550_SERIAL | |
| 253 | #define CFG_NS16550_REG_SIZE 1 | |
| 254 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 255 | ||
| 256 | #define CFG_BAUDRATE_TABLE \ | |
| 257 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 258 | ||
| 259 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
| 260 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
| 261 | ||
| 262 | /* Use the HUSH parser */ | |
| 263 | #define CFG_HUSH_PARSER | |
| 264 | #ifdef CFG_HUSH_PARSER | |
| 265 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 266 | #endif | |
| 267 | ||
| 268 | /* pass open firmware flat tree */ | |
| 269 | #define CONFIG_OF_FLAT_TREE 1 | |
| 270 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 271 | ||
| 272 | /* maximum size of the flat tree (8K) */ | |
| 273 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
| 274 | ||
| 275 | #define OF_CPU "PowerPC,8641@0" | |
| 276 | #define OF_SOC "soc8641@f8000000" | |
| 277 | #define OF_TBCLK (bd->bi_busfreq / 8) | |
| 278 | #define OF_STDOUT_PATH "/soc8641@f8000000/serial@4500" | |
| 279 | ||
| 280 | #define CFG_64BIT_VSPRINTF 1 | |
| 281 | #define CFG_64BIT_STRTOUL 1 | |
| 282 | ||
| 283 | /* I2C */ | |
| 284 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 285 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 286 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 287 | #define CFG_I2C_SLAVE 0x7F | |
| 288 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 289 | ||
| 290 | /* RapidIO MMU */ | |
| 291 | #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ | |
| 292 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
| 293 | #define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ | |
| 294 | ||
| 295 | /* | |
| 296 | * General PCI | |
| 297 | * Addresses are mapped 1-1. | |
| 298 | */ | |
| 299 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
| 300 | //#define CFG_PCI1_MEM_BASE 0xd0000000 | |
| 301 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
| 302 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
| 303 | #define CFG_PCI1_IO_BASE 0xe2000000 | |
| 304 | //#define CFG_PCI1_IO_BASE 0xe0000000 | |
| 305 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE | |
| 306 | //#define CFG_PCI1_IO_BUS 0x00000000 | |
| 307 | #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
| 308 | ||
| 309 | /* For RTL8139 */ | |
| 310 | #define _IO_BASE 0x00000000 | |
| 311 | ||
| 312 | #define CFG_PCI2_MEM_BASE 0xa0000000 | |
| 313 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
| 314 | #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 315 | #define CFG_PCI2_IO_BASE 0xe3000000 | |
| 316 | #define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE | |
| 317 | #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ | |
| 318 | ||
| 319 | // #define CFG_PCI1_MEM_BASE 0x80000000 | |
| 320 | // #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
| 321 | // #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
| 322 | // #define CFG_PCI1_IO_BASE 0xe2000000 | |
| 323 | // #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE | |
| 324 | // #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ | |
| 325 | ||
| 326 | ||
| 327 | ||
| 328 | #if defined(CONFIG_PCI) | |
| 329 | ||
| 330 | ||
| 331 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 332 | ||
| 333 | //#define CFG_SCSI_SCAN_BUS_REVERSE | |
| 334 | ||
| 335 | ||
| 336 | #define CONFIG_NET_MULTI | |
| 337 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 338 | ||
| 339 | #define CONFIG_RTL8139 | |
| 340 | ||
| 341 | ||
| 342 | #undef CONFIG_EEPRO100 | |
| 343 | #undef CONFIG_TULIP | |
| 344 | ||
| 345 | #if !defined(CONFIG_PCI_PNP) | |
| 346 | #define PCI_ENET0_IOADDR 0xe0000000 | |
| 347 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
| 348 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
| 349 | #endif | |
| 350 | ||
| 351 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 352 | //#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
| 353 | ||
| 354 | #endif /* CONFIG_PCI */ | |
| 355 | ||
| 356 | ||
| 357 | #if defined(CONFIG_TSEC_ENET) | |
| 358 | ||
| 359 | #ifndef CONFIG_NET_MULTI | |
| 360 | #define CONFIG_NET_MULTI 1 | |
| 361 | #endif | |
| 362 | ||
| 363 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 364 | ||
| 365 | #define CONFIG_MPC86XX_TSEC1 1 | |
| 366 | #define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" | |
| 367 | #define CONFIG_MPC86XX_TSEC2 1 | |
| 368 | #define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" | |
| 369 | #define CONFIG_MPC86XX_TSEC3 1 | |
| 370 | #define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" | |
| 371 | #define CONFIG_MPC86XX_TSEC4 1 | |
| 372 | #define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" | |
| 373 | ||
| 374 | ||
| 375 | #define TSEC1_PHY_ADDR 0 | |
| 376 | #define TSEC2_PHY_ADDR 1 | |
| 377 | #define TSEC3_PHY_ADDR 2 | |
| 378 | #define TSEC4_PHY_ADDR 3 | |
| 379 | #define TSEC1_PHYIDX 0 | |
| 380 | #define TSEC2_PHYIDX 0 | |
| 381 | #define TSEC3_PHYIDX 0 | |
| 382 | #define TSEC4_PHYIDX 0 | |
| 383 | ||
| 384 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 385 | ||
| 386 | #endif /* CONFIG_TSEC_ENET */ | |
| 387 | ||
| 388 | ||
| 389 | /* BAT0 2G Cacheable, non-guarded | |
| 390 | * 0x0000_0000 2G DDR | |
| 391 | */ | |
| 392 | //#define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 393 | #define CFG_DBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE | BATL_MEMCOHERENCE) | |
| 394 | #define CFG_DBAT0U (0x0 | BATU_BL_512M | BATU_VS | BATU_VP) | |
| 395 | //#define CFG_IBAT0L CFG_DBAT0L | |
| 396 | //#define CFG_IBAT0L (0x0 | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 397 | #define CFG_IBAT0L (0x0| BATL_PP_RW | BATL_CACHEINHIBIT | BATL_MEMCOHERENCE) | |
| 398 | #define CFG_IBAT0U CFG_DBAT0U | |
| 399 | ||
| 400 | /* BAT1 1G Cache-inhibited, guarded | |
| 401 | * 0x8000_0000 512M PCI-Express 1 Memory | |
| 402 | * 0xa000_0000 512M PCI-Express 2 Memory | |
| 403 | ** SS - Changed it for operating from 0xd0000000 | |
| 404 | */ | |
| 405 | #define CFG_DBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 406 | #define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 407 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 408 | #define CFG_IBAT1U CFG_DBAT1U | |
| 409 | ||
| 410 | /* BAT2 512M Cache-inhibited, guarded | |
| 411 | * 0xc000_0000 512M RapidIO Memory | |
| 412 | */ | |
| 413 | #define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 414 | #define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) | |
| 415 | #define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 416 | #define CFG_IBAT2U CFG_DBAT2U | |
| 417 | ||
| 418 | /* BAT3 4M Cache-inhibited, guarded | |
| 419 | * 0xf800_0000 4M CCSR | |
| 420 | */ | |
| 421 | #define CFG_DBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 422 | #define CFG_DBAT3U (CFG_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) | |
| 423 | #define CFG_IBAT3L (CFG_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 424 | #define CFG_IBAT3U CFG_DBAT3U | |
| 425 | ||
| 426 | /* BAT4 32M Cache-inhibited, guarded | |
| 427 | * 0xe200_0000 16M PCI-Express 1 I/O | |
| 428 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
| 429 | ** SS - Note that this is at 0xe0000000 | |
| 430 | */ | |
| 431 | #define CFG_DBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 432 | #define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 433 | #define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 434 | #define CFG_IBAT4U CFG_DBAT4U | |
| 435 | ||
| 436 | /* BAT5 128K Cacheable, non-guarded | |
| 437 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
| 438 | */ | |
| 439 | #define CFG_DBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 440 | #define CFG_DBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 441 | #define CFG_IBAT5L CFG_DBAT5L | |
| 442 | #define CFG_IBAT5U CFG_DBAT5U | |
| 443 | ||
| 444 | /* BAT6 32M Cache-inhibited, guarded | |
| 445 | * 0xfe00_0000 32M FLASH | |
| 446 | */ | |
| 447 | #define CFG_DBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 448 | #define CFG_DBAT6U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 449 | #define CFG_IBAT6L (CFG_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 450 | #define CFG_IBAT6U CFG_DBAT6U | |
| 451 | ||
| 452 | ||
| 453 | #define CFG_DBAT7L 0x00000000 | |
| 454 | #define CFG_DBAT7U 0x00000000 | |
| 455 | #define CFG_IBAT7L 0x00000000 | |
| 456 | #define CFG_IBAT7U 0x00000000 | |
| 457 | ||
| 458 | ||
| 459 | ||
| 460 | ||
| 461 | /* | |
| 462 | * Environment | |
| 463 | */ | |
| 464 | #ifndef CFG_RAMBOOT | |
| 465 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 466 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
| 467 | #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ | |
| 468 | #define CFG_ENV_SIZE 0x2000 | |
| 469 | #else | |
| 470 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
| 471 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 472 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
| 473 | #define CFG_ENV_SIZE 0x2000 | |
| 474 | #endif | |
| 475 | ||
| 476 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 477 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 478 | ||
| 479 | #if defined(CFG_RAMBOOT) | |
| 480 | #if defined(CONFIG_PCI) | |
| 481 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | |
| 482 | | CFG_CMD_PING \ | |
| 483 | | CFG_CMD_PCI \ | |
| 484 | | CFG_CMD_I2C) \ | |
| 485 | & \ | |
| 486 | ~(CFG_CMD_ENV \ | |
| 487 | | CFG_CMD_IMLS \ | |
| 488 | | CFG_CMD_FLASH \ | |
| 489 | | CFG_CMD_LOADS)) | |
| 490 | #else | |
| 491 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | |
| 492 | | CFG_CMD_PING \ | |
| 493 | | CFG_CMD_I2C) \ | |
| 494 | & \ | |
| 495 | ~(CFG_CMD_ENV \ | |
| 496 | | CFG_CMD_IMLS \ | |
| 497 | | CFG_CMD_FLASH \ | |
| 498 | | CFG_CMD_LOADS)) | |
| 499 | #endif | |
| 500 | #else | |
| 501 | #if defined(CONFIG_PCI) | |
| 502 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
| 503 | | CFG_CMD_PCI \ | |
| 504 | | CFG_CMD_PING \ | |
| 505 | | CFG_CMD_I2C) | |
| 506 | #else | |
| 507 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
| 508 | | CFG_CMD_PING \ | |
| 509 | | CFG_CMD_I2C) | |
| 510 | #endif | |
| 511 | #endif | |
| 512 | ||
| 513 | #include <cmd_confdefs.h> | |
| 514 | ||
| 515 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 516 | ||
| 517 | /* | |
| 518 | * Miscellaneous configurable options | |
| 519 | */ | |
| 520 | #define CFG_LONGHELP /* undef to save memory */ | |
| 521 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
| 522 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 523 | ||
| 524 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 525 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 526 | #else | |
| 527 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 528 | #endif | |
| 529 | ||
| 530 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 531 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 532 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 533 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 534 | ||
| 535 | /* | |
| 536 | * For booting Linux, the board info and command line data | |
| 537 | * have to be in the first 8 MB of memory, since this is | |
| 538 | * the maximum mapped by the Linux kernel during initialization. | |
| 539 | */ | |
| 540 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
| 541 | ||
| 542 | /* Cache Configuration */ | |
| 543 | #define CFG_DCACHE_SIZE 32768 | |
| 544 | #define CFG_CACHELINE_SIZE 32 | |
| 545 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 546 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ | |
| 547 | #endif | |
| 548 | ||
| 549 | /* | |
| 550 | * Internal Definitions | |
| 551 | * | |
| 552 | * Boot Flags | |
| 553 | */ | |
| 554 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 555 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 556 | ||
| 557 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
| 558 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 559 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 560 | #endif | |
| 561 | ||
| 562 | ||
| 563 | /* | |
| 564 | * Environment Configuration | |
| 565 | */ | |
| 566 | ||
| 567 | /* The mac addresses for all ethernet interface */ | |
| 568 | #if defined(CONFIG_TSEC_ENET) | |
| 569 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 | |
| 570 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD | |
| 571 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
| 572 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
| 573 | #endif | |
| 574 | ||
| 575 | #define CONFIG_HAS_ETH1 1 | |
| 576 | #define CONFIG_HAS_ETH2 1 | |
| 577 | #define CONFIG_HAS_ETH3 1 | |
| 578 | ||
| 579 | #define CONFIG_IPADDR 10.82.193.138 | |
| 580 | ||
| 581 | #define CONFIG_HOSTNAME unknown | |
| 582 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 583 | #define CONFIG_BOOTFILE uImage | |
| 584 | ||
| 585 | #define CONFIG_SERVERIP 10.82.193.104 | |
| 586 | #define CONFIG_GATEWAYIP 10.82.193.254 | |
| 587 | #define CONFIG_NETMASK 255.255.252.0 | |
| 588 | ||
| 589 | #define CONFIG_LOADADDR 1000000 /* default location for tftp and bootm */ | |
| 590 | ||
| 591 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 592 | //#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 593 | #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" | |
| 594 | ||
| 595 | #define CONFIG_BAUDRATE 115200 | |
| 596 | ||
| 597 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 598 | "netdev=eth0\0" \ | |
| 599 | "consoledev=ttyS0\0" \ | |
| 600 | "ramdiskaddr=400000\0" \ | |
| 601 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
| 602 | "pex0=echo ---------------------------; echo --------- PCI EXPRESS -----\0" \ | |
| 603 | "pexstat=mw f8008000 84000004; echo -expect:- 16000000; md f8008004 1\0" \ | |
| 604 | "pex1=pci write 1.0.0 4 146; pci write 1.0.0 10 80000000\0" \ | |
| 605 | "pexd=echo -expect:- xxx01002 00100146; pci display 1.0.0 0 2\0" \ | |
| 606 | "pex=run pexstat; run pex1; run pexd\0" \ | |
| 607 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ | |
| 608 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
| 609 | "maxcpus=2" | |
| 610 | ||
| 611 | ||
| 612 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 613 | "setenv bootargs root=/dev/nfs rw " \ | |
| 614 | "nfsroot=$serverip:$rootpath " \ | |
| 615 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 616 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 617 | "tftp $loadaddr $bootfile;" \ | |
| 618 | "bootm $loadaddr" | |
| 619 | ||
| 620 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 621 | "setenv bootargs root=/dev/ram rw " \ | |
| 622 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 623 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 624 | "tftp $loadaddr $bootfile;" \ | |
| 625 | "bootm $loadaddr $ramdiskaddr" | |
| 626 | ||
| 627 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 628 | ||
| 629 | #endif /* __CONFIG_H */ |