[thirdparty/u-boot.git] / include / configs / MVBC_P.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2008
 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <version.h>

#define CONFIG_MPC5xxx	1
#define CONFIG_MPC5200 	1

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFF800000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000

#define CONFIG_MISC_INIT_R	1

#define CONFIG_SYS_CACHELINE_SIZE	32
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5
#endif

#define CONFIG_PSC_CONSOLE	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}

#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#undef	CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1
#define CONFIG_HIGH_BATS	1

#define MV_CI			mvBlueCOUGAR-P
#define MV_VCI			mvBlueCOUGAR-P
#define MV_FPGA_DATA		0xff860000
#define MV_FPGA_SIZE		0
#define MV_KERNEL_ADDR		0xffd00000
#define MV_INITRD_ADDR		0xff900000
#define MV_INITRD_LENGTH	0x00400000
#define MV_SCRATCH_ADDR		0x00000000
#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
#define MV_SCRIPT_ADDR		0xff840000
#define MV_SCRIPT_ADDR2		0xff850000
#define MV_DTB_ADDR		0xfffc0000

#define CONFIG_SHOW_BOOT_PROGRESS 1

#define MV_KERNEL_ADDR_RAM	0x00100000
#define MV_DTB_ADDR_RAM		0x00600000
#define MV_INITRD_ADDR_RAM	0x01000000

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define MV_DTB_NAME		mvbc-p.dtb
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * Supported commands
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C

#undef CONFIG_WATCHDOG

#define CONFIG_BOOTP_VENDOREX
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME

/*
 * Autoboot
 */
#define CONFIG_BOOTDELAY		2
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR 	"s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY		1000

#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; \
					then source ${script_addr};	\
					else source ${script_addr2};	\
				fi;"

#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
#define CONFIG_ENV_OVERWRITE

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"console_nr=0\0"					\
	"console=yes\0"						\
	"stdin=serial\0"					\
	"stdout=serial\0"					\
	"stderr=serial\0"					\
	"fpga=0\0"						\
	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
	"mv_version=" U_BOOT_VERSION "\0"			\
	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
	"netretry=no\0"						\
	"use_static_ipaddr=no\0"				\
	"static_ipaddr=192.168.90.10\0"				\
	"static_netmask=255.255.255.0\0"			\
	"static_gateway=0.0.0.0\0"				\
	"initrd_name=uInitrd.mvbc-p-rfs\0"			\
	"zcip=no\0"						\
	"netboot=yes\0"						\
	"mvtest=Ff\0"						\
	"tried_bootfromflash=no\0"				\
	"tried_bootfromnet=no\0"				\
	"use_dhcp=yes\0"					\
	"gev_start=yes\0"					\
	"mvbcdma_debug=0\0"					\
	"mvbcia_debug=0\0"					\
	"propdev_debug=0\0"					\
	"gevss_debug=0\0"					\
	"watchdog=1\0"						\
	"sensor_cnt=1\0"					\
	""

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2

/*
 * Flash configuration
 */
#undef 	CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_SYS_LOWBOOT
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FLASH_SIZE		0x00800000

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH
#undef	CONFIG_SYS_FLASH_PROTECTION

#define CONFIG_ENV_ADDR		0xFFFE0000
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_MODULE	1
#define CONFIG_SYS_I2C_SPEED	86000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/*
 * Ethernet configuration
 */
#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_E1000
#define CONFIG_E1000_FALLBACK_MAC	{ 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
#undef CONFIG_MPC5xxx_FEC
#undef CONFIG_PHY_ADDR
#define CONFIG_NETDEV		eth0

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#undef 	CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"=> "
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE		1024
#else
#define CONFIG_SYS_CBSIZE		256
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x00800000
#define CONFIG_SYS_MEMTEST_END		0x02f00000

#define CONFIG_SYS_HZ			1000

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		0x02000000
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 	0x00200000

/*
 * Various low-level settings
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x20000004

#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x000000f0
#define CONFIG_SYS_CS_DEADCYCLE	0x33333303

#define CONFIG_SYS_RESET_ADDRESS	0x00000100

#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA	1
#define CONFIG_FPGA_CYCLON2	1
#define CONFIG_FPGA_COUNT	1

#endif
Commit	Line	Data
5e0de0e2 AS	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
5e0de0e2 AS	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	#include <version.h>
	15
	16	#define CONFIG_MPC5xxx 1
	17	#define CONFIG_MPC5200 1
	18
2ae18241 WD	19	#ifndef CONFIG_SYS_TEXT_BASE
	20	#define CONFIG_SYS_TEXT_BASE 0xFF800000
	21	#endif
	22
6d0f6bcf	23	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
5e0de0e2	24
5e0de0e2 AS	25	#define CONFIG_MISC_INIT_R 1
5e0de0e2 AS	26
6d0f6bcf	27	#define CONFIG_SYS_CACHELINE_SIZE 32
17e900b8	28	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	29	#define CONFIG_SYS_CACHELINE_SHIFT 5
5e0de0e2 AS	30	#endif
	31
	32	#define CONFIG_PSC_CONSOLE 1
	33	#define CONFIG_BAUDRATE 115200
6d0f6bcf	34	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
5e0de0e2 AS	35
	36	#define CONFIG_PCI 1
	37	#define CONFIG_PCI_PNP 1
	38	#undef CONFIG_PCI_SCAN_SHOW
	39	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
	40
	41	#define CONFIG_PCI_MEM_BUS 0x40000000
	42	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	43	#define CONFIG_PCI_MEM_SIZE 0x10000000
	44
	45	#define CONFIG_PCI_IO_BUS 0x50000000
	46	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	47	#define CONFIG_PCI_IO_SIZE 0x01000000
	48
6d0f6bcf	49	#define CONFIG_SYS_XLB_PIPELINING 1
5e0de0e2 AS	50	#define CONFIG_HIGH_BATS 1
	51
	52	#define MV_CI mvBlueCOUGAR-P
	53	#define MV_VCI mvBlueCOUGAR-P
	54	#define MV_FPGA_DATA 0xff860000
28887d83	55	#define MV_FPGA_SIZE 0
e3b39f84	56	#define MV_KERNEL_ADDR 0xffd00000
5e0de0e2	57	#define MV_INITRD_ADDR 0xff900000
e3b39f84	58	#define MV_INITRD_LENGTH 0x00400000
5e0de0e2 AS	59	#define MV_SCRATCH_ADDR 0x00000000
5e0de0e2 AS	60	#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
3202d331 PT	61	#define MV_SCRIPT_ADDR 0xff840000
3202d331 PT	62	#define MV_SCRIPT_ADDR2 0xff850000
5e0de0e2 AS	63	#define MV_DTB_ADDR 0xfffc0000
	64
	65	#define CONFIG_SHOW_BOOT_PROGRESS 1
	66
	67	#define MV_KERNEL_ADDR_RAM 0x00100000
	68	#define MV_DTB_ADDR_RAM 0x00600000
	69	#define MV_INITRD_ADDR_RAM 0x01000000
	70
	71	/* pass open firmware flat tree */
	72	#define CONFIG_OF_LIBFDT 1
	73	#define CONFIG_OF_BOARD_SETUP 1
	74
	75	#define OF_CPU "PowerPC,5200@0"
	76	#define OF_SOC "soc5200@f0000000"
	77	#define OF_TBCLK (bd->bi_busfreq / 4)
	78	#define MV_DTB_NAME mvbc-p.dtb
	79	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	80
	81	/*
	82	* Supported commands
	83	*/
	84	#include <config_cmd_default.h>
	85
	86	#define CONFIG_CMD_CACHE
	87	#define CONFIG_CMD_NET
	88	#define CONFIG_CMD_PING
	89	#define CONFIG_CMD_DHCP
	90	#define CONFIG_CMD_SDRAM
	91	#define CONFIG_CMD_PCI
	92	#define CONFIG_CMD_FPGA
e3b39f84	93	#define CONFIG_CMD_I2C
5e0de0e2 AS	94
	95	#undef CONFIG_WATCHDOG
	96
	97	#define CONFIG_BOOTP_VENDOREX
	98	#define CONFIG_BOOTP_SUBNETMASK
	99	#define CONFIG_BOOTP_GATEWAY
	100	#define CONFIG_BOOTP_DNS
	101	#define CONFIG_BOOTP_DNS2
	102	#define CONFIG_BOOTP_HOSTNAME
	103	#define CONFIG_BOOTP_BOOTFILESIZE
	104	#define CONFIG_BOOTP_BOOTPATH
	105	#define CONFIG_BOOTP_NTPSERVER
	106	#define CONFIG_BOOTP_RANDOM_DELAY
	107	#define CONFIG_BOOTP_SEND_HOSTNAME
	108
	109	/*
	110	* Autoboot
	111	*/
	112	#define CONFIG_BOOTDELAY 2
	113	#define CONFIG_AUTOBOOT_KEYED
	114	#define CONFIG_AUTOBOOT_STOP_STR "s"
	115	#define CONFIG_ZERO_BOOTDELAY_CHECK
	116	#define CONFIG_RESET_TO_RETRY 1000
	117
3202d331 PT	118	#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
	119	then source ${script_addr}; \
	120	else source ${script_addr2}; \
5e0de0e2 AS	121	fi;"
	122
	123	#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
	124	#define CONFIG_ENV_OVERWRITE
	125
5e0de0e2 AS	126	#define CONFIG_EXTRA_ENV_SETTINGS \
	127	"console_nr=0\0" \
	128	"console=yes\0" \
	129	"stdin=serial\0" \
	130	"stdout=serial\0" \
	131	"stderr=serial\0" \
	132	"fpga=0\0" \
5368c55d MV	133	"fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
	134	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
	135	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
	136	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
	137	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
	138	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
	139	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
	140	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
	141	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
	142	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
	143	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
	144	"dtb_name=" __stringify(MV_DTB_NAME) "\0" \
	145	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
	146	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
5e0de0e2	147	"mv_version=" U_BOOT_VERSION "\0" \
5368c55d MV	148	"dhcp_client_id=" __stringify(MV_CI) "\0" \
5368c55d MV	149	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
5e0de0e2 AS	150	"netretry=no\0" \
	151	"use_static_ipaddr=no\0" \
	152	"static_ipaddr=192.168.90.10\0" \
	153	"static_netmask=255.255.255.0\0" \
	154	"static_gateway=0.0.0.0\0" \
	155	"initrd_name=uInitrd.mvbc-p-rfs\0" \
	156	"zcip=no\0" \
	157	"netboot=yes\0" \
	158	"mvtest=Ff\0" \
	159	"tried_bootfromflash=no\0" \
	160	"tried_bootfromnet=no\0" \
	161	"use_dhcp=yes\0" \
	162	"gev_start=yes\0" \
	163	"mvbcdma_debug=0\0" \
	164	"mvbcia_debug=0\0" \
	165	"propdev_debug=0\0" \
	166	"gevss_debug=0\0" \
	167	"watchdog=1\0" \
e3b39f84	168	"sensor_cnt=1\0" \
5e0de0e2 AS	169	""
5e0de0e2 AS	170
5e0de0e2 AS	171	/*
	172	* IPB Bus clocking configuration.
	173	*/
6d0f6bcf JCPV	174	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
6d0f6bcf JCPV	175	#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
5e0de0e2 AS	176
	177	/*
	178	* Flash configuration
	179	*/
	180	#undef CONFIG_FLASH_16BIT
6d0f6bcf	181	#define CONFIG_SYS_FLASH_CFI
00b1883a	182	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	183	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
6d0f6bcf JCPV	184	#define CONFIG_SYS_FLASH_EMPTY_INFO
5e0de0e2	185
6d0f6bcf JCPV	186	#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
6d0f6bcf JCPV	187	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
5e0de0e2	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_MAX_FLASH_BANKS 1
6d0f6bcf JCPV	190	#define CONFIG_SYS_MAX_FLASH_SECT 256
5e0de0e2	191
6d0f6bcf	192	#define CONFIG_SYS_LOWBOOT
14d0a02a	193	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	194	#define CONFIG_SYS_FLASH_SIZE 0x00800000
5e0de0e2 AS	195
	196	/*
	197	* Environment settings
	198	*/
5a1aceb0	199	#define CONFIG_ENV_IS_IN_FLASH
6d0f6bcf	200	#undef CONFIG_SYS_FLASH_PROTECTION
5e0de0e2	201
0e8d1586 JCPV	202	#define CONFIG_ENV_ADDR 0xFFFE0000
	203	#define CONFIG_ENV_SIZE 0x10000
	204	#define CONFIG_ENV_SECT_SIZE 0x10000
	205	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
	206	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
5e0de0e2 AS	207
	208	/*
	209	* Memory map
	210	*/
6d0f6bcf JCPV	211	#define CONFIG_SYS_MBAR 0xF0000000
	212	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	213	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
5e0de0e2	214
6d0f6bcf	215	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	216	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
5e0de0e2	217
25ddd1fb	218	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	219	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e0de0e2	220
14d0a02a	221	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	222	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	223	#define CONFIG_SYS_RAMBOOT 1
5e0de0e2 AS	224	#endif
5e0de0e2 AS	225
6d0f6bcf JCPV	226	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
	227	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
	228	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	229	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
5e0de0e2	230
e3b39f84 AS	231	/*
	232	* I2C configuration
	233	*/
	234	#define CONFIG_HARD_I2C 1
	235	#define CONFIG_SYS_I2C_MODULE 1
	236	#define CONFIG_SYS_I2C_SPEED 86000
	237	#define CONFIG_SYS_I2C_SLAVE 0x7F
	238
5e0de0e2 AS	239	/*
	240	* Ethernet configuration
	241	*/
5e0de0e2 AS	242	#define CONFIG_NET_RETRY_COUNT 5
	243
	244	#define CONFIG_E1000
c4ec6db0	245	#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
5e0de0e2 AS	246	#undef CONFIG_MPC5xxx_FEC
	247	#undef CONFIG_PHY_ADDR
	248	#define CONFIG_NETDEV eth0
	249
	250	/*
	251	* Miscellaneous configurable options
	252	*/
6d0f6bcf	253	#define CONFIG_SYS_HUSH_PARSER
5e0de0e2	254	#define CONFIG_CMDLINE_EDITING
6d0f6bcf JCPV	255	#undef CONFIG_SYS_LONGHELP
6d0f6bcf JCPV	256	#define CONFIG_SYS_PROMPT "=> "
17e900b8	257	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	258	#define CONFIG_SYS_CBSIZE 1024
5e0de0e2	259	#else
6d0f6bcf	260	#define CONFIG_SYS_CBSIZE 256
5e0de0e2	261	#endif
6d0f6bcf JCPV	262	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	263	#define CONFIG_SYS_MAXARGS 16
	264	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
5e0de0e2	265
6d0f6bcf JCPV	266	#define CONFIG_SYS_MEMTEST_START 0x00800000
6d0f6bcf JCPV	267	#define CONFIG_SYS_MEMTEST_END 0x02f00000
5e0de0e2	268
6d0f6bcf	269	#define CONFIG_SYS_HZ 1000
5e0de0e2 AS	270
5e0de0e2 AS	271	/* default load address */
6d0f6bcf	272	#define CONFIG_SYS_LOAD_ADDR 0x02000000
5e0de0e2 AS	273	/* default location for tftp and bootm */
	274	#define CONFIG_LOADADDR 0x00200000
	275
	276	/*
	277	* Various low-level settings
	278	*/
6d0f6bcf	279	#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
5e0de0e2	280
6d0f6bcf JCPV	281	#define CONFIG_SYS_HID0_INIT (HID0_ICE \| HID0_ICFI)
6d0f6bcf JCPV	282	#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e0de0e2	283
6d0f6bcf JCPV	284	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	285	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	286	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
	287	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	288	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e0de0e2	289
6d0f6bcf JCPV	290	#define CONFIG_SYS_CS_BURST 0x000000f0
6d0f6bcf JCPV	291	#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
5e0de0e2	292
6d0f6bcf	293	#define CONFIG_SYS_RESET_ADDRESS 0x00000100
5e0de0e2 AS	294
5e0de0e2 AS	295	#undef FPGA_DEBUG
6d0f6bcf	296	#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
b03b25ca	297	#define CONFIG_FPGA
5e0de0e2 AS	298	#define CONFIG_FPGA_ALTERA 1
	299	#define CONFIG_FPGA_CYCLON2 1
	300	#define CONFIG_FPGA_COUNT 1
	301
	302	#endif