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Commit | Line | Data |
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c005b939 AS |
1 | /* |
2 | * Copyright (C) Matrix Vision GmbH 2008 | |
3 | * | |
4 | * Matrix Vision mvBlueLYNX-M7 configuration file | |
5 | * based on Freescale's MPC8349ITX. | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
c005b939 AS |
8 | */ |
9 | ||
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
5ed546fd | 14 | #include <version.h> |
c005b939 AS |
15 | |
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
19 | #define CONFIG_E300 1 | |
2c7920af | 20 | #define CONFIG_MPC834x 1 |
c005b939 AS |
21 | #define CONFIG_MPC8343 1 |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
24 | ||
6d0f6bcf | 25 | #define CONFIG_SYS_IMMR 0xE0000000 |
c005b939 AS |
26 | |
27 | #define CONFIG_PCI | |
842033e6 | 28 | #define CONFIG_PCI_INDIRECT_BRIDGE |
c005b939 | 29 | #define CONFIG_PCI_SKIP_HOST_BRIDGE |
c005b939 AS |
30 | #define CONFIG_TSEC_ENET |
31 | #define CONFIG_MPC8XXX_SPI | |
32 | #define CONFIG_HARD_SPI | |
33 | #define MVBLM7_MMC_CS 0x04000000 | |
28887d83 | 34 | #define CONFIG_MISC_INIT_R |
c005b939 AS |
35 | |
36 | /* I2C */ | |
00f792e0 HS |
37 | #define CONFIG_SYS_I2C |
38 | #define CONFIG_SYS_I2C_FSL | |
39 | #define CONFIG_SYS_FSL_I2C_SPEED 100000 | |
40 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
41 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
42 | #define CONFIG_SYS_FSL_I2C2_SPEED 100000 | |
43 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
44 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
c005b939 AS |
45 | |
46 | /* | |
47 | * DDR Setup | |
48 | */ | |
28887d83 AS |
49 | #undef CONFIG_SPD_EEPROM |
50 | ||
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_DDR_BASE 0x00000000 |
52 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
53 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
54 | #define CONFIG_SYS_83XX_DDR_USES_CS0 1 | |
55 | #define CONFIG_SYS_MEMTEST_START (60<<20) | |
56 | #define CONFIG_SYS_MEMTEST_END (70<<20) | |
28887d83 | 57 | #define CONFIG_VERY_BIG_RAM |
6d0f6bcf | 58 | |
2fef4020 JH |
59 | #define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \ |
60 | | DDRCDR_NZ_HIZ \ | |
61 | | DDRCDR_Q_DRN) | |
62 | /* 0x22000001 */ | |
28887d83 | 63 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 |
c005b939 | 64 | |
28887d83 | 65 | #define CONFIG_SYS_DDR_SIZE 512 |
c005b939 | 66 | |
28887d83 | 67 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
c005b939 | 68 | |
28887d83 | 69 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
c005b939 | 70 | |
28887d83 AS |
71 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
72 | #define CONFIG_SYS_DDR_TIMING_1 0x3837c322 | |
73 | #define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 | |
74 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
c005b939 | 75 | |
28887d83 | 76 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 |
6d0f6bcf | 77 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
28887d83 | 78 | #define CONFIG_SYS_DDR_INTERVAL 0x02000100 |
c005b939 | 79 | |
28887d83 AS |
80 | #define CONFIG_SYS_DDR_MODE 0x04040242 |
81 | #define CONFIG_SYS_DDR_MODE2 0x00800000 | |
c005b939 AS |
82 | |
83 | /* Flash */ | |
6d0f6bcf | 84 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 85 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
87 | ||
88 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 | |
89 | #define CONFIG_SYS_FLASH_SIZE 8 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
91 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 | |
92 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
93 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
94 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
95 | ||
7d6a0982 JH |
96 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
97 | | BR_PS_16 \ | |
98 | | BR_MS_GPCM \ | |
99 | | BR_V) | |
100 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
b2773a5e JH |
101 | | OR_UPM_XAM \ |
102 | | OR_GPCM_CSNT \ | |
103 | | OR_GPCM_ACS_DIV2 \ | |
104 | | OR_GPCM_XACS \ | |
105 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
106 | | OR_GPCM_TRLX_SET \ |
107 | | OR_GPCM_EHTR_SET \ | |
b2773a5e | 108 | | OR_GPCM_EAD) |
6d0f6bcf | 109 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 110 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
c005b939 AS |
111 | |
112 | /* | |
113 | * U-Boot memory configuration | |
114 | */ | |
14d0a02a | 115 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 116 | #undef CONFIG_SYS_RAMBOOT |
c005b939 | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_INIT_RAM_LOCK |
b2773a5e JH |
119 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
120 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
c005b939 | 121 | |
b2773a5e JH |
122 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
123 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 124 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c005b939 | 125 | |
6d0f6bcf JCPV |
126 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
127 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
128 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
c005b939 AS |
129 | |
130 | /* | |
131 | * Local Bus LCRR and LBCR regs | |
132 | * LCRR: DLL bypass, Clock divider is 4 | |
133 | * External Local Bus rate is | |
134 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
135 | */ | |
c7190f02 KP |
136 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
137 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 138 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
c005b939 AS |
139 | |
140 | /* LB sdram refresh timer, about 6us */ | |
6d0f6bcf | 141 | #define CONFIG_SYS_LBC_LSRT 0x32000000 |
c005b939 | 142 | /* LB refresh timer prescal, 266MHz/32*/ |
6d0f6bcf | 143 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 |
c005b939 AS |
144 | |
145 | /* | |
146 | * Serial Port | |
147 | */ | |
148 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_NS16550 |
150 | #define CONFIG_SYS_NS16550_SERIAL | |
151 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
152 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
c005b939 | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
b2773a5e | 155 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
c005b939 AS |
156 | |
157 | #define CONFIG_CONSOLE ttyS0 | |
158 | #define CONFIG_BAUDRATE 115200 | |
159 | ||
6d0f6bcf JCPV |
160 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
161 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
c005b939 AS |
162 | |
163 | /* pass open firmware flat tree */ | |
164 | #define CONFIG_OF_LIBFDT 1 | |
165 | #define CONFIG_OF_BOARD_SETUP 1 | |
166 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
167 | #define MV_DTB_NAME "mvblm7.dtb" | |
168 | ||
169 | /* | |
170 | * PCI | |
171 | */ | |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
173 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
174 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 | |
b2773a5e JH |
175 | #define CONFIG_SYS_PCI1_MMIO_BASE \ |
176 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
178 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 | |
179 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
180 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
181 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 | |
c005b939 | 182 | |
c005b939 AS |
183 | #define CONFIG_NET_RETRY_COUNT 3 |
184 | ||
2ae18241 | 185 | #define CONFIG_PCI_66M |
c005b939 AS |
186 | #define CONFIG_83XX_CLKIN 66666667 |
187 | #define CONFIG_PCI_PNP | |
188 | #define CONFIG_PCI_SCAN_SHOW | |
189 | ||
190 | /* TSEC */ | |
191 | #define CONFIG_GMII | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_VSC8601_SKEWFIX |
193 | #define CONFIG_SYS_VSC8601_SKEW_TX 3 | |
194 | #define CONFIG_SYS_VSC8601_SKEW_RX 3 | |
c005b939 AS |
195 | |
196 | #define CONFIG_TSEC1 | |
197 | #define CONFIG_TSEC2 | |
198 | ||
199 | #define CONFIG_HAS_ETH0 | |
200 | #define CONFIG_TSEC1_NAME "TSEC0" | |
201 | #define CONFIG_FEC1_PHY_NORXERR | |
6d0f6bcf | 202 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
b2773a5e | 203 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
c005b939 AS |
204 | #define TSEC1_PHY_ADDR 0x10 |
205 | #define TSEC1_PHYIDX 0 | |
206 | #define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) | |
207 | ||
208 | #define CONFIG_HAS_ETH1 | |
b2773a5e | 209 | #define CONFIG_TSEC2_NAME "TSEC1" |
c005b939 | 210 | #define CONFIG_FEC2_PHY_NORXERR |
6d0f6bcf | 211 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
b2773a5e | 212 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
c005b939 AS |
213 | #define TSEC2_PHY_ADDR 0x11 |
214 | #define TSEC2_PHYIDX 0 | |
215 | #define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) | |
216 | ||
217 | #define CONFIG_ETHPRIME "TSEC0" | |
218 | ||
219 | #define CONFIG_BOOTP_VENDOREX | |
220 | #define CONFIG_BOOTP_SUBNETMASK | |
221 | #define CONFIG_BOOTP_GATEWAY | |
222 | #define CONFIG_BOOTP_DNS | |
223 | #define CONFIG_BOOTP_DNS2 | |
224 | #define CONFIG_BOOTP_HOSTNAME | |
225 | #define CONFIG_BOOTP_BOOTFILESIZE | |
226 | #define CONFIG_BOOTP_BOOTPATH | |
227 | #define CONFIG_BOOTP_NTPSERVER | |
228 | #define CONFIG_BOOTP_RANDOM_DELAY | |
229 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
230 | ||
231 | /* USB */ | |
fd194f82 AS |
232 | #define CONFIG_SYS_USB_HOST |
233 | #define CONFIG_USB_EHCI | |
234 | #define CONFIG_USB_EHCI_FSL | |
c005b939 | 235 | #define CONFIG_HAS_FSL_DR_USB |
fd194f82 | 236 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
c005b939 AS |
237 | |
238 | /* | |
239 | * Environment | |
240 | */ | |
6d0f6bcf | 241 | #undef CONFIG_SYS_FLASH_PROTECTION |
c005b939 AS |
242 | #define CONFIG_ENV_OVERWRITE |
243 | ||
5a1aceb0 | 244 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
245 | #define CONFIG_ENV_ADDR 0xFF800000 |
246 | #define CONFIG_ENV_SIZE 0x2000 | |
247 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
248 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) | |
b2773a5e | 249 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
c005b939 | 250 | |
e093a247 | 251 | #define CONFIG_LOADS_ECHO |
6d0f6bcf | 252 | #define CONFIG_SYS_LOADS_BAUD_CHANGE |
c005b939 AS |
253 | |
254 | /* | |
255 | * Command line configuration. | |
256 | */ | |
257 | #include <config_cmd_default.h> | |
258 | ||
259 | #define CONFIG_CMD_CACHE | |
260 | #define CONFIG_CMD_IRQ | |
261 | #define CONFIG_CMD_NET | |
262 | #define CONFIG_CMD_MII | |
263 | #define CONFIG_CMD_PING | |
264 | #define CONFIG_CMD_DHCP | |
265 | #define CONFIG_CMD_SDRAM | |
266 | #define CONFIG_CMD_PCI | |
267 | #define CONFIG_CMD_I2C | |
268 | #define CONFIG_CMD_FPGA | |
fd194f82 AS |
269 | #define CONFIG_CMD_USB |
270 | #define CONFIG_DOS_PARTITION | |
c005b939 AS |
271 | |
272 | #undef CONFIG_WATCHDOG | |
273 | ||
274 | /* | |
275 | * Miscellaneous configurable options | |
276 | */ | |
6d0f6bcf | 277 | #define CONFIG_SYS_LONGHELP |
c005b939 | 278 | #define CONFIG_CMDLINE_EDITING |
b2773a5e | 279 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
6d0f6bcf | 280 | #define CONFIG_SYS_HUSH_PARSER |
c005b939 AS |
281 | |
282 | /* default load address */ | |
6d0f6bcf | 283 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 |
c005b939 AS |
284 | /* default location for tftp and bootm */ |
285 | #define CONFIG_LOADADDR 0x200000 | |
286 | ||
6d0f6bcf JCPV |
287 | #define CONFIG_SYS_PROMPT "mvBL-M7> " |
288 | #define CONFIG_SYS_CBSIZE 256 | |
c005b939 | 289 | |
b2773a5e JH |
290 | #define CONFIG_SYS_PBSIZE \ |
291 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_MAXARGS 16 |
293 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
c005b939 AS |
294 | |
295 | /* | |
296 | * For booting Linux, the board info and command line data | |
9f530d59 | 297 | * have to be in the first 256 MB of memory, since this is |
c005b939 AS |
298 | * the maximum mapped by the Linux kernel during initialization. |
299 | */ | |
b2773a5e JH |
300 | /* Initial Memory map for Linux*/ |
301 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
c005b939 | 302 | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_HRCW_LOW 0x0 |
304 | #define CONFIG_SYS_HRCW_HIGH 0x0 | |
c005b939 AS |
305 | |
306 | /* | |
307 | * System performance | |
308 | */ | |
6d0f6bcf | 309 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
b2773a5e | 310 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
312 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
c005b939 AS |
313 | |
314 | /* clocking */ | |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_SCCR_ENCCM 0 |
316 | #define CONFIG_SYS_SCCR_USBMPHCM 0 | |
317 | #define CONFIG_SYS_SCCR_USBDRCM 2 | |
318 | #define CONFIG_SYS_SCCR_TSEC1CM 1 | |
319 | #define CONFIG_SYS_SCCR_TSEC2CM 1 | |
c005b939 | 320 | |
116ef54d | 321 | #define CONFIG_SYS_SICRH 0x1fef0003 |
6d0f6bcf | 322 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) |
c005b939 | 323 | |
6d0f6bcf | 324 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
1a2e203b KP |
325 | #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ |
326 | HID0_ENABLE_INSTRUCTION_CACHE) | |
c005b939 | 327 | |
6d0f6bcf | 328 | #define CONFIG_SYS_HID2 HID2_HBE |
5ed546fd | 329 | #define CONFIG_HIGH_BATS 1 |
c005b939 AS |
330 | |
331 | /* DDR */ | |
b2773a5e | 332 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 333 | | BATL_PP_RW \ |
b2773a5e JH |
334 | | BATL_MEMCOHERENCE) |
335 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
336 | | BATU_BL_256M \ | |
337 | | BATU_VS \ | |
338 | | BATU_VP) | |
c005b939 AS |
339 | |
340 | /* PCI */ | |
b2773a5e | 341 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 342 | | BATL_PP_RW \ |
b2773a5e JH |
343 | | BATL_MEMCOHERENCE) |
344 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
345 | | BATU_BL_256M \ | |
346 | | BATU_VS \ | |
347 | | BATU_VP) | |
348 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 349 | | BATL_PP_RW \ |
b2773a5e JH |
350 | | BATL_CACHEINHIBIT \ |
351 | | BATL_GUARDEDSTORAGE) | |
352 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
353 | | BATU_BL_256M \ | |
354 | | BATU_VS \ | |
355 | | BATU_VP) | |
c005b939 AS |
356 | |
357 | /* no PCI2 */ | |
6d0f6bcf JCPV |
358 | #define CONFIG_SYS_IBAT3L 0 |
359 | #define CONFIG_SYS_IBAT3U 0 | |
360 | #define CONFIG_SYS_IBAT4L 0 | |
361 | #define CONFIG_SYS_IBAT4U 0 | |
c005b939 AS |
362 | |
363 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
b2773a5e | 364 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 365 | | BATL_PP_RW \ |
b2773a5e JH |
366 | | BATL_CACHEINHIBIT \ |
367 | | BATL_GUARDEDSTORAGE) | |
368 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
369 | | BATU_BL_256M \ | |
370 | | BATU_VS \ | |
371 | | BATU_VP) | |
c005b939 AS |
372 | |
373 | /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ | |
b2773a5e | 374 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 | 375 | | BATL_PP_RW \ |
b2773a5e | 376 | | BATL_MEMCOHERENCE \ |
72cd4087 | 377 | | BATL_GUARDEDSTORAGE) |
b2773a5e JH |
378 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ |
379 | | BATU_BL_256M \ | |
380 | | BATU_VS \ | |
381 | | BATU_VP) | |
6d0f6bcf JCPV |
382 | #define CONFIG_SYS_IBAT7L 0 |
383 | #define CONFIG_SYS_IBAT7U 0 | |
384 | ||
385 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
386 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
387 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
388 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
389 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
390 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
391 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
392 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
393 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
394 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
395 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
396 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
397 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
398 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
399 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
400 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
c005b939 | 401 | |
c005b939 AS |
402 | /* |
403 | * Environment Configuration | |
404 | */ | |
405 | #define CONFIG_ENV_OVERWRITE | |
406 | ||
407 | #define CONFIG_NETDEV eth0 | |
408 | ||
409 | /* Default path and filenames */ | |
410 | #define CONFIG_BOOTDELAY 5 | |
411 | #define CONFIG_AUTOBOOT_KEYED | |
412 | #define CONFIG_AUTOBOOT_STOP_STR "s" | |
413 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
414 | #define CONFIG_RESET_TO_RETRY 1000 | |
415 | ||
b2773a5e JH |
416 | #define MV_CI "mvBL-M7" |
417 | #define MV_VCI "mvBL-M7" | |
28887d83 AS |
418 | #define MV_FPGA_DATA 0xfff40000 |
419 | #define MV_FPGA_SIZE 0 | |
1a9eeb78 AS |
420 | #define MV_KERNEL_ADDR 0xff810000 |
421 | #define MV_INITRD_ADDR 0xffb00000 | |
3202d331 PT |
422 | #define MV_SCRIPT_ADDR 0xff804000 |
423 | #define MV_SCRIPT_ADDR2 0xff806000 | |
1a9eeb78 AS |
424 | #define MV_DTB_ADDR 0xff808000 |
425 | #define MV_INITRD_LENGTH 0x00400000 | |
c005b939 AS |
426 | |
427 | #define CONFIG_SHOW_BOOT_PROGRESS 1 | |
428 | ||
1a9eeb78 AS |
429 | #define MV_KERNEL_ADDR_RAM 0x00100000 |
430 | #define MV_DTB_ADDR_RAM 0x00600000 | |
431 | #define MV_INITRD_ADDR_RAM 0x01000000 | |
c005b939 | 432 | |
b2773a5e JH |
433 | #define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \ |
434 | "then source ${script_addr}; " \ | |
435 | "else source ${script_addr2}; " \ | |
436 | "fi;" | |
c005b939 AS |
437 | #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" |
438 | ||
439 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
440 | "console_nr=0\0" \ | |
5368c55d | 441 | "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \ |
c005b939 AS |
442 | "stdin=serial\0" \ |
443 | "stdout=serial\0" \ | |
444 | "stderr=serial\0" \ | |
445 | "fpga=0\0" \ | |
5368c55d MV |
446 | "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \ |
447 | "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \ | |
448 | "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \ | |
449 | "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \ | |
450 | "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \ | |
451 | "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \ | |
452 | "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \ | |
453 | "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \ | |
454 | "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \ | |
455 | "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \ | |
456 | "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \ | |
457 | "dtb_name=" __stringify(MV_DTB_NAME) "\0" \ | |
5ed546fd | 458 | "mv_version=" U_BOOT_VERSION "\0" \ |
b2773a5e JH |
459 | "dhcp_client_id=" MV_CI "\0" \ |
460 | "dhcp_vendor-class-identifier=" MV_VCI "\0" \ | |
c005b939 AS |
461 | "netretry=no\0" \ |
462 | "use_static_ipaddr=no\0" \ | |
463 | "static_ipaddr=192.168.90.10\0" \ | |
464 | "static_netmask=255.255.255.0\0" \ | |
465 | "static_gateway=0.0.0.0\0" \ | |
28887d83 | 466 | "initrd_name=uInitrd.mvBL-M7-rfs\0" \ |
c005b939 AS |
467 | "zcip=no\0" \ |
468 | "netboot=yes\0" \ | |
469 | "mvtest=Ff\0" \ | |
470 | "tried_bootfromflash=no\0" \ | |
471 | "tried_bootfromnet=no\0" \ | |
472 | "bootfile=mvblm72625.boot\0" \ | |
473 | "use_dhcp=yes\0" \ | |
474 | "gev_start=yes\0" \ | |
475 | "mvbcdma_debug=0\0" \ | |
476 | "mvbcia_debug=0\0" \ | |
477 | "propdev_debug=0\0" \ | |
478 | "gevss_debug=0\0" \ | |
479 | "watchdog=0\0" \ | |
480 | "usb_dr_mode=host\0" \ | |
1a9eeb78 | 481 | "sensor_cnt=2\0" \ |
c005b939 AS |
482 | "" |
483 | ||
484 | #define CONFIG_FPGA_COUNT 1 | |
b03b25ca | 485 | #define CONFIG_FPGA |
c005b939 AS |
486 | #define CONFIG_FPGA_ALTERA |
487 | #define CONFIG_FPGA_CYCLON2 | |
488 | ||
489 | #endif |