[people/ms/u-boot.git] / include / configs / MVBLM7.h

/*
 * Copyright (C) Matrix Vision GmbH 2008
 *
 * Matrix Vision mvBlueLYNX-M7 configuration file
 * based on Freescale's MPC8349ITX.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#ifndef __CONFIG_H
#define __CONFIG_H

#include <version.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_E300	1
#define CONFIG_MPC83xx	1
#define CONFIG_MPC834x	1
#define CONFIG_MPC8343	1

#define CONFIG_SYS_IMMR		0xE0000000

#define CONFIG_PCI
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET
#define CONFIG_MPC8XXX_SPI
#define CONFIG_HARD_SPI
#define MVBLM7_MMC_CS   0x04000000
#define CONFIG_MISC_INIT_R

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100

#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * DDR Setup
 */
#undef	CONFIG_SPD_EEPROM

#define CONFIG_SYS_DDR_BASE		0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_83XX_DDR_USES_CS0	1
#define CONFIG_SYS_MEMTEST_START	(60<<20)
#define CONFIG_SYS_MEMTEST_END		(70<<20)
#define CONFIG_VERY_BIG_RAM

#define CONFIG_SYS_DDRCDR		0x22000001
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05

#define CONFIG_SYS_DDR_SIZE		512

#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202

#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f

#define CONFIG_SYS_DDR_TIMING_0		0x00260802
#define CONFIG_SYS_DDR_TIMING_1		0x3837c322
#define CONFIG_SYS_DDR_TIMING_2		0x0f9848c6
#define CONFIG_SYS_DDR_TIMING_3		0x00000000

#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080008
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#define CONFIG_SYS_DDR_INTERVAL		0x02000100

#define CONFIG_SYS_DDR_MODE		0x04040242
#define CONFIG_SYS_DDR_MODE2		0x00800000

/* Flash */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFF800000
#define CONFIG_SYS_FLASH_SIZE		8
#define CONFIG_SYS_FLASH_SIZE_SHIFT	3
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM |  \
				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\
				OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \
				OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))

/*
 * U-Boot memory configuration
 */
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
#undef	CONFIG_SYS_RAMBOOT

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END	0x1000		/* End of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)

/*
 * Local Bus LCRR and LBCR regs
 *  LCRR:  DLL bypass, Clock divider is 4
 * External Local Bus rate is
 *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
#define CONFIG_SYS_LBC_LBCR	0x00000000

/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT	0x32000000
/* LB refresh timer prescal, 266MHz/32*/
#define CONFIG_SYS_LBC_MRTPR	0x20000000

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_CONSOLE		ttyS0
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1
#define MV_DTB_NAME	"mvblm7.dtb"

/*
 * PCI
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCI1_MMIO_BASE	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000
#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
#define CONFIG_NET_RETRY_COUNT	3

#define PCI_66M
#define CONFIG_83XX_CLKIN	66666667
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW

/* TSEC */
#define CONFIG_GMII
#define CONFIG_SYS_VSC8601_SKEWFIX
#define	CONFIG_SYS_VSC8601_SKEW_TX	3
#define	CONFIG_SYS_VSC8601_SKEW_RX	3

#define CONFIG_TSEC1
#define CONFIG_TSEC2

#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_FEC1_PHY_NORXERR
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define TSEC1_PHY_ADDR		0x10
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)

#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME  	"TSEC1"
#define CONFIG_FEC2_PHY_NORXERR
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2 		(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
#define TSEC2_PHY_ADDR		0x11
#define TSEC2_PHYIDX		0
#define TSEC2_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)

#define CONFIG_ETHPRIME		"TSEC0"

#define CONFIG_BOOTP_VENDOREX
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME

/* USB */
#define CONFIG_HAS_FSL_DR_USB

/*
 * Environment
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0xFF800000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND 	CONFIG_ENV_SIZE

#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_I2C
#define CONFIG_CMD_FPGA

#undef CONFIG_WATCHDOG

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "

/* default load address */
#define CONFIG_SYS_LOAD_ADDR	0x2000000
/* default location for tftp and bootm */
#define CONFIG_LOADADDR	0x200000

#define CONFIG_SYS_PROMPT	"mvBL-M7> "
#define CONFIG_SYS_CBSIZE	256

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ		1000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

#define CONFIG_SYS_HRCW_LOW	0x0
#define CONFIG_SYS_HRCW_HIGH	0x0

/*
 * System performance
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */

/* clocking */
#define CONFIG_SYS_SCCR_ENCCM		0
#define CONFIG_SYS_SCCR_USBMPHCM	0
#define	CONFIG_SYS_SCCR_USBDRCM	2
#define CONFIG_SYS_SCCR_TSEC1CM	1
#define CONFIG_SYS_SCCR_TSEC2CM	1

#define CONFIG_SYS_SICRH	0x1fff8003
#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	CONFIG_SYS_HID0_INIT

#define CONFIG_SYS_HID2	HID2_HBE
#define CONFIG_HIGH_BATS	1

/* DDR  */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* PCI  */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\
				BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* no PCI2 */
#define CONFIG_SYS_IBAT3L	0
#define CONFIG_SYS_IBAT3U	0
#define CONFIG_SYS_IBAT4L	0
#define CONFIG_SYS_IBAT4U	0

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
				BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)

/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
				 BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT7L	0
#define CONFIG_SYS_IBAT7U	0

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02	/* Software reboot */


/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		eth0

/* Default path and filenames */
#define CONFIG_BOOTDELAY		5
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR	"s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY		1000

#define MV_CI			mvBL-M7
#define MV_VCI			mvBL-M7
#define MV_FPGA_DATA		0xfff40000
#define MV_FPGA_SIZE		0
#define MV_KERNEL_ADDR		0xff810000
#define MV_INITRD_ADDR		0xffb00000
#define MV_SCRIPT_ADDR		0xff804000
#define MV_SCRIPT_ADDR2		0xff806000
#define MV_DTB_ADDR		0xff808000
#define MV_INITRD_LENGTH	0x00400000

#define CONFIG_SHOW_BOOT_PROGRESS 1

#define MV_KERNEL_ADDR_RAM	0x00100000
#define MV_DTB_ADDR_RAM		0x00600000
#define MV_INITRD_ADDR_RAM	0x01000000

#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; \
					then source ${script_addr};  \
					else source ${script_addr2}; \
				fi;"
#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"console_nr=0\0"					\
	"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" 		\
	"stdin=serial\0"					\
	"stdout=serial\0"					\
	"stderr=serial\0"					\
	"fpga=0\0"						\
	"fpgadata=" MK_STR(MV_FPGA_DATA) "\0"			\
	"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"		\
	"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0"		\
	"script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0"		\
	"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0"		\
	"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"	\
	"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0"		\
	"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"	\
	"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0"	\
	"mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0"			\
	"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"		\
	"dtb_name=" MK_STR(MV_DTB_NAME) "\0"			\
	"mv_version=" U_BOOT_VERSION "\0"			\
	"dhcp_client_id=" MK_STR(MV_CI) "\0"			\
	"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"	\
	"netretry=no\0"						\
	"use_static_ipaddr=no\0"				\
	"static_ipaddr=192.168.90.10\0"				\
	"static_netmask=255.255.255.0\0"			\
	"static_gateway=0.0.0.0\0"				\
	"initrd_name=uInitrd.mvBL-M7-rfs\0"			\
	"zcip=no\0"						\
	"netboot=yes\0"						\
	"mvtest=Ff\0"						\
	"tried_bootfromflash=no\0"				\
	"tried_bootfromnet=no\0"				\
	"bootfile=mvblm72625.boot\0"				\
	"use_dhcp=yes\0"					\
	"gev_start=yes\0"					\
	"mvbcdma_debug=0\0"					\
	"mvbcia_debug=0\0"					\
	"propdev_debug=0\0"					\
	"gevss_debug=0\0"					\
	"watchdog=0\0"						\
	"usb_dr_mode=host\0"					\
	"sensor_cnt=2\0"					\
	""

#define CONFIG_FPGA_COUNT	1
#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2

#endif
Commit	Line	Data
c005b939 AS	1	/*
	2	* Copyright (C) Matrix Vision GmbH 2008
	3	*
	4	* Matrix Vision mvBlueLYNX-M7 configuration file
	5	* based on Freescale's MPC8349ITX.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
5ed546fd	30	#include <version.h>
c005b939 AS	31
	32	/*
	33	* High Level Configuration Options
	34	*/
	35	#define CONFIG_E300 1
0f898604	36	#define CONFIG_MPC83xx 1
2c7920af	37	#define CONFIG_MPC834x 1
c005b939 AS	38	#define CONFIG_MPC8343 1
c005b939 AS	39
6d0f6bcf	40	#define CONFIG_SYS_IMMR 0xE0000000
c005b939 AS	41
c005b939 AS	42	#define CONFIG_PCI
c005b939 AS	43	#define CONFIG_PCI_SKIP_HOST_BRIDGE
	44	#define CONFIG_HARD_I2C
	45	#define CONFIG_TSEC_ENET
	46	#define CONFIG_MPC8XXX_SPI
	47	#define CONFIG_HARD_SPI
	48	#define MVBLM7_MMC_CS 0x04000000
28887d83	49	#define CONFIG_MISC_INIT_R
c005b939 AS	50
c005b939 AS	51	/* I2C */
c005b939 AS	52	#define CONFIG_FSL_I2C
c005b939 AS	53	#define CONFIG_I2C_MULTI_BUS
6d0f6bcf JCPV	54	#define CONFIG_SYS_I2C_OFFSET 0x3000
6d0f6bcf JCPV	55	#define CONFIG_SYS_I2C2_OFFSET 0x3100
c005b939	56
6d0f6bcf JCPV	57	#define CONFIG_SYS_I2C_SPEED 100000
6d0f6bcf JCPV	58	#define CONFIG_SYS_I2C_SLAVE 0x7F
c005b939 AS	59
	60	/*
	61	* DDR Setup
	62	*/
28887d83 AS	63	#undef CONFIG_SPD_EEPROM
28887d83 AS	64
6d0f6bcf JCPV	65	#define CONFIG_SYS_DDR_BASE 0x00000000
	66	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	67	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	68	#define CONFIG_SYS_83XX_DDR_USES_CS0 1
	69	#define CONFIG_SYS_MEMTEST_START (60<<20)
	70	#define CONFIG_SYS_MEMTEST_END (70<<20)
28887d83	71	#define CONFIG_VERY_BIG_RAM
6d0f6bcf	72
28887d83 AS	73	#define CONFIG_SYS_DDRCDR 0x22000001
28887d83 AS	74	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
c005b939	75
28887d83	76	#define CONFIG_SYS_DDR_SIZE 512
c005b939	77
28887d83	78	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
c005b939	79
28887d83	80	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
c005b939	81
28887d83 AS	82	#define CONFIG_SYS_DDR_TIMING_0 0x00260802
	83	#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
	84	#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
	85	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
c005b939	86
28887d83	87	#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
6d0f6bcf	88	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
28887d83	89	#define CONFIG_SYS_DDR_INTERVAL 0x02000100
c005b939	90
28887d83 AS	91	#define CONFIG_SYS_DDR_MODE 0x04040242
28887d83 AS	92	#define CONFIG_SYS_DDR_MODE2 0x00800000
c005b939 AS	93
c005b939 AS	94	/* Flash */
6d0f6bcf	95	#define CONFIG_SYS_FLASH_CFI
00b1883a	96	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	97	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	98
	99	#define CONFIG_SYS_FLASH_BASE 0xFF800000
	100	#define CONFIG_SYS_FLASH_SIZE 8
	101	#define CONFIG_SYS_FLASH_SIZE_SHIFT 3
	102	#define CONFIG_SYS_FLASH_EMPTY_INFO
	103	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
	104	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	105	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	106	#define CONFIG_SYS_MAX_FLASH_SECT 256
	107
	108	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| BR_PS_16 \| BR_V)
	109	#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \| OR_UPM_XAM \| \
2329fe11	110	OR_GPCM_CSNT \| OR_GPCM_ACS_DIV2 \| OR_GPCM_XACS\|\
c005b939 AS	111	OR_GPCM_SCY_15 \| OR_GPCM_TRLX \| OR_GPCM_EHTR \| \
c005b939 AS	112	OR_GPCM_EAD)
6d0f6bcf JCPV	113	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	114	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT))
c005b939 AS	115
	116	/*
	117	* U-Boot memory configuration
	118	*/
6d0f6bcf JCPV	119	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
6d0f6bcf JCPV	120	#undef CONFIG_SYS_RAMBOOT
c005b939	121
6d0f6bcf JCPV	122	#define CONFIG_SYS_INIT_RAM_LOCK
	123	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
	124	#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
c005b939	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	127	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	128	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c005b939	129
6d0f6bcf JCPV	130	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
	131	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	132	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
c005b939 AS	133
	134	/*
	135	* Local Bus LCRR and LBCR regs
	136	* LCRR: DLL bypass, Clock divider is 4
	137	* External Local Bus rate is
	138	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	139	*/
6d0f6bcf JCPV	140	#define CONFIG_SYS_LCRR (LCRR_DBYP \| LCRR_CLKDIV_4)
6d0f6bcf JCPV	141	#define CONFIG_SYS_LBC_LBCR 0x00000000
c005b939 AS	142
c005b939 AS	143	/* LB sdram refresh timer, about 6us */
6d0f6bcf	144	#define CONFIG_SYS_LBC_LSRT 0x32000000
c005b939	145	/* LB refresh timer prescal, 266MHz/32*/
6d0f6bcf	146	#define CONFIG_SYS_LBC_MRTPR 0x20000000
c005b939 AS	147
	148	/*
	149	* Serial Port
	150	*/
	151	#define CONFIG_CONS_INDEX 1
	152	#undef CONFIG_SERIAL_SOFTWARE_FIFO
6d0f6bcf JCPV	153	#define CONFIG_SYS_NS16550
	154	#define CONFIG_SYS_NS16550_SERIAL
	155	#define CONFIG_SYS_NS16550_REG_SIZE 1
	156	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
c005b939	157
6d0f6bcf	158	#define CONFIG_SYS_BAUDRATE_TABLE \
c005b939 AS	159	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	160
	161	#define CONFIG_CONSOLE ttyS0
	162	#define CONFIG_BAUDRATE 115200
	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	165	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
c005b939 AS	166
	167	/* pass open firmware flat tree */
	168	#define CONFIG_OF_LIBFDT 1
	169	#define CONFIG_OF_BOARD_SETUP 1
	170	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	171	#define MV_DTB_NAME "mvblm7.dtb"
	172
	173	/*
	174	* PCI
	175	*/
6d0f6bcf JCPV	176	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	177	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	178	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
	179	#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
	180	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	181	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
	182	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	183	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	184	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
c005b939	185
c005b939 AS	186	#define CONFIG_NET_MULTI 1
	187	#define CONFIG_NET_RETRY_COUNT 3
	188
	189	#define PCI_66M
	190	#define CONFIG_83XX_CLKIN 66666667
	191	#define CONFIG_PCI_PNP
	192	#define CONFIG_PCI_SCAN_SHOW
	193
	194	/* TSEC */
	195	#define CONFIG_GMII
6d0f6bcf JCPV	196	#define CONFIG_SYS_VSC8601_SKEWFIX
	197	#define CONFIG_SYS_VSC8601_SKEW_TX 3
	198	#define CONFIG_SYS_VSC8601_SKEW_RX 3
c005b939 AS	199
	200	#define CONFIG_TSEC1
	201	#define CONFIG_TSEC2
	202
	203	#define CONFIG_HAS_ETH0
	204	#define CONFIG_TSEC1_NAME "TSEC0"
	205	#define CONFIG_FEC1_PHY_NORXERR
6d0f6bcf JCPV	206	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
6d0f6bcf JCPV	207	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
c005b939 AS	208	#define TSEC1_PHY_ADDR 0x10
	209	#define TSEC1_PHYIDX 0
	210	#define TSEC1_FLAGS (TSEC_GIGABIT\|TSEC_REDUCED)
	211
	212	#define CONFIG_HAS_ETH1
	213	#define CONFIG_TSEC2_NAME "TSEC1"
	214	#define CONFIG_FEC2_PHY_NORXERR
6d0f6bcf JCPV	215	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
6d0f6bcf JCPV	216	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
c005b939 AS	217	#define TSEC2_PHY_ADDR 0x11
	218	#define TSEC2_PHYIDX 0
	219	#define TSEC2_FLAGS (TSEC_GIGABIT\|TSEC_REDUCED)
	220
	221	#define CONFIG_ETHPRIME "TSEC0"
	222
	223	#define CONFIG_BOOTP_VENDOREX
	224	#define CONFIG_BOOTP_SUBNETMASK
	225	#define CONFIG_BOOTP_GATEWAY
	226	#define CONFIG_BOOTP_DNS
	227	#define CONFIG_BOOTP_DNS2
	228	#define CONFIG_BOOTP_HOSTNAME
	229	#define CONFIG_BOOTP_BOOTFILESIZE
	230	#define CONFIG_BOOTP_BOOTPATH
	231	#define CONFIG_BOOTP_NTPSERVER
	232	#define CONFIG_BOOTP_RANDOM_DELAY
	233	#define CONFIG_BOOTP_SEND_HOSTNAME
	234
	235	/* USB */
	236	#define CONFIG_HAS_FSL_DR_USB
	237
	238	/*
	239	* Environment
	240	*/
6d0f6bcf	241	#undef CONFIG_SYS_FLASH_PROTECTION
c005b939 AS	242	#define CONFIG_ENV_OVERWRITE
c005b939 AS	243
5a1aceb0	244	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	245	#define CONFIG_ENV_ADDR 0xFF800000
	246	#define CONFIG_ENV_SIZE 0x2000
	247	#define CONFIG_ENV_SECT_SIZE 0x2000
	248	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
	249	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
c005b939	250
e093a247	251	#define CONFIG_LOADS_ECHO
6d0f6bcf	252	#define CONFIG_SYS_LOADS_BAUD_CHANGE
c005b939 AS	253
	254	/*
	255	* Command line configuration.
	256	*/
	257	#include <config_cmd_default.h>
	258
	259	#define CONFIG_CMD_CACHE
	260	#define CONFIG_CMD_IRQ
	261	#define CONFIG_CMD_NET
	262	#define CONFIG_CMD_MII
	263	#define CONFIG_CMD_PING
	264	#define CONFIG_CMD_DHCP
	265	#define CONFIG_CMD_SDRAM
	266	#define CONFIG_CMD_PCI
	267	#define CONFIG_CMD_I2C
	268	#define CONFIG_CMD_FPGA
	269
	270	#undef CONFIG_WATCHDOG
	271
	272	/*
	273	* Miscellaneous configurable options
	274	*/
6d0f6bcf	275	#define CONFIG_SYS_LONGHELP
c005b939	276	#define CONFIG_CMDLINE_EDITING
6d0f6bcf JCPV	277	#define CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	278	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
c005b939 AS	279
c005b939 AS	280	/* default load address */
6d0f6bcf	281	#define CONFIG_SYS_LOAD_ADDR 0x2000000
c005b939 AS	282	/* default location for tftp and bootm */
	283	#define CONFIG_LOADADDR 0x200000
	284
6d0f6bcf JCPV	285	#define CONFIG_SYS_PROMPT "mvBL-M7> "
6d0f6bcf JCPV	286	#define CONFIG_SYS_CBSIZE 256
c005b939	287
6d0f6bcf JCPV	288	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	289	#define CONFIG_SYS_MAXARGS 16
	290	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	291	#define CONFIG_SYS_HZ 1000
c005b939 AS	292
	293	/*
	294	* For booting Linux, the board info and command line data
	295	* have to be in the first 8 MB of memory, since this is
	296	* the maximum mapped by the Linux kernel during initialization.
	297	*/
6d0f6bcf	298	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
c005b939	299
6d0f6bcf JCPV	300	#define CONFIG_SYS_HRCW_LOW 0x0
6d0f6bcf JCPV	301	#define CONFIG_SYS_HRCW_HIGH 0x0
c005b939 AS	302
	303	/*
	304	* System performance
	305	*/
6d0f6bcf JCPV	306	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
	307	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
	308	#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
	309	#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
c005b939 AS	310
c005b939 AS	311	/* clocking */
6d0f6bcf JCPV	312	#define CONFIG_SYS_SCCR_ENCCM 0
	313	#define CONFIG_SYS_SCCR_USBMPHCM 0
	314	#define CONFIG_SYS_SCCR_USBDRCM 2
	315	#define CONFIG_SYS_SCCR_TSEC1CM 1
	316	#define CONFIG_SYS_SCCR_TSEC2CM 1
c005b939	317
6d0f6bcf JCPV	318	#define CONFIG_SYS_SICRH 0x1fff8003
6d0f6bcf JCPV	319	#define CONFIG_SYS_SICRL (SICRL_LDP_A \| SICRL_USB1 \| SICRL_USB0)
c005b939	320
6d0f6bcf JCPV	321	#define CONFIG_SYS_HID0_INIT 0x000000000
6d0f6bcf JCPV	322	#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
c005b939	323
6d0f6bcf	324	#define CONFIG_SYS_HID2 HID2_HBE
5ed546fd	325	#define CONFIG_HIGH_BATS 1
c005b939 AS	326
c005b939 AS	327	/* DDR */
6d0f6bcf JCPV	328	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
6d0f6bcf JCPV	329	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c005b939 AS	330
c005b939 AS	331	/* PCI */
6d0f6bcf JCPV	332	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	333	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	334	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT \|\
c005b939	335	BATL_GUARDEDSTORAGE)
6d0f6bcf	336	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c005b939 AS	337
c005b939 AS	338	/* no PCI2 */
6d0f6bcf JCPV	339	#define CONFIG_SYS_IBAT3L 0
	340	#define CONFIG_SYS_IBAT3U 0
	341	#define CONFIG_SYS_IBAT4L 0
	342	#define CONFIG_SYS_IBAT4U 0
c005b939 AS	343
c005b939 AS	344	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
6d0f6bcf	345	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \| BATL_PP_10 \| BATL_CACHEINHIBIT \| \
c005b939	346	BATL_GUARDEDSTORAGE)
6d0f6bcf	347	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \| BATU_BL_256M \| BATU_VS \| BATU_VP)
c005b939 AS	348
c005b939 AS	349	/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
c1230980 SW	350	#define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_10 \| BATL_MEMCOHERENCE \| \
c1230980 SW	351	BATL_GUARDEDSTORAGE)
6d0f6bcf JCPV	352	#define CONFIG_SYS_IBAT6U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	353	#define CONFIG_SYS_IBAT7L 0
	354	#define CONFIG_SYS_IBAT7U 0
	355
	356	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	357	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	358	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	359	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	360	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	361	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	362	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	363	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	364	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	365	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	366	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	367	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	368	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	369	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	370	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	371	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
c005b939 AS	372
	373	/*
	374	* Internal Definitions
	375	*
	376	* Boot Flags
	377	*/
	378	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	379	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	380
	381
	382	/*
	383	* Environment Configuration
	384	*/
	385	#define CONFIG_ENV_OVERWRITE
	386
	387	#define CONFIG_NETDEV eth0
	388
	389	/* Default path and filenames */
	390	#define CONFIG_BOOTDELAY 5
	391	#define CONFIG_AUTOBOOT_KEYED
	392	#define CONFIG_AUTOBOOT_STOP_STR "s"
	393	#define CONFIG_ZERO_BOOTDELAY_CHECK
	394	#define CONFIG_RESET_TO_RETRY 1000
	395
1a9eeb78 AS	396	#define MV_CI mvBL-M7
1a9eeb78 AS	397	#define MV_VCI mvBL-M7
28887d83 AS	398	#define MV_FPGA_DATA 0xfff40000
28887d83 AS	399	#define MV_FPGA_SIZE 0
1a9eeb78 AS	400	#define MV_KERNEL_ADDR 0xff810000
1a9eeb78 AS	401	#define MV_INITRD_ADDR 0xffb00000
3202d331 PT	402	#define MV_SCRIPT_ADDR 0xff804000
3202d331 PT	403	#define MV_SCRIPT_ADDR2 0xff806000
1a9eeb78 AS	404	#define MV_DTB_ADDR 0xff808000
1a9eeb78 AS	405	#define MV_INITRD_LENGTH 0x00400000
c005b939 AS	406
	407	#define CONFIG_SHOW_BOOT_PROGRESS 1
	408
1a9eeb78 AS	409	#define MV_KERNEL_ADDR_RAM 0x00100000
	410	#define MV_DTB_ADDR_RAM 0x00600000
	411	#define MV_INITRD_ADDR_RAM 0x01000000
c005b939	412
3202d331 PT	413	#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
	414	then source ${script_addr}; \
	415	else source ${script_addr2}; \
c005b939 AS	416	fi;"
	417	#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
	418
	419	#define CONFIG_EXTRA_ENV_SETTINGS \
	420	"console_nr=0\0" \
1a9eeb78	421	"baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
c005b939 AS	422	"stdin=serial\0" \
	423	"stdout=serial\0" \
	424	"stderr=serial\0" \
	425	"fpga=0\0" \
1a9eeb78 AS	426	"fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
1a9eeb78 AS	427	"fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
3202d331 PT	428	"script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
3202d331 PT	429	"script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
1a9eeb78 AS	430	"mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
	431	"mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
	432	"mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
	433	"mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
	434	"mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
	435	"mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
	436	"mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
	437	"dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
5ed546fd	438	"mv_version=" U_BOOT_VERSION "\0" \
1a9eeb78 AS	439	"dhcp_client_id=" MK_STR(MV_CI) "\0" \
1a9eeb78 AS	440	"dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
c005b939 AS	441	"netretry=no\0" \
	442	"use_static_ipaddr=no\0" \
	443	"static_ipaddr=192.168.90.10\0" \
	444	"static_netmask=255.255.255.0\0" \
	445	"static_gateway=0.0.0.0\0" \
28887d83	446	"initrd_name=uInitrd.mvBL-M7-rfs\0" \
c005b939 AS	447	"zcip=no\0" \
	448	"netboot=yes\0" \
	449	"mvtest=Ff\0" \
	450	"tried_bootfromflash=no\0" \
	451	"tried_bootfromnet=no\0" \
	452	"bootfile=mvblm72625.boot\0" \
	453	"use_dhcp=yes\0" \
	454	"gev_start=yes\0" \
	455	"mvbcdma_debug=0\0" \
	456	"mvbcia_debug=0\0" \
	457	"propdev_debug=0\0" \
	458	"gevss_debug=0\0" \
	459	"watchdog=0\0" \
	460	"usb_dr_mode=host\0" \
1a9eeb78	461	"sensor_cnt=2\0" \
c005b939 AS	462	""
	463
	464	#define CONFIG_FPGA_COUNT 1
6d0f6bcf	465	#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
c005b939 AS	466	#define CONFIG_FPGA_ALTERA
	467	#define CONFIG_FPGA_CYCLON2
	468
	469	#endif