[people/ms/u-boot.git] / include / configs / MVBLM7.h

/*
 * Copyright (C) Matrix Vision GmbH 2008
 *
 * Matrix Vision mvBlueLYNX-M7 configuration file
 * based on Freescale's MPC8349ITX.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#ifndef __CONFIG_H
#define __CONFIG_H

#include <version.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_E300	1
#define CONFIG_MPC83xx	1
#define CONFIG_MPC834x	1
#define CONFIG_MPC8343	1

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#define CONFIG_SYS_IMMR		0xE0000000

#define CONFIG_PCI
#define CONFIG_PCI_SKIP_HOST_BRIDGE
#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET
#define CONFIG_MPC8XXX_SPI
#define CONFIG_HARD_SPI
#define MVBLM7_MMC_CS   0x04000000
#define CONFIG_MISC_INIT_R

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100

#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * DDR Setup
 */
#undef	CONFIG_SPD_EEPROM

#define CONFIG_SYS_DDR_BASE		0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_83XX_DDR_USES_CS0	1
#define CONFIG_SYS_MEMTEST_START	(60<<20)
#define CONFIG_SYS_MEMTEST_END		(70<<20)
#define CONFIG_VERY_BIG_RAM

#define CONFIG_SYS_DDRCDR		(DDRCDR_PZ_HIZ \
					| DDRCDR_NZ_HIZ \
					| DDRCDR_Q_DRN)
					/* 0x22000001 */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05

#define CONFIG_SYS_DDR_SIZE		512

#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202

#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f

#define CONFIG_SYS_DDR_TIMING_0		0x00260802
#define CONFIG_SYS_DDR_TIMING_1		0x3837c322
#define CONFIG_SYS_DDR_TIMING_2		0x0f9848c6
#define CONFIG_SYS_DDR_TIMING_3		0x00000000

#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080008
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#define CONFIG_SYS_DDR_INTERVAL		0x02000100

#define CONFIG_SYS_DDR_MODE		0x04040242
#define CONFIG_SYS_DDR_MODE2		0x00800000

/* Flash */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFF800000
#define CONFIG_SYS_FLASH_SIZE		8
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16 \
				| BR_MS_GPCM \
				| BR_V)
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)

/*
 * U-Boot memory configuration
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#undef	CONFIG_SYS_RAMBOOT

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)

/*
 * Local Bus LCRR and LBCR regs
 *  LCRR:  DLL bypass, Clock divider is 4
 * External Local Bus rate is
 *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
#define CONFIG_SYS_LBC_LBCR	0x00000000

/* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_LSRT	0x32000000
/* LB refresh timer prescal, 266MHz/32*/
#define CONFIG_SYS_LBC_MRTPR	0x20000000

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_CONSOLE		ttyS0
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1
#define MV_DTB_NAME	"mvblm7.dtb"

/*
 * PCI
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCI1_MMIO_BASE	\
			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000
#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000

#define CONFIG_NET_RETRY_COUNT	3

#define CONFIG_PCI_66M
#define CONFIG_83XX_CLKIN	66666667
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW

/* TSEC */
#define CONFIG_GMII
#define CONFIG_SYS_VSC8601_SKEWFIX
#define	CONFIG_SYS_VSC8601_SKEW_TX	3
#define	CONFIG_SYS_VSC8601_SKEW_RX	3

#define CONFIG_TSEC1
#define CONFIG_TSEC2

#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_FEC1_PHY_NORXERR
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define TSEC1_PHY_ADDR		0x10
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)

#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define CONFIG_FEC2_PHY_NORXERR
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
#define TSEC2_PHY_ADDR		0x11
#define TSEC2_PHYIDX		0
#define TSEC2_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)

#define CONFIG_ETHPRIME		"TSEC0"

#define CONFIG_BOOTP_VENDOREX
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME

/* USB */
#define CONFIG_SYS_USB_HOST
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

/*
 * Environment
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0xFF800000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCI
#define CONFIG_CMD_I2C
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_USB
#define CONFIG_DOS_PARTITION

#undef CONFIG_WATCHDOG

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
#define CONFIG_SYS_HUSH_PARSER

/* default load address */
#define CONFIG_SYS_LOAD_ADDR	0x2000000
/* default location for tftp and bootm */
#define CONFIG_LOADADDR	0x200000

#define CONFIG_SYS_PROMPT	"mvBL-M7> "
#define CONFIG_SYS_CBSIZE	256

#define CONFIG_SYS_PBSIZE	\
			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ		1000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
				/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)

#define CONFIG_SYS_HRCW_LOW	0x0
#define CONFIG_SYS_HRCW_HIGH	0x0

/*
 * System performance
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */

/* clocking */
#define CONFIG_SYS_SCCR_ENCCM		0
#define CONFIG_SYS_SCCR_USBMPHCM	0
#define	CONFIG_SYS_SCCR_USBDRCM	2
#define CONFIG_SYS_SCCR_TSEC1CM	1
#define CONFIG_SYS_SCCR_TSEC2CM	1

#define CONFIG_SYS_SICRH	0x1fef0003
#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
				 HID0_ENABLE_INSTRUCTION_CACHE)

#define CONFIG_SYS_HID2	HID2_HBE
#define CONFIG_HIGH_BATS	1

/* DDR  */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* PCI  */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* no PCI2 */
#define CONFIG_SYS_IBAT3L	0
#define CONFIG_SYS_IBAT3U	0
#define CONFIG_SYS_IBAT4L	0
#define CONFIG_SYS_IBAT4U	0

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)

/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
#define CONFIG_SYS_IBAT6L	(0xF0000000 \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_IBAT7L	0
#define CONFIG_SYS_IBAT7U	0

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		eth0

/* Default path and filenames */
#define CONFIG_BOOTDELAY		5
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR	"s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY		1000

#define MV_CI			"mvBL-M7"
#define MV_VCI			"mvBL-M7"
#define MV_FPGA_DATA		0xfff40000
#define MV_FPGA_SIZE		0
#define MV_KERNEL_ADDR		0xff810000
#define MV_INITRD_ADDR		0xffb00000
#define MV_SCRIPT_ADDR		0xff804000
#define MV_SCRIPT_ADDR2		0xff806000
#define MV_DTB_ADDR		0xff808000
#define MV_INITRD_LENGTH	0x00400000

#define CONFIG_SHOW_BOOT_PROGRESS 1

#define MV_KERNEL_ADDR_RAM	0x00100000
#define MV_DTB_ADDR_RAM		0x00600000
#define MV_INITRD_ADDR_RAM	0x01000000

#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; "		\
					"then source ${script_addr}; "	\
					"else source ${script_addr2}; "	\
				"fi;"
#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"console_nr=0\0"					\
	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"		\
	"stdin=serial\0"					\
	"stdout=serial\0"					\
	"stderr=serial\0"					\
	"fpga=0\0"						\
	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
	"mv_version=" U_BOOT_VERSION "\0"			\
	"dhcp_client_id=" MV_CI "\0"				\
	"dhcp_vendor-class-identifier=" MV_VCI "\0"		\
	"netretry=no\0"						\
	"use_static_ipaddr=no\0"				\
	"static_ipaddr=192.168.90.10\0"				\
	"static_netmask=255.255.255.0\0"			\
	"static_gateway=0.0.0.0\0"				\
	"initrd_name=uInitrd.mvBL-M7-rfs\0"			\
	"zcip=no\0"						\
	"netboot=yes\0"						\
	"mvtest=Ff\0"						\
	"tried_bootfromflash=no\0"				\
	"tried_bootfromnet=no\0"				\
	"bootfile=mvblm72625.boot\0"				\
	"use_dhcp=yes\0"					\
	"gev_start=yes\0"					\
	"mvbcdma_debug=0\0"					\
	"mvbcia_debug=0\0"					\
	"propdev_debug=0\0"					\
	"gevss_debug=0\0"					\
	"watchdog=0\0"						\
	"usb_dr_mode=host\0"					\
	"sensor_cnt=2\0"					\
	""

#define CONFIG_FPGA_COUNT	1
#define CONFIG_FPGA		CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2

#endif
Commit	Line	Data
c005b939 AS	1	/*
	2	* Copyright (C) Matrix Vision GmbH 2008
	3	*
	4	* Matrix Vision mvBlueLYNX-M7 configuration file
	5	* based on Freescale's MPC8349ITX.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
5ed546fd	30	#include <version.h>
c005b939 AS	31
	32	/*
	33	* High Level Configuration Options
	34	*/
	35	#define CONFIG_E300 1
0f898604	36	#define CONFIG_MPC83xx 1
2c7920af	37	#define CONFIG_MPC834x 1
c005b939 AS	38	#define CONFIG_MPC8343 1
c005b939 AS	39
2ae18241 WD	40	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	41
6d0f6bcf	42	#define CONFIG_SYS_IMMR 0xE0000000
c005b939 AS	43
c005b939 AS	44	#define CONFIG_PCI
c005b939 AS	45	#define CONFIG_PCI_SKIP_HOST_BRIDGE
	46	#define CONFIG_HARD_I2C
	47	#define CONFIG_TSEC_ENET
	48	#define CONFIG_MPC8XXX_SPI
	49	#define CONFIG_HARD_SPI
	50	#define MVBLM7_MMC_CS 0x04000000
28887d83	51	#define CONFIG_MISC_INIT_R
c005b939 AS	52
c005b939 AS	53	/* I2C */
c005b939 AS	54	#define CONFIG_FSL_I2C
c005b939 AS	55	#define CONFIG_I2C_MULTI_BUS
6d0f6bcf JCPV	56	#define CONFIG_SYS_I2C_OFFSET 0x3000
6d0f6bcf JCPV	57	#define CONFIG_SYS_I2C2_OFFSET 0x3100
c005b939	58
6d0f6bcf JCPV	59	#define CONFIG_SYS_I2C_SPEED 100000
6d0f6bcf JCPV	60	#define CONFIG_SYS_I2C_SLAVE 0x7F
c005b939 AS	61
	62	/*
	63	* DDR Setup
	64	*/
28887d83 AS	65	#undef CONFIG_SPD_EEPROM
28887d83 AS	66
6d0f6bcf JCPV	67	#define CONFIG_SYS_DDR_BASE 0x00000000
	68	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	69	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	70	#define CONFIG_SYS_83XX_DDR_USES_CS0 1
	71	#define CONFIG_SYS_MEMTEST_START (60<<20)
	72	#define CONFIG_SYS_MEMTEST_END (70<<20)
28887d83	73	#define CONFIG_VERY_BIG_RAM
6d0f6bcf	74
2fef4020 JH	75	#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
	76	\| DDRCDR_NZ_HIZ \
	77	\| DDRCDR_Q_DRN)
	78	/* 0x22000001 */
28887d83	79	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
c005b939	80
28887d83	81	#define CONFIG_SYS_DDR_SIZE 512
c005b939	82
28887d83	83	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
c005b939	84
28887d83	85	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
c005b939	86
28887d83 AS	87	#define CONFIG_SYS_DDR_TIMING_0 0x00260802
	88	#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
	89	#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
	90	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
c005b939	91
28887d83	92	#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
6d0f6bcf	93	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
28887d83	94	#define CONFIG_SYS_DDR_INTERVAL 0x02000100
c005b939	95
28887d83 AS	96	#define CONFIG_SYS_DDR_MODE 0x04040242
28887d83 AS	97	#define CONFIG_SYS_DDR_MODE2 0x00800000
c005b939 AS	98
c005b939 AS	99	/* Flash */
6d0f6bcf	100	#define CONFIG_SYS_FLASH_CFI
00b1883a	101	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	102	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	103
	104	#define CONFIG_SYS_FLASH_BASE 0xFF800000
	105	#define CONFIG_SYS_FLASH_SIZE 8
6d0f6bcf JCPV	106	#define CONFIG_SYS_FLASH_EMPTY_INFO
	107	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
	108	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
	109	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	110	#define CONFIG_SYS_MAX_FLASH_SECT 256
	111
7d6a0982 JH	112	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
	113	\| BR_PS_16 \
	114	\| BR_MS_GPCM \
	115	\| BR_V)
	116	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
b2773a5e JH	117	\| OR_UPM_XAM \
	118	\| OR_GPCM_CSNT \
	119	\| OR_GPCM_ACS_DIV2 \
	120	\| OR_GPCM_XACS \
	121	\| OR_GPCM_SCY_15 \
7d6a0982 JH	122	\| OR_GPCM_TRLX_SET \
7d6a0982 JH	123	\| OR_GPCM_EHTR_SET \
b2773a5e	124	\| OR_GPCM_EAD)
6d0f6bcf	125	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	126	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
c005b939 AS	127
	128	/*
	129	* U-Boot memory configuration
	130	*/
14d0a02a	131	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	132	#undef CONFIG_SYS_RAMBOOT
c005b939	133
6d0f6bcf	134	#define CONFIG_SYS_INIT_RAM_LOCK
b2773a5e JH	135	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
b2773a5e JH	136	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
c005b939	137
b2773a5e JH	138	#define CONFIG_SYS_GBL_DATA_OFFSET \
b2773a5e JH	139	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	140	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c005b939	141
6d0f6bcf JCPV	142	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
	143	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	144	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
c005b939 AS	145
	146	/*
	147	* Local Bus LCRR and LBCR regs
	148	* LCRR: DLL bypass, Clock divider is 4
	149	* External Local Bus rate is
	150	* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
	151	*/
c7190f02 KP	152	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	153	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
6d0f6bcf	154	#define CONFIG_SYS_LBC_LBCR 0x00000000
c005b939 AS	155
c005b939 AS	156	/* LB sdram refresh timer, about 6us */
6d0f6bcf	157	#define CONFIG_SYS_LBC_LSRT 0x32000000
c005b939	158	/* LB refresh timer prescal, 266MHz/32*/
6d0f6bcf	159	#define CONFIG_SYS_LBC_MRTPR 0x20000000
c005b939 AS	160
	161	/*
	162	* Serial Port
	163	*/
	164	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	165	#define CONFIG_SYS_NS16550
	166	#define CONFIG_SYS_NS16550_SERIAL
	167	#define CONFIG_SYS_NS16550_REG_SIZE 1
	168	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
c005b939	169
6d0f6bcf	170	#define CONFIG_SYS_BAUDRATE_TABLE \
b2773a5e	171	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
c005b939 AS	172
	173	#define CONFIG_CONSOLE ttyS0
	174	#define CONFIG_BAUDRATE 115200
	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
6d0f6bcf JCPV	177	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
c005b939 AS	178
	179	/* pass open firmware flat tree */
	180	#define CONFIG_OF_LIBFDT 1
	181	#define CONFIG_OF_BOARD_SETUP 1
	182	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	183	#define MV_DTB_NAME "mvblm7.dtb"
	184
	185	/*
	186	* PCI
	187	*/
6d0f6bcf JCPV	188	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	189	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	190	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
b2773a5e JH	191	#define CONFIG_SYS_PCI1_MMIO_BASE \
b2773a5e JH	192	(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
6d0f6bcf JCPV	193	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	194	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
	195	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	196	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	197	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
c005b939	198
c005b939 AS	199	#define CONFIG_NET_RETRY_COUNT 3
c005b939 AS	200
2ae18241	201	#define CONFIG_PCI_66M
c005b939 AS	202	#define CONFIG_83XX_CLKIN 66666667
	203	#define CONFIG_PCI_PNP
	204	#define CONFIG_PCI_SCAN_SHOW
	205
	206	/* TSEC */
	207	#define CONFIG_GMII
6d0f6bcf JCPV	208	#define CONFIG_SYS_VSC8601_SKEWFIX
	209	#define CONFIG_SYS_VSC8601_SKEW_TX 3
	210	#define CONFIG_SYS_VSC8601_SKEW_RX 3
c005b939 AS	211
	212	#define CONFIG_TSEC1
	213	#define CONFIG_TSEC2
	214
	215	#define CONFIG_HAS_ETH0
	216	#define CONFIG_TSEC1_NAME "TSEC0"
	217	#define CONFIG_FEC1_PHY_NORXERR
6d0f6bcf	218	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
b2773a5e	219	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
c005b939 AS	220	#define TSEC1_PHY_ADDR 0x10
	221	#define TSEC1_PHYIDX 0
	222	#define TSEC1_FLAGS (TSEC_GIGABIT\|TSEC_REDUCED)
	223
	224	#define CONFIG_HAS_ETH1
b2773a5e	225	#define CONFIG_TSEC2_NAME "TSEC1"
c005b939	226	#define CONFIG_FEC2_PHY_NORXERR
6d0f6bcf	227	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
b2773a5e	228	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
c005b939 AS	229	#define TSEC2_PHY_ADDR 0x11
	230	#define TSEC2_PHYIDX 0
	231	#define TSEC2_FLAGS (TSEC_GIGABIT\|TSEC_REDUCED)
	232
	233	#define CONFIG_ETHPRIME "TSEC0"
	234
	235	#define CONFIG_BOOTP_VENDOREX
	236	#define CONFIG_BOOTP_SUBNETMASK
	237	#define CONFIG_BOOTP_GATEWAY
	238	#define CONFIG_BOOTP_DNS
	239	#define CONFIG_BOOTP_DNS2
	240	#define CONFIG_BOOTP_HOSTNAME
	241	#define CONFIG_BOOTP_BOOTFILESIZE
	242	#define CONFIG_BOOTP_BOOTPATH
	243	#define CONFIG_BOOTP_NTPSERVER
	244	#define CONFIG_BOOTP_RANDOM_DELAY
	245	#define CONFIG_BOOTP_SEND_HOSTNAME
	246
	247	/* USB */
fd194f82 AS	248	#define CONFIG_SYS_USB_HOST
	249	#define CONFIG_USB_EHCI
	250	#define CONFIG_USB_EHCI_FSL
c005b939	251	#define CONFIG_HAS_FSL_DR_USB
fd194f82	252	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
c005b939 AS	253
	254	/*
	255	* Environment
	256	*/
6d0f6bcf	257	#undef CONFIG_SYS_FLASH_PROTECTION
c005b939 AS	258	#define CONFIG_ENV_OVERWRITE
c005b939 AS	259
5a1aceb0	260	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	261	#define CONFIG_ENV_ADDR 0xFF800000
	262	#define CONFIG_ENV_SIZE 0x2000
	263	#define CONFIG_ENV_SECT_SIZE 0x2000
	264	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
b2773a5e	265	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
c005b939	266
e093a247	267	#define CONFIG_LOADS_ECHO
6d0f6bcf	268	#define CONFIG_SYS_LOADS_BAUD_CHANGE
c005b939 AS	269
	270	/*
	271	* Command line configuration.
	272	*/
	273	#include <config_cmd_default.h>
	274
	275	#define CONFIG_CMD_CACHE
	276	#define CONFIG_CMD_IRQ
	277	#define CONFIG_CMD_NET
	278	#define CONFIG_CMD_MII
	279	#define CONFIG_CMD_PING
	280	#define CONFIG_CMD_DHCP
	281	#define CONFIG_CMD_SDRAM
	282	#define CONFIG_CMD_PCI
	283	#define CONFIG_CMD_I2C
	284	#define CONFIG_CMD_FPGA
fd194f82 AS	285	#define CONFIG_CMD_USB
fd194f82 AS	286	#define CONFIG_DOS_PARTITION
c005b939 AS	287
	288	#undef CONFIG_WATCHDOG
	289
	290	/*
	291	* Miscellaneous configurable options
	292	*/
6d0f6bcf	293	#define CONFIG_SYS_LONGHELP
c005b939	294	#define CONFIG_CMDLINE_EDITING
b2773a5e	295	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	296	#define CONFIG_SYS_HUSH_PARSER
c005b939 AS	297
c005b939 AS	298	/* default load address */
6d0f6bcf	299	#define CONFIG_SYS_LOAD_ADDR 0x2000000
c005b939 AS	300	/* default location for tftp and bootm */
	301	#define CONFIG_LOADADDR 0x200000
	302
6d0f6bcf JCPV	303	#define CONFIG_SYS_PROMPT "mvBL-M7> "
6d0f6bcf JCPV	304	#define CONFIG_SYS_CBSIZE 256
c005b939	305
b2773a5e JH	306	#define CONFIG_SYS_PBSIZE \
b2773a5e JH	307	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
6d0f6bcf JCPV	308	#define CONFIG_SYS_MAXARGS 16
	309	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	310	#define CONFIG_SYS_HZ 1000
c005b939 AS	311
	312	/*
	313	* For booting Linux, the board info and command line data
9f530d59	314	* have to be in the first 256 MB of memory, since this is
c005b939 AS	315	* the maximum mapped by the Linux kernel during initialization.
c005b939 AS	316	*/
b2773a5e JH	317	/* Initial Memory map for Linux*/
b2773a5e JH	318	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
c005b939	319
6d0f6bcf JCPV	320	#define CONFIG_SYS_HRCW_LOW 0x0
6d0f6bcf JCPV	321	#define CONFIG_SYS_HRCW_HIGH 0x0
c005b939 AS	322
	323	/*
	324	* System performance
	325	*/
6d0f6bcf	326	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
b2773a5e	327	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
6d0f6bcf JCPV	328	#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
6d0f6bcf JCPV	329	#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
c005b939 AS	330
c005b939 AS	331	/* clocking */
6d0f6bcf JCPV	332	#define CONFIG_SYS_SCCR_ENCCM 0
	333	#define CONFIG_SYS_SCCR_USBMPHCM 0
	334	#define CONFIG_SYS_SCCR_USBDRCM 2
	335	#define CONFIG_SYS_SCCR_TSEC1CM 1
	336	#define CONFIG_SYS_SCCR_TSEC2CM 1
c005b939	337
116ef54d	338	#define CONFIG_SYS_SICRH 0x1fef0003
6d0f6bcf	339	#define CONFIG_SYS_SICRL (SICRL_LDP_A \| SICRL_USB1 \| SICRL_USB0)
c005b939	340
6d0f6bcf	341	#define CONFIG_SYS_HID0_INIT 0x000000000
1a2e203b KP	342	#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT \| \
1a2e203b KP	343	HID0_ENABLE_INSTRUCTION_CACHE)
c005b939	344
6d0f6bcf	345	#define CONFIG_SYS_HID2 HID2_HBE
5ed546fd	346	#define CONFIG_HIGH_BATS 1
c005b939 AS	347
c005b939 AS	348	/* DDR */
b2773a5e	349	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	350	\| BATL_PP_RW \
b2773a5e JH	351	\| BATL_MEMCOHERENCE)
	352	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	353	\| BATU_BL_256M \
	354	\| BATU_VS \
	355	\| BATU_VP)
c005b939 AS	356
c005b939 AS	357	/* PCI */
b2773a5e	358	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
72cd4087	359	\| BATL_PP_RW \
b2773a5e JH	360	\| BATL_MEMCOHERENCE)
	361	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
	362	\| BATU_BL_256M \
	363	\| BATU_VS \
	364	\| BATU_VP)
	365	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
72cd4087	366	\| BATL_PP_RW \
b2773a5e JH	367	\| BATL_CACHEINHIBIT \
	368	\| BATL_GUARDEDSTORAGE)
	369	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
	370	\| BATU_BL_256M \
	371	\| BATU_VS \
	372	\| BATU_VP)
c005b939 AS	373
c005b939 AS	374	/* no PCI2 */
6d0f6bcf JCPV	375	#define CONFIG_SYS_IBAT3L 0
	376	#define CONFIG_SYS_IBAT3U 0
	377	#define CONFIG_SYS_IBAT4L 0
	378	#define CONFIG_SYS_IBAT4U 0
c005b939 AS	379
c005b939 AS	380	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
b2773a5e	381	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
72cd4087	382	\| BATL_PP_RW \
b2773a5e JH	383	\| BATL_CACHEINHIBIT \
	384	\| BATL_GUARDEDSTORAGE)
	385	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
	386	\| BATU_BL_256M \
	387	\| BATU_VS \
	388	\| BATU_VP)
c005b939 AS	389
c005b939 AS	390	/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
b2773a5e	391	#define CONFIG_SYS_IBAT6L (0xF0000000 \
72cd4087	392	\| BATL_PP_RW \
b2773a5e	393	\| BATL_MEMCOHERENCE \
72cd4087	394	\| BATL_GUARDEDSTORAGE)
b2773a5e JH	395	#define CONFIG_SYS_IBAT6U (0xF0000000 \
	396	\| BATU_BL_256M \
	397	\| BATU_VS \
	398	\| BATU_VP)
6d0f6bcf JCPV	399	#define CONFIG_SYS_IBAT7L 0
	400	#define CONFIG_SYS_IBAT7U 0
	401
	402	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	403	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	404	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	405	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	406	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	407	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	408	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	409	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	410	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	411	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	412	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	413	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	414	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	415	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	416	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	417	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
c005b939	418
c005b939 AS	419	/*
	420	* Environment Configuration
	421	*/
	422	#define CONFIG_ENV_OVERWRITE
	423
	424	#define CONFIG_NETDEV eth0
	425
	426	/* Default path and filenames */
	427	#define CONFIG_BOOTDELAY 5
	428	#define CONFIG_AUTOBOOT_KEYED
	429	#define CONFIG_AUTOBOOT_STOP_STR "s"
	430	#define CONFIG_ZERO_BOOTDELAY_CHECK
	431	#define CONFIG_RESET_TO_RETRY 1000
	432
b2773a5e JH	433	#define MV_CI "mvBL-M7"
b2773a5e JH	434	#define MV_VCI "mvBL-M7"
28887d83 AS	435	#define MV_FPGA_DATA 0xfff40000
28887d83 AS	436	#define MV_FPGA_SIZE 0
1a9eeb78 AS	437	#define MV_KERNEL_ADDR 0xff810000
1a9eeb78 AS	438	#define MV_INITRD_ADDR 0xffb00000
3202d331 PT	439	#define MV_SCRIPT_ADDR 0xff804000
3202d331 PT	440	#define MV_SCRIPT_ADDR2 0xff806000
1a9eeb78 AS	441	#define MV_DTB_ADDR 0xff808000
1a9eeb78 AS	442	#define MV_INITRD_LENGTH 0x00400000
c005b939 AS	443
	444	#define CONFIG_SHOW_BOOT_PROGRESS 1
	445
1a9eeb78 AS	446	#define MV_KERNEL_ADDR_RAM 0x00100000
	447	#define MV_DTB_ADDR_RAM 0x00600000
	448	#define MV_INITRD_ADDR_RAM 0x01000000
c005b939	449
b2773a5e JH	450	#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
	451	"then source ${script_addr}; " \
	452	"else source ${script_addr2}; " \
	453	"fi;"
c005b939 AS	454	#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
	455
	456	#define CONFIG_EXTRA_ENV_SETTINGS \
	457	"console_nr=0\0" \
5368c55d	458	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
c005b939 AS	459	"stdin=serial\0" \
	460	"stdout=serial\0" \
	461	"stderr=serial\0" \
	462	"fpga=0\0" \
5368c55d MV	463	"fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
	464	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
	465	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
	466	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
	467	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
	468	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
	469	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
	470	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
	471	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
	472	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
	473	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
	474	"dtb_name=" __stringify(MV_DTB_NAME) "\0" \
5ed546fd	475	"mv_version=" U_BOOT_VERSION "\0" \
b2773a5e JH	476	"dhcp_client_id=" MV_CI "\0" \
b2773a5e JH	477	"dhcp_vendor-class-identifier=" MV_VCI "\0" \
c005b939 AS	478	"netretry=no\0" \
	479	"use_static_ipaddr=no\0" \
	480	"static_ipaddr=192.168.90.10\0" \
	481	"static_netmask=255.255.255.0\0" \
	482	"static_gateway=0.0.0.0\0" \
28887d83	483	"initrd_name=uInitrd.mvBL-M7-rfs\0" \
c005b939 AS	484	"zcip=no\0" \
	485	"netboot=yes\0" \
	486	"mvtest=Ff\0" \
	487	"tried_bootfromflash=no\0" \
	488	"tried_bootfromnet=no\0" \
	489	"bootfile=mvblm72625.boot\0" \
	490	"use_dhcp=yes\0" \
	491	"gev_start=yes\0" \
	492	"mvbcdma_debug=0\0" \
	493	"mvbcia_debug=0\0" \
	494	"propdev_debug=0\0" \
	495	"gevss_debug=0\0" \
	496	"watchdog=0\0" \
	497	"usb_dr_mode=host\0" \
1a9eeb78	498	"sensor_cnt=2\0" \
c005b939 AS	499	""
	500
	501	#define CONFIG_FPGA_COUNT 1
6d0f6bcf	502	#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
c005b939 AS	503	#define CONFIG_FPGA_ALTERA
	504	#define CONFIG_FPGA_CYCLON2
	505
	506	#endif