[people/ms/u-boot.git] / include / configs / MVBLUE.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#ifndef __CONFIG_H
#define __CONFIG_H

#define MV_VERSION	"v0.2.0"

/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
#define ERR_NONE		0
#define ERR_ENV			1
#define ERR_BOOTM_BADMAGIC	2
#define ERR_BOOTM_BADCRC	3
#define ERR_BOOTM_GUNZIP	4
#define ERR_BOOTP_TIMEOUT	5
#define ERR_DHCP		6
#define ERR_TFTP		7
#define ERR_NOLAN		8
#define ERR_LANDRV		9

#define CONFIG_BOARD_TYPES	1
#define MVBLUE_BOARD_BOX	1
#define MVBLUE_BOARD_LYNX	2

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
#define CONFIG_SYS_LDSCRIPT	"board/mvblue/u-boot.lds"

#if 0
#define ERR_LED(code)	do { if (code) \
		*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
	else \
		*(volatile char *)(0xff000003) = ( 1 ); \
} while(0)
#else
#define ERR_LED(code)
#endif

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_MVBLUE		1

#define CONFIG_CLOCKS_IN_MHZ	1

#define CONFIG_BOARD_TYPES	1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOT_RETRY_TIME	-1

#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"autoboot in %d seconds (stop with 's')...\n", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR	"s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY		60


/*
 * Command line configuration.
 */

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_RUN


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* Max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address			*/

#define CONFIG_BOOTCOMMAND	"run nfsboot"
#define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"

#define CONFIG_NFSBOOTCOMMAND	"bootp; run nfsargs addcons;bootm"

#define CONFIG_EXTRA_ENV_SETTINGS			\
	"console_nr=0\0"				\
    "dhcp_client_id=mvBOX-XP\0"				\
    "dhcp_vendor-class-identifier=mvBOX\0"		\
    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
			"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
    "mv_version=" MV_VERSION "\0"	\
	"bootretry=30\0"

#define CONFIG_OVERWRITE_ETHADDR_ONCE

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */

#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW

#define CONFIG_NET_RETRY_COUNT		5

#define CONFIG_TULIP
#define CONFIG_TULIP_FIX_DAVICOM	1
#define CONFIG_ETHADDR			b6:b4:45:eb:fb:c0

#define CONFIG_HW_WATCHDOG

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE	    0x00000000

#define CONFIG_SYS_FLASH_BASE      0xFFF00000
#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
#define CONFIG_SYS_EUMB_ADDR	    0xFC000000

#define CONFIG_SYS_MONITOR_LEN     0x00100000
#define CONFIG_SYS_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */

#define CONFIG_SYS_MEMTEST_START   0x00100000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/

/* Maximum amount of RAM.  */
#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */


#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_ISA_IO      0xFE000000

/*
 * serial configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE    1

#define CONFIG_SYS_NS16550_CLK     get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1    (CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM2    (CONFIG_SYS_EUMB_ADDR + 0x4600)

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CONFIG_SYS_HZ			 10000

/* Bit-field values for MCCR1.  */
#define CONFIG_SYS_ROMNAL      7
#define CONFIG_SYS_ROMFAL      11

/* Bit-field values for MCCR2.  */
#define CONFIG_SYS_TSWAIT      0x5
#define CONFIG_SYS_REFINT      430

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
#define CONFIG_SYS_BSTOPRE     121

/* Bit-field values for MCCR3.  */
#define CONFIG_SYS_REFREC      8

/* Bit-field values for MCCR4.  */
#define CONFIG_SYS_PRETOACT    3
#define CONFIG_SYS_ACTTOPRE    5
#define CONFIG_SYS_ACTORW      3
#define CONFIG_SYS_SDMODE_CAS_LAT  3
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
#define CONFIG_SYS_EXTROM      1
#define CONFIG_SYS_REGDIMM     0
#define CONFIG_SYS_DBUS_SIZE2  1
#define CONFIG_SYS_SDMODE_WRAP 0

#define CONFIG_SYS_PGMAX       0x32
#define CONFIG_SYS_SDRAM_DSCD  0x20

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START     0x3ff00000
#define CONFIG_SYS_BANK1_END       0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START     0x3ff00000
#define CONFIG_SYS_BANK2_END       0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START     0x3ff00000
#define CONFIG_SYS_BANK3_END       0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START     0x3ff00000
#define CONFIG_SYS_BANK4_END       0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START     0x3ff00000
#define CONFIG_SYS_BANK5_END       0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START     0x3ff00000
#define CONFIG_SYS_BANK6_END       0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START     0x3ff00000
#define CONFIG_SYS_BANK7_END       0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR	    0xff

#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000


#define CONFIG_ENV_IS_IN_FLASH

#define CONFIG_ENV_OFFSET		0x00010000
#define CONFIG_ENV_SIZE		0x00010000
#define CONFIG_ENV_SECT_SIZE	0x00010000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
b4676a25 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#define MV_VERSION "v0.2.0"
	29
	30	/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
53677ef1 WD	31	#define ERR_NONE 0
	32	#define ERR_ENV 1
	33	#define ERR_BOOTM_BADMAGIC 2
	34	#define ERR_BOOTM_BADCRC 3
	35	#define ERR_BOOTM_GUNZIP 4
b4676a25	36	#define ERR_BOOTP_TIMEOUT 5
53677ef1 WD	37	#define ERR_DHCP 6
	38	#define ERR_TFTP 7
	39	#define ERR_NOLAN 8
	40	#define ERR_LANDRV 9
b4676a25 WD	41
	42	#define CONFIG_BOARD_TYPES 1
	43	#define MVBLUE_BOARD_BOX 1
	44	#define MVBLUE_BOARD_LYNX 2
	45
2ae18241	46	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
de550d6b	47	#define CONFIG_SYS_LDSCRIPT "board/mvblue/u-boot.lds"
2ae18241	48
b4676a25 WD	49	#if 0
b4676a25 WD	50	#define ERR_LED(code) do { if (code) \
53677ef1 WD	51	(volatile char )(0xff000003) = ( 3 \| (code<<4) ) & 0xf3; \
	52	else \
	53	(volatile char )(0xff000003) = ( 1 ); \
	54	} while(0)
b4676a25 WD	55	#else
	56	#define ERR_LED(code)
	57	#endif
	58
b4676a25 WD	59	#define CONFIG_MPC824X 1
	60	#define CONFIG_MPC8245 1
	61	#define CONFIG_MVBLUE 1
	62
	63	#define CONFIG_CLOCKS_IN_MHZ 1
	64
f2302d44	65	#define CONFIG_BOARD_TYPES 1
b4676a25 WD	66
	67	#define CONFIG_CONS_INDEX 1
	68	#define CONFIG_BAUDRATE 115200
b4676a25	69
f2302d44	70	#define CONFIG_BOOTDELAY 3
b4676a25 WD	71	#define CONFIG_BOOT_RETRY_TIME -1
	72
	73	#define CONFIG_AUTOBOOT_KEYED
f2302d44 SR	74	#define CONFIG_AUTOBOOT_PROMPT \
f2302d44 SR	75	"autoboot in %d seconds (stop with 's')...\n", bootdelay
d4ca31c4	76	#define CONFIG_AUTOBOOT_STOP_STR "s"
b4676a25 WD	77	#define CONFIG_ZERO_BOOTDELAY_CHECK
	78	#define CONFIG_RESET_TO_RETRY 60
	79
b4676a25	80
8353e139 JL	81	/*
	82	* Command line configuration.
	83	*/
b4676a25	84
8353e139 JL	85	#define CONFIG_CMD_ASKENV
	86	#define CONFIG_CMD_BOOTD
	87	#define CONFIG_CMD_CACHE
	88	#define CONFIG_CMD_DHCP
	89	#define CONFIG_CMD_ECHO
bdab39d3	90	#define CONFIG_CMD_SAVEENV
8353e139 JL	91	#define CONFIG_CMD_FLASH
8353e139 JL	92	#define CONFIG_CMD_IMI
8353e139 JL	93	#define CONFIG_CMD_NET
	94	#define CONFIG_CMD_PCI
	95	#define CONFIG_CMD_RUN
b4676a25	96
8353e139	97
7be044e4 JL	98	/*
	99	* BOOTP options
	100	*/
	101	#define CONFIG_BOOTP_SUBNETMASK
	102	#define CONFIG_BOOTP_GATEWAY
	103	#define CONFIG_BOOTP_HOSTNAME
	104	#define CONFIG_BOOTP_BOOTPATH
	105	#define CONFIG_BOOTP_BOOTFILESIZE
	106	#define CONFIG_BOOTP_SUBNETMASK
	107	#define CONFIG_BOOTP_GATEWAY
	108	#define CONFIG_BOOTP_HOSTNAME
	109	#define CONFIG_BOOTP_NISDOMAIN
	110	#define CONFIG_BOOTP_BOOTPATH
	111	#define CONFIG_BOOTP_DNS
	112	#define CONFIG_BOOTP_DNS2
	113	#define CONFIG_BOOTP_SEND_HOSTNAME
	114	#define CONFIG_BOOTP_NTPSERVER
	115	#define CONFIG_BOOTP_TIMEOFFSET
	116
b4676a25 WD	117
	118	/*
	119	* Miscellaneous configurable options
	120	*/
6d0f6bcf JCPV	121	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	122	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	123	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b4676a25	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	126	#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
	127	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	128	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
b4676a25	129
53677ef1	130	#define CONFIG_BOOTCOMMAND "run nfsboot"
b4676a25 WD	131	#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
b4676a25 WD	132
53677ef1	133	#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
b4676a25	134
d4ca31c4 WD	135	#define CONFIG_EXTRA_ENV_SETTINGS \
	136	"console_nr=0\0" \
	137	"dhcp_client_id=mvBOX-XP\0" \
	138	"dhcp_vendor-class-identifier=mvBOX\0" \
	139	"adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
	140	"flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
	141	"safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
	142	"hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
fe126d8b WD	143	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	144	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
	145	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
b4676a25	146	"mv_version=" MV_VERSION "\0" \
d4ca31c4	147	"bootretry=30\0"
b4676a25 WD	148
	149	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	150
	151	/*-----------------------------------------------------------------------
	152	* PCI stuff
	153	*-----------------------------------------------------------------------
	154	*/
	155
d4ca31c4	156	#define CONFIG_PCI
b4676a25 WD	157	#define CONFIG_PCI_PNP
	158	#define CONFIG_PCI_SCAN_SHOW
	159
53677ef1	160	#define CONFIG_NET_RETRY_COUNT 5
b4676a25 WD	161
	162	#define CONFIG_TULIP
	163	#define CONFIG_TULIP_FIX_DAVICOM 1
53677ef1	164	#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
b4676a25 WD	165
	166	#define CONFIG_HW_WATCHDOG
	167
	168	/*-----------------------------------------------------------------------
	169	* Start addresses for the final memory configuration
	170	* (Set up by the startup code)
6d0f6bcf	171	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
b4676a25	172	*/
6d0f6bcf	173	#define CONFIG_SYS_SDRAM_BASE 0x00000000
b4676a25	174
6d0f6bcf	175	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
14d0a02a	176	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
b4676a25	177
6d0f6bcf JCPV	178	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
6d0f6bcf JCPV	179	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
b4676a25	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_MONITOR_LEN 0x00100000
6d0f6bcf JCPV	182	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
b4676a25	183
6d0f6bcf JCPV	184	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	185	#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
b4676a25 WD	186
b4676a25 WD	187	/* Maximum amount of RAM. */
6d0f6bcf	188	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
b4676a25 WD	189
b4676a25 WD	190
6d0f6bcf JCPV	191	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	192	#undef CONFIG_SYS_RAMBOOT
b4676a25	193	#else
6d0f6bcf	194	#define CONFIG_SYS_RAMBOOT
b4676a25 WD	195	#endif
b4676a25 WD	196
6d0f6bcf	197	#define CONFIG_SYS_ISA_IO 0xFE000000
b4676a25 WD	198
	199	/*
	200	* serial configuration
	201	*/
6d0f6bcf JCPV	202	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	203	#define CONFIG_SYS_NS16550_SERIAL
b4676a25	204
6d0f6bcf	205	#define CONFIG_SYS_NS16550_REG_SIZE 1
b4676a25	206
6d0f6bcf	207	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
b4676a25	208
6d0f6bcf JCPV	209	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
6d0f6bcf JCPV	210	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
b4676a25 WD	211
	212	/*-----------------------------------------------------------------------
	213	* Definitions for initial stack pointer and data area
	214	*/
6d0f6bcf	215	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	216	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	217	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
b4676a25 WD	218
	219	/*
	220	* Low Level Configuration Settings
	221	* (address mappings, register initial values, etc.)
	222	* You should know what you are doing if you make changes here.
	223	* For the detail description refer to the MPC8240 user's manual.
	224	*/
	225
d4ca31c4	226	#define CONFIG_SYS_CLK_FREQ 33000000
6d0f6bcf	227	#define CONFIG_SYS_HZ 10000
b4676a25 WD	228
b4676a25 WD	229	/* Bit-field values for MCCR1. */
6d0f6bcf JCPV	230	#define CONFIG_SYS_ROMNAL 7
6d0f6bcf JCPV	231	#define CONFIG_SYS_ROMFAL 11
b4676a25 WD	232
b4676a25 WD	233	/* Bit-field values for MCCR2. */
6d0f6bcf JCPV	234	#define CONFIG_SYS_TSWAIT 0x5
6d0f6bcf JCPV	235	#define CONFIG_SYS_REFINT 430
b4676a25 WD	236
b4676a25 WD	237	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
6d0f6bcf	238	#define CONFIG_SYS_BSTOPRE 121
b4676a25 WD	239
b4676a25 WD	240	/* Bit-field values for MCCR3. */
6d0f6bcf	241	#define CONFIG_SYS_REFREC 8
b4676a25 WD	242
b4676a25 WD	243	/* Bit-field values for MCCR4. */
6d0f6bcf JCPV	244	#define CONFIG_SYS_PRETOACT 3
	245	#define CONFIG_SYS_ACTTOPRE 5
	246	#define CONFIG_SYS_ACTORW 3
	247	#define CONFIG_SYS_SDMODE_CAS_LAT 3
	248	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	249	#define CONFIG_SYS_EXTROM 1
	250	#define CONFIG_SYS_REGDIMM 0
	251	#define CONFIG_SYS_DBUS_SIZE2 1
	252	#define CONFIG_SYS_SDMODE_WRAP 0
	253
	254	#define CONFIG_SYS_PGMAX 0x32
	255	#define CONFIG_SYS_SDRAM_DSCD 0x20
b4676a25 WD	256
	257	/* Memory bank settings.
	258	* Only bits 20-29 are actually used from these vales to set the
	259	* start/end addresses. The upper two bits will always be 0, and the lower
	260	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	261	* address. Refer to the MPC8240 book.
	262	*/
	263
6d0f6bcf JCPV	264	#define CONFIG_SYS_BANK0_START 0x00000000
	265	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	266	#define CONFIG_SYS_BANK0_ENABLE 1
	267	#define CONFIG_SYS_BANK1_START 0x3ff00000
	268	#define CONFIG_SYS_BANK1_END 0x3fffffff
	269	#define CONFIG_SYS_BANK1_ENABLE 0
	270	#define CONFIG_SYS_BANK2_START 0x3ff00000
	271	#define CONFIG_SYS_BANK2_END 0x3fffffff
	272	#define CONFIG_SYS_BANK2_ENABLE 0
	273	#define CONFIG_SYS_BANK3_START 0x3ff00000
	274	#define CONFIG_SYS_BANK3_END 0x3fffffff
	275	#define CONFIG_SYS_BANK3_ENABLE 0
	276	#define CONFIG_SYS_BANK4_START 0x3ff00000
	277	#define CONFIG_SYS_BANK4_END 0x3fffffff
	278	#define CONFIG_SYS_BANK4_ENABLE 0
	279	#define CONFIG_SYS_BANK5_START 0x3ff00000
	280	#define CONFIG_SYS_BANK5_END 0x3fffffff
	281	#define CONFIG_SYS_BANK5_ENABLE 0
	282	#define CONFIG_SYS_BANK6_START 0x3ff00000
	283	#define CONFIG_SYS_BANK6_END 0x3fffffff
	284	#define CONFIG_SYS_BANK6_ENABLE 0
	285	#define CONFIG_SYS_BANK7_START 0x3ff00000
	286	#define CONFIG_SYS_BANK7_END 0x3fffffff
	287	#define CONFIG_SYS_BANK7_ENABLE 0
	288
	289	#define CONFIG_SYS_ODCR 0xff
	290
	291	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	292	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	293
	294	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	295	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	296
	297	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	298	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	299
	300	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	301	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	302
	303	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	304	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	305	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	306	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	307	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	308	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	309	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	310	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
b4676a25 WD	311
	312	/*
	313	* For booting Linux, the board info and command line data
	314	* have to be in the first 8 MB of memory, since this is
	315	* the maximum mapped by the Linux kernel during initialization.
	316	*/
6d0f6bcf	317	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b4676a25 WD	318
	319	/*-----------------------------------------------------------------------
	320	* FLASH organization
	321	*/
6d0f6bcf JCPV	322	#undef CONFIG_SYS_FLASH_PROTECTION
	323	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
	324	#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
b4676a25	325
6d0f6bcf JCPV	326	#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
6d0f6bcf JCPV	327	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
b4676a25 WD	328
b4676a25 WD	329
5a1aceb0	330	#define CONFIG_ENV_IS_IN_FLASH
b4676a25	331
0e8d1586 JCPV	332	#define CONFIG_ENV_OFFSET 0x00010000
	333	#define CONFIG_ENV_SIZE 0x00010000
	334	#define CONFIG_ENV_SECT_SIZE 0x00010000
b4676a25 WD	335
	336	/*-----------------------------------------------------------------------
	337	* Cache Configuration
	338	*/
6d0f6bcf	339	#define CONFIG_SYS_CACHELINE_SIZE 32
8353e139	340	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	341	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
b4676a25	342	#endif
b4676a25	343	#endif /* __CONFIG_H */