[people/ms/u-boot.git] / include / configs / MVBLUE.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#ifndef __CONFIG_H
#define __CONFIG_H

#define MV_VERSION	"v0.2.0"

/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
#define ERR_NONE		0
#define ERR_ENV			1
#define ERR_BOOTM_BADMAGIC	2
#define ERR_BOOTM_BADCRC	3
#define ERR_BOOTM_GUNZIP	4
#define ERR_BOOTP_TIMEOUT	5
#define ERR_DHCP		6
#define ERR_TFTP		7
#define ERR_NOLAN		8
#define ERR_LANDRV		9

#define CONFIG_BOARD_TYPES	1
#define MVBLUE_BOARD_BOX	1
#define MVBLUE_BOARD_LYNX	2

#if 0
#define ERR_LED(code)	do { if (code) \
		*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
	else \
		*(volatile char *)(0xff000003) = ( 1 ); \
} while(0)
#else
#define ERR_LED(code)
#endif

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_MVBLUE		1

#define CONFIG_CLOCKS_IN_MHZ	1

#define CONFIG_BOARD_TYPES	1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOT_RETRY_TIME	-1

#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"autoboot in %d seconds (stop with 's')...\n", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR	"s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY		60


/*
 * Command line configuration.
 */

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_RUN


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/

#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_MAXARGS	16		/* Max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x00100000	/* Default load address			*/

#define CONFIG_BOOTCOMMAND	"run nfsboot"
#define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"

#define CONFIG_NFSBOOTCOMMAND	"bootp; run nfsargs addcons;bootm"

#define CONFIG_EXTRA_ENV_SETTINGS			\
	"console_nr=0\0"				\
    "dhcp_client_id=mvBOX-XP\0"				\
    "dhcp_vendor-class-identifier=mvBOX\0"		\
    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
			"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
    "mv_version=" MV_VERSION "\0"	\
	"bootretry=30\0"

#define CONFIG_OVERWRITE_ETHADDR_ONCE

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */

#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW

#define CONFIG_NET_MULTI
#define CONFIG_NET_RETRY_COUNT		5

#define CONFIG_TULIP
#define CONFIG_TULIP_FIX_DAVICOM	1
#define CONFIG_ETHADDR			b6:b4:45:eb:fb:c0

#define CONFIG_HW_WATCHDOG

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE	    0x00000000

#define CFG_FLASH_BASE      0xFFF00000
#define CFG_MONITOR_BASE    TEXT_BASE

#define CFG_RESET_ADDRESS   0xFFF00100
#define CFG_EUMB_ADDR	    0xFC000000

#define CFG_MONITOR_LEN     0x00100000
#define CFG_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */

#define CFG_MEMTEST_START   0x00100000	/* memtest works on		*/
#define CFG_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/

/* Maximum amount of RAM.  */
#define CFG_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */


#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#undef CFG_RAMBOOT
#else
#define CFG_RAMBOOT
#endif

#define CFG_ISA_IO      0xFE000000

/*
 * serial configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE    1

#define CFG_NS16550_CLK     get_bus_freq(0)

#define CFG_NS16550_COM1    (CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM2    (CFG_EUMB_ADDR + 0x4600)

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CFG_INIT_RAM_ADDR     0x40000000
#define CFG_INIT_RAM_END      0x1000
#define CFG_GBL_DATA_SIZE     128
#define CFG_GBL_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CFG_HZ			 10000

/* Bit-field values for MCCR1.  */
#define CFG_ROMNAL      7
#define CFG_ROMFAL      11

/* Bit-field values for MCCR2.  */
#define CFG_TSWAIT      0x5
#define CFG_REFINT      430

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
#define CFG_BSTOPRE     121

/* Bit-field values for MCCR3.  */
#define CFG_REFREC      8

/* Bit-field values for MCCR4.  */
#define CFG_PRETOACT    3
#define CFG_ACTTOPRE    5
#define CFG_ACTORW      3
#define CFG_SDMODE_CAS_LAT  3
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM      1
#define CFG_REGDIMM     0
#define CFG_DBUS_SIZE2  1
#define CFG_SDMODE_WRAP 0

#define CFG_PGMAX       0x32
#define CFG_SDRAM_DSCD  0x20

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CFG_BANK0_START	    0x00000000
#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
#define CFG_BANK0_ENABLE    1
#define CFG_BANK1_START     0x3ff00000
#define CFG_BANK1_END       0x3fffffff
#define CFG_BANK1_ENABLE    0
#define CFG_BANK2_START     0x3ff00000
#define CFG_BANK2_END       0x3fffffff
#define CFG_BANK2_ENABLE    0
#define CFG_BANK3_START     0x3ff00000
#define CFG_BANK3_END       0x3fffffff
#define CFG_BANK3_ENABLE    0
#define CFG_BANK4_START     0x3ff00000
#define CFG_BANK4_END       0x3fffffff
#define CFG_BANK4_ENABLE    0
#define CFG_BANK5_START     0x3ff00000
#define CFG_BANK5_END       0x3fffffff
#define CFG_BANK5_ENABLE    0
#define CFG_BANK6_START     0x3ff00000
#define CFG_BANK6_END       0x3fffffff
#define CFG_BANK6_ENABLE    0
#define CFG_BANK7_START     0x3ff00000
#define CFG_BANK7_END       0x3fffffff
#define CFG_BANK7_ENABLE    0

#define CFG_ODCR	    0xff

#define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_DBAT0L  CFG_IBAT0L
#define CFG_DBAT0U  CFG_IBAT0U
#define CFG_DBAT1L  CFG_IBAT1L
#define CFG_DBAT1U  CFG_IBAT1U
#define CFG_DBAT2L  CFG_IBAT2L
#define CFG_DBAT2U  CFG_IBAT2U
#define CFG_DBAT3L  CFG_IBAT3L
#define CFG_DBAT3U  CFG_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#undef  CFG_FLASH_PROTECTION
#define CFG_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
#define CFG_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/

#define CFG_FLASH_ERASE_TOUT	12000
#define CFG_FLASH_WRITE_TOUT	1000


#define CFG_ENV_IS_IN_FLASH

#define CFG_ENV_OFFSET		0x00010000
#define CFG_ENV_SIZE		0x00010000
#define CFG_ENV_SECT_SIZE	0x00010000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
b4676a25 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	#define MV_VERSION "v0.2.0"
	29
	30	/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
53677ef1 WD	31	#define ERR_NONE 0
	32	#define ERR_ENV 1
	33	#define ERR_BOOTM_BADMAGIC 2
	34	#define ERR_BOOTM_BADCRC 3
	35	#define ERR_BOOTM_GUNZIP 4
b4676a25	36	#define ERR_BOOTP_TIMEOUT 5
53677ef1 WD	37	#define ERR_DHCP 6
	38	#define ERR_TFTP 7
	39	#define ERR_NOLAN 8
	40	#define ERR_LANDRV 9
b4676a25 WD	41
	42	#define CONFIG_BOARD_TYPES 1
	43	#define MVBLUE_BOARD_BOX 1
	44	#define MVBLUE_BOARD_LYNX 2
	45
	46	#if 0
	47	#define ERR_LED(code) do { if (code) \
53677ef1 WD	48	(volatile char )(0xff000003) = ( 3 \| (code<<4) ) & 0xf3; \
	49	else \
	50	(volatile char )(0xff000003) = ( 1 ); \
	51	} while(0)
b4676a25 WD	52	#else
	53	#define ERR_LED(code)
	54	#endif
	55
b4676a25 WD	56	#define CONFIG_MPC824X 1
	57	#define CONFIG_MPC8245 1
	58	#define CONFIG_MVBLUE 1
	59
	60	#define CONFIG_CLOCKS_IN_MHZ 1
	61
f2302d44	62	#define CONFIG_BOARD_TYPES 1
b4676a25 WD	63
	64	#define CONFIG_CONS_INDEX 1
	65	#define CONFIG_BAUDRATE 115200
	66	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	67
f2302d44	68	#define CONFIG_BOOTDELAY 3
b4676a25 WD	69	#define CONFIG_BOOT_RETRY_TIME -1
	70
	71	#define CONFIG_AUTOBOOT_KEYED
f2302d44 SR	72	#define CONFIG_AUTOBOOT_PROMPT \
f2302d44 SR	73	"autoboot in %d seconds (stop with 's')...\n", bootdelay
d4ca31c4	74	#define CONFIG_AUTOBOOT_STOP_STR "s"
b4676a25 WD	75	#define CONFIG_ZERO_BOOTDELAY_CHECK
	76	#define CONFIG_RESET_TO_RETRY 60
	77
b4676a25	78
8353e139 JL	79	/*
	80	* Command line configuration.
	81	*/
b4676a25	82
8353e139 JL	83	#define CONFIG_CMD_ASKENV
	84	#define CONFIG_CMD_BOOTD
	85	#define CONFIG_CMD_CACHE
	86	#define CONFIG_CMD_DHCP
	87	#define CONFIG_CMD_ECHO
	88	#define CONFIG_CMD_ENV
	89	#define CONFIG_CMD_FLASH
	90	#define CONFIG_CMD_IMI
	91	#define CONFIG_CMD_IRQ
	92	#define CONFIG_CMD_NET
	93	#define CONFIG_CMD_PCI
	94	#define CONFIG_CMD_RUN
b4676a25	95
8353e139	96
7be044e4 JL	97	/*
	98	* BOOTP options
	99	*/
	100	#define CONFIG_BOOTP_SUBNETMASK
	101	#define CONFIG_BOOTP_GATEWAY
	102	#define CONFIG_BOOTP_HOSTNAME
	103	#define CONFIG_BOOTP_BOOTPATH
	104	#define CONFIG_BOOTP_BOOTFILESIZE
	105	#define CONFIG_BOOTP_SUBNETMASK
	106	#define CONFIG_BOOTP_GATEWAY
	107	#define CONFIG_BOOTP_HOSTNAME
	108	#define CONFIG_BOOTP_NISDOMAIN
	109	#define CONFIG_BOOTP_BOOTPATH
	110	#define CONFIG_BOOTP_DNS
	111	#define CONFIG_BOOTP_DNS2
	112	#define CONFIG_BOOTP_SEND_HOSTNAME
	113	#define CONFIG_BOOTP_NTPSERVER
	114	#define CONFIG_BOOTP_TIMEOFFSET
	115
b4676a25 WD	116
	117	/*
	118	* Miscellaneous configurable options
	119	*/
53677ef1 WD	120	#define CFG_LONGHELP /* undef to save memory */
53677ef1 WD	121	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
b4676a25 WD	122	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
b4676a25 WD	123
53677ef1 WD	124	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
53677ef1 WD	125	#define CFG_MAXARGS 16 /* Max number of command args */
b4676a25 WD	126	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	127	#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
	128
53677ef1	129	#define CONFIG_BOOTCOMMAND "run nfsboot"
b4676a25 WD	130	#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
b4676a25 WD	131
53677ef1	132	#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
b4676a25	133
d4ca31c4 WD	134	#define CONFIG_EXTRA_ENV_SETTINGS \
	135	"console_nr=0\0" \
	136	"dhcp_client_id=mvBOX-XP\0" \
	137	"dhcp_vendor-class-identifier=mvBOX\0" \
	138	"adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
	139	"flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
	140	"safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
	141	"hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
fe126d8b WD	142	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	143	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
	144	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
b4676a25	145	"mv_version=" MV_VERSION "\0" \
d4ca31c4	146	"bootretry=30\0"
b4676a25 WD	147
	148	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	149
	150	/*-----------------------------------------------------------------------
	151	* PCI stuff
	152	*-----------------------------------------------------------------------
	153	*/
	154
d4ca31c4	155	#define CONFIG_PCI
b4676a25 WD	156	#define CONFIG_PCI_PNP
	157	#define CONFIG_PCI_SCAN_SHOW
	158
d4ca31c4	159	#define CONFIG_NET_MULTI
53677ef1	160	#define CONFIG_NET_RETRY_COUNT 5
b4676a25 WD	161
	162	#define CONFIG_TULIP
	163	#define CONFIG_TULIP_FIX_DAVICOM 1
53677ef1	164	#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
b4676a25 WD	165
	166	#define CONFIG_HW_WATCHDOG
	167
	168	/*-----------------------------------------------------------------------
	169	* Start addresses for the final memory configuration
	170	* (Set up by the startup code)
	171	* Please note that CFG_SDRAM_BASE _must_ start at 0
	172	*/
	173	#define CFG_SDRAM_BASE 0x00000000
	174
d4ca31c4 WD	175	#define CFG_FLASH_BASE 0xFFF00000
d4ca31c4 WD	176	#define CFG_MONITOR_BASE TEXT_BASE
b4676a25 WD	177
	178	#define CFG_RESET_ADDRESS 0xFFF00100
	179	#define CFG_EUMB_ADDR 0xFC000000
	180
	181	#define CFG_MONITOR_LEN 0x00100000
	182	#define CFG_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
	183
	184	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	185	#define CFG_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
	186
	187	/* Maximum amount of RAM. */
	188	#define CFG_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
	189
	190
	191	#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
	192	#undef CFG_RAMBOOT
	193	#else
	194	#define CFG_RAMBOOT
	195	#endif
	196
	197	#define CFG_ISA_IO 0xFE000000
	198
	199	/*
	200	* serial configuration
	201	*/
	202	#define CFG_NS16550
	203	#define CFG_NS16550_SERIAL
	204
	205	#define CFG_NS16550_REG_SIZE 1
	206
	207	#define CFG_NS16550_CLK get_bus_freq(0)
	208
	209	#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
	210	#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
	211
	212	/*-----------------------------------------------------------------------
	213	* Definitions for initial stack pointer and data area
	214	*/
	215	#define CFG_INIT_RAM_ADDR 0x40000000
	216	#define CFG_INIT_RAM_END 0x1000
	217	#define CFG_GBL_DATA_SIZE 128
	218	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	219
	220	/*
	221	* Low Level Configuration Settings
	222	* (address mappings, register initial values, etc.)
	223	* You should know what you are doing if you make changes here.
	224	* For the detail description refer to the MPC8240 user's manual.
	225	*/
	226
d4ca31c4	227	#define CONFIG_SYS_CLK_FREQ 33000000
53677ef1	228	#define CFG_HZ 10000
b4676a25 WD	229
	230	/* Bit-field values for MCCR1. */
	231	#define CFG_ROMNAL 7
	232	#define CFG_ROMFAL 11
	233
	234	/* Bit-field values for MCCR2. */
	235	#define CFG_TSWAIT 0x5
d4ca31c4	236	#define CFG_REFINT 430
b4676a25 WD	237
b4676a25 WD	238	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
d4ca31c4	239	#define CFG_BSTOPRE 121
b4676a25 WD	240
	241	/* Bit-field values for MCCR3. */
	242	#define CFG_REFREC 8
	243
	244	/* Bit-field values for MCCR4. */
d4ca31c4 WD	245	#define CFG_PRETOACT 3
d4ca31c4 WD	246	#define CFG_ACTTOPRE 5
b4676a25 WD	247	#define CFG_ACTORW 3
	248	#define CFG_SDMODE_CAS_LAT 3
	249	#define CFG_REGISTERD_TYPE_BUFFER 1
	250	#define CFG_EXTROM 1
	251	#define CFG_REGDIMM 0
	252	#define CFG_DBUS_SIZE2 1
	253	#define CFG_SDMODE_WRAP 0
	254
	255	#define CFG_PGMAX 0x32
	256	#define CFG_SDRAM_DSCD 0x20
	257
	258	/* Memory bank settings.
	259	* Only bits 20-29 are actually used from these vales to set the
	260	* start/end addresses. The upper two bits will always be 0, and the lower
	261	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	262	* address. Refer to the MPC8240 book.
	263	*/
	264
	265	#define CFG_BANK0_START 0x00000000
	266	#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
	267	#define CFG_BANK0_ENABLE 1
	268	#define CFG_BANK1_START 0x3ff00000
	269	#define CFG_BANK1_END 0x3fffffff
	270	#define CFG_BANK1_ENABLE 0
	271	#define CFG_BANK2_START 0x3ff00000
	272	#define CFG_BANK2_END 0x3fffffff
	273	#define CFG_BANK2_ENABLE 0
	274	#define CFG_BANK3_START 0x3ff00000
	275	#define CFG_BANK3_END 0x3fffffff
	276	#define CFG_BANK3_ENABLE 0
	277	#define CFG_BANK4_START 0x3ff00000
	278	#define CFG_BANK4_END 0x3fffffff
	279	#define CFG_BANK4_ENABLE 0
	280	#define CFG_BANK5_START 0x3ff00000
	281	#define CFG_BANK5_END 0x3fffffff
	282	#define CFG_BANK5_ENABLE 0
	283	#define CFG_BANK6_START 0x3ff00000
	284	#define CFG_BANK6_END 0x3fffffff
	285	#define CFG_BANK6_ENABLE 0
	286	#define CFG_BANK7_START 0x3ff00000
	287	#define CFG_BANK7_END 0x3fffffff
	288	#define CFG_BANK7_ENABLE 0
	289
	290	#define CFG_ODCR 0xff
	291
	292	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	293	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	294
	295	#define CFG_IBAT1L (CFG_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	296	#define CFG_IBAT1U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	297
	298	#define CFG_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	299	#define CFG_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	300
	301	#define CFG_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	302	#define CFG_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	303
	304	#define CFG_DBAT0L CFG_IBAT0L
	305	#define CFG_DBAT0U CFG_IBAT0U
	306	#define CFG_DBAT1L CFG_IBAT1L
	307	#define CFG_DBAT1U CFG_IBAT1U
	308	#define CFG_DBAT2L CFG_IBAT2L
	309	#define CFG_DBAT2U CFG_IBAT2U
	310	#define CFG_DBAT3L CFG_IBAT3L
311	#define CFG_DBAT3U CFG_IBAT3U
312
313	/*
314	* For booting Linux, the board info and command line data
315	* have to be in the first 8 MB of memory, since this is
316	* the maximum mapped by the Linux kernel during initialization.
317	*/
318	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
319
320	/*-----------------------------------------------------------------------
321	* FLASH organization
322	*/
d4ca31c4	323	#undef CFG_FLASH_PROTECTION
b4676a25 WD	324	#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
	325	#define CFG_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
	326
	327	#define CFG_FLASH_ERASE_TOUT 12000
	328	#define CFG_FLASH_WRITE_TOUT 1000
	329
	330
d4ca31c4	331	#define CFG_ENV_IS_IN_FLASH
b4676a25 WD	332
b4676a25 WD	333	#define CFG_ENV_OFFSET 0x00010000
d4ca31c4 WD	334	#define CFG_ENV_SIZE 0x00010000
d4ca31c4 WD	335	#define CFG_ENV_SECT_SIZE 0x00010000
b4676a25 WD	336
	337	/*-----------------------------------------------------------------------
	338	* Cache Configuration
	339	*/
	340	#define CFG_CACHELINE_SIZE 32
8353e139	341	#if defined(CONFIG_CMD_KGDB)
b4676a25 WD	342	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	343	#endif
	344
	345	/*
	346	* Internal Definitions
	347	*
	348	* Boot Flags
	349	*/
	350	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	351	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	352
	353	#endif /* __CONFIG_H */