[thirdparty/u-boot.git] / include / configs / MVBLUE.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#ifndef __CONFIG_H
#define __CONFIG_H

#define MV_VERSION	"v0.2.0"

/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
#define ERR_NONE		0
#define ERR_ENV			1
#define ERR_BOOTM_BADMAGIC	2
#define ERR_BOOTM_BADCRC	3
#define ERR_BOOTM_GUNZIP	4
#define ERR_BOOTP_TIMEOUT	5
#define ERR_DHCP		6
#define ERR_TFTP		7
#define ERR_NOLAN		8
#define ERR_LANDRV		9

#define CONFIG_BOARD_TYPES	1
#define MVBLUE_BOARD_BOX	1
#define MVBLUE_BOARD_LYNX	2

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
#define CONFIG_SYS_LDSCRIPT	"board/mvblue/u-boot.lds"

#if 0
#define ERR_LED(code)	do { if (code) \
		*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
	else \
		*(volatile char *)(0xff000003) = ( 1 ); \
} while(0)
#else
#define ERR_LED(code)
#endif

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_MVBLUE		1

#define CONFIG_CLOCKS_IN_MHZ	1

#define CONFIG_BOARD_TYPES	1

#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		115200

#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOT_RETRY_TIME	-1

#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"autoboot in %d seconds (stop with 's')...\n", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR	"s"
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_RESET_TO_RETRY		60


/*
 * Command line configuration.
 */

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_RUN


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16		/* Max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address			*/

#define CONFIG_BOOTCOMMAND	"run nfsboot"
#define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"

#define CONFIG_NFSBOOTCOMMAND	"bootp; run nfsargs addcons;bootm"

#define CONFIG_EXTRA_ENV_SETTINGS			\
	"console_nr=0\0"				\
    "dhcp_client_id=mvBOX-XP\0"				\
    "dhcp_vendor-class-identifier=mvBOX\0"		\
    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
			"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
    "mv_version=" MV_VERSION "\0"	\
	"bootretry=30\0"

#define CONFIG_OVERWRITE_ETHADDR_ONCE

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW

#define CONFIG_NET_RETRY_COUNT		5

#define CONFIG_TULIP
#define CONFIG_TULIP_FIX_DAVICOM	1
#define CONFIG_ETHADDR			b6:b4:45:eb:fb:c0

#define CONFIG_HW_WATCHDOG

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE	    0x00000000

#define CONFIG_SYS_FLASH_BASE      0xFFF00000
#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
#define CONFIG_SYS_EUMB_ADDR	    0xFC000000

#define CONFIG_SYS_MONITOR_LEN     0x00100000
#define CONFIG_SYS_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */

#define CONFIG_SYS_MEMTEST_START   0x00100000	/* memtest works on		*/
#define CONFIG_SYS_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/

/* Maximum amount of RAM.  */
#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */


#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
#undef CONFIG_SYS_RAMBOOT
#else
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_ISA_IO      0xFE000000

/*
 * serial configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE    1

#define CONFIG_SYS_NS16550_CLK     get_bus_freq(0)

#define CONFIG_SYS_NS16550_COM1    (CONFIG_SYS_EUMB_ADDR + 0x4500)
#define CONFIG_SYS_NS16550_COM2    (CONFIG_SYS_EUMB_ADDR + 0x4600)

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CONFIG_SYS_HZ			 10000

/* Bit-field values for MCCR1.  */
#define CONFIG_SYS_ROMNAL      7
#define CONFIG_SYS_ROMFAL      11

/* Bit-field values for MCCR2.  */
#define CONFIG_SYS_TSWAIT      0x5
#define CONFIG_SYS_REFINT      430

/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
#define CONFIG_SYS_BSTOPRE     121

/* Bit-field values for MCCR3.  */
#define CONFIG_SYS_REFREC      8

/* Bit-field values for MCCR4.  */
#define CONFIG_SYS_PRETOACT    3
#define CONFIG_SYS_ACTTOPRE    5
#define CONFIG_SYS_ACTORW      3
#define CONFIG_SYS_SDMODE_CAS_LAT  3
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
#define CONFIG_SYS_EXTROM      1
#define CONFIG_SYS_REGDIMM     0
#define CONFIG_SYS_DBUS_SIZE2  1
#define CONFIG_SYS_SDMODE_WRAP 0

#define CONFIG_SYS_PGMAX       0x32
#define CONFIG_SYS_SDRAM_DSCD  0x20

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */

#define CONFIG_SYS_BANK0_START	    0x00000000
#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START     0x3ff00000
#define CONFIG_SYS_BANK1_END       0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START     0x3ff00000
#define CONFIG_SYS_BANK2_END       0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START     0x3ff00000
#define CONFIG_SYS_BANK3_END       0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START     0x3ff00000
#define CONFIG_SYS_BANK4_END       0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START     0x3ff00000
#define CONFIG_SYS_BANK5_END       0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START     0x3ff00000
#define CONFIG_SYS_BANK6_END       0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START     0x3ff00000
#define CONFIG_SYS_BANK7_END       0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR	    0xff

#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000


#define CONFIG_ENV_IS_IN_FLASH

#define CONFIG_ENV_OFFSET		0x00010000
#define CONFIG_ENV_SIZE		0x00010000
#define CONFIG_ENV_SECT_SIZE	0x00010000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
b4676a25 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
b4676a25 WD	6	*/
	7
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	#define MV_VERSION "v0.2.0"
	13
	14	/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
53677ef1 WD	15	#define ERR_NONE 0
	16	#define ERR_ENV 1
	17	#define ERR_BOOTM_BADMAGIC 2
	18	#define ERR_BOOTM_BADCRC 3
	19	#define ERR_BOOTM_GUNZIP 4
b4676a25	20	#define ERR_BOOTP_TIMEOUT 5
53677ef1 WD	21	#define ERR_DHCP 6
	22	#define ERR_TFTP 7
	23	#define ERR_NOLAN 8
	24	#define ERR_LANDRV 9
b4676a25 WD	25
	26	#define CONFIG_BOARD_TYPES 1
	27	#define MVBLUE_BOARD_BOX 1
	28	#define MVBLUE_BOARD_LYNX 2
	29
2ae18241	30	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
de550d6b	31	#define CONFIG_SYS_LDSCRIPT "board/mvblue/u-boot.lds"
2ae18241	32
b4676a25 WD	33	#if 0
b4676a25 WD	34	#define ERR_LED(code) do { if (code) \
53677ef1 WD	35	(volatile char )(0xff000003) = ( 3 \| (code<<4) ) & 0xf3; \
	36	else \
	37	(volatile char )(0xff000003) = ( 1 ); \
	38	} while(0)
b4676a25 WD	39	#else
	40	#define ERR_LED(code)
	41	#endif
	42
b4676a25 WD	43	#define CONFIG_MPC824X 1
	44	#define CONFIG_MPC8245 1
	45	#define CONFIG_MVBLUE 1
	46
	47	#define CONFIG_CLOCKS_IN_MHZ 1
	48
f2302d44	49	#define CONFIG_BOARD_TYPES 1
b4676a25 WD	50
	51	#define CONFIG_CONS_INDEX 1
	52	#define CONFIG_BAUDRATE 115200
b4676a25	53
f2302d44	54	#define CONFIG_BOOTDELAY 3
b4676a25 WD	55	#define CONFIG_BOOT_RETRY_TIME -1
	56
	57	#define CONFIG_AUTOBOOT_KEYED
f2302d44 SR	58	#define CONFIG_AUTOBOOT_PROMPT \
f2302d44 SR	59	"autoboot in %d seconds (stop with 's')...\n", bootdelay
d4ca31c4	60	#define CONFIG_AUTOBOOT_STOP_STR "s"
b4676a25 WD	61	#define CONFIG_ZERO_BOOTDELAY_CHECK
	62	#define CONFIG_RESET_TO_RETRY 60
	63
b4676a25	64
8353e139 JL	65	/*
	66	* Command line configuration.
	67	*/
b4676a25	68
8353e139 JL	69	#define CONFIG_CMD_ASKENV
	70	#define CONFIG_CMD_BOOTD
	71	#define CONFIG_CMD_CACHE
	72	#define CONFIG_CMD_DHCP
	73	#define CONFIG_CMD_ECHO
bdab39d3	74	#define CONFIG_CMD_SAVEENV
8353e139 JL	75	#define CONFIG_CMD_FLASH
8353e139 JL	76	#define CONFIG_CMD_IMI
8353e139 JL	77	#define CONFIG_CMD_NET
	78	#define CONFIG_CMD_PCI
	79	#define CONFIG_CMD_RUN
b4676a25	80
8353e139	81
7be044e4 JL	82	/*
	83	* BOOTP options
	84	*/
	85	#define CONFIG_BOOTP_SUBNETMASK
	86	#define CONFIG_BOOTP_GATEWAY
	87	#define CONFIG_BOOTP_HOSTNAME
	88	#define CONFIG_BOOTP_BOOTPATH
	89	#define CONFIG_BOOTP_BOOTFILESIZE
	90	#define CONFIG_BOOTP_SUBNETMASK
	91	#define CONFIG_BOOTP_GATEWAY
	92	#define CONFIG_BOOTP_HOSTNAME
	93	#define CONFIG_BOOTP_NISDOMAIN
	94	#define CONFIG_BOOTP_BOOTPATH
	95	#define CONFIG_BOOTP_DNS
	96	#define CONFIG_BOOTP_DNS2
	97	#define CONFIG_BOOTP_SEND_HOSTNAME
	98	#define CONFIG_BOOTP_NTPSERVER
	99	#define CONFIG_BOOTP_TIMEOFFSET
	100
b4676a25 WD	101
	102	/*
	103	* Miscellaneous configurable options
	104	*/
6d0f6bcf JCPV	105	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	106	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	107	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b4676a25	108
6d0f6bcf JCPV	109	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	110	#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
	111	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	112	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
b4676a25	113
53677ef1	114	#define CONFIG_BOOTCOMMAND "run nfsboot"
b4676a25 WD	115	#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
b4676a25 WD	116
53677ef1	117	#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
b4676a25	118
d4ca31c4 WD	119	#define CONFIG_EXTRA_ENV_SETTINGS \
	120	"console_nr=0\0" \
	121	"dhcp_client_id=mvBOX-XP\0" \
	122	"dhcp_vendor-class-identifier=mvBOX\0" \
	123	"adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
	124	"flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
	125	"safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
	126	"hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
fe126d8b WD	127	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	128	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
	129	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
b4676a25	130	"mv_version=" MV_VERSION "\0" \
d4ca31c4	131	"bootretry=30\0"
b4676a25 WD	132
	133	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	134
	135	/*-----------------------------------------------------------------------
	136	* PCI stuff
	137	*-----------------------------------------------------------------------
	138	*/
	139
d4ca31c4	140	#define CONFIG_PCI
842033e6	141	#define CONFIG_PCI_INDIRECT_BRIDGE
b4676a25 WD	142	#define CONFIG_PCI_PNP
	143	#define CONFIG_PCI_SCAN_SHOW
	144
53677ef1	145	#define CONFIG_NET_RETRY_COUNT 5
b4676a25 WD	146
	147	#define CONFIG_TULIP
	148	#define CONFIG_TULIP_FIX_DAVICOM 1
53677ef1	149	#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
b4676a25 WD	150
	151	#define CONFIG_HW_WATCHDOG
	152
	153	/*-----------------------------------------------------------------------
	154	* Start addresses for the final memory configuration
	155	* (Set up by the startup code)
6d0f6bcf	156	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
b4676a25	157	*/
6d0f6bcf	158	#define CONFIG_SYS_SDRAM_BASE 0x00000000
b4676a25	159
6d0f6bcf	160	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
14d0a02a	161	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
b4676a25	162
6d0f6bcf JCPV	163	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
6d0f6bcf JCPV	164	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
b4676a25	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_MONITOR_LEN 0x00100000
6d0f6bcf JCPV	167	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
b4676a25	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	170	#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
b4676a25 WD	171
b4676a25 WD	172	/* Maximum amount of RAM. */
6d0f6bcf	173	#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
b4676a25 WD	174
b4676a25 WD	175
6d0f6bcf JCPV	176	#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	177	#undef CONFIG_SYS_RAMBOOT
b4676a25	178	#else
6d0f6bcf	179	#define CONFIG_SYS_RAMBOOT
b4676a25 WD	180	#endif
b4676a25 WD	181
6d0f6bcf	182	#define CONFIG_SYS_ISA_IO 0xFE000000
b4676a25 WD	183
	184	/*
	185	* serial configuration
	186	*/
6d0f6bcf JCPV	187	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	188	#define CONFIG_SYS_NS16550_SERIAL
b4676a25	189
6d0f6bcf	190	#define CONFIG_SYS_NS16550_REG_SIZE 1
b4676a25	191
6d0f6bcf	192	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
b4676a25	193
6d0f6bcf JCPV	194	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
6d0f6bcf JCPV	195	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
b4676a25 WD	196
	197	/*-----------------------------------------------------------------------
	198	* Definitions for initial stack pointer and data area
	199	*/
6d0f6bcf	200	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
553f0982	201	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
25ddd1fb	202	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
b4676a25 WD	203
	204	/*
	205	* Low Level Configuration Settings
	206	* (address mappings, register initial values, etc.)
	207	* You should know what you are doing if you make changes here.
	208	* For the detail description refer to the MPC8240 user's manual.
	209	*/
	210
d4ca31c4	211	#define CONFIG_SYS_CLK_FREQ 33000000
6d0f6bcf	212	#define CONFIG_SYS_HZ 10000
b4676a25 WD	213
b4676a25 WD	214	/* Bit-field values for MCCR1. */
6d0f6bcf JCPV	215	#define CONFIG_SYS_ROMNAL 7
6d0f6bcf JCPV	216	#define CONFIG_SYS_ROMFAL 11
b4676a25 WD	217
b4676a25 WD	218	/* Bit-field values for MCCR2. */
6d0f6bcf JCPV	219	#define CONFIG_SYS_TSWAIT 0x5
6d0f6bcf JCPV	220	#define CONFIG_SYS_REFINT 430
b4676a25 WD	221
b4676a25 WD	222	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
6d0f6bcf	223	#define CONFIG_SYS_BSTOPRE 121
b4676a25 WD	224
b4676a25 WD	225	/* Bit-field values for MCCR3. */
6d0f6bcf	226	#define CONFIG_SYS_REFREC 8
b4676a25 WD	227
b4676a25 WD	228	/* Bit-field values for MCCR4. */
6d0f6bcf JCPV	229	#define CONFIG_SYS_PRETOACT 3
	230	#define CONFIG_SYS_ACTTOPRE 5
	231	#define CONFIG_SYS_ACTORW 3
	232	#define CONFIG_SYS_SDMODE_CAS_LAT 3
	233	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
	234	#define CONFIG_SYS_EXTROM 1
	235	#define CONFIG_SYS_REGDIMM 0
	236	#define CONFIG_SYS_DBUS_SIZE2 1
	237	#define CONFIG_SYS_SDMODE_WRAP 0
	238
	239	#define CONFIG_SYS_PGMAX 0x32
	240	#define CONFIG_SYS_SDRAM_DSCD 0x20
b4676a25 WD	241
	242	/* Memory bank settings.
	243	* Only bits 20-29 are actually used from these vales to set the
	244	* start/end addresses. The upper two bits will always be 0, and the lower
	245	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	246	* address. Refer to the MPC8240 book.
	247	*/
	248
6d0f6bcf JCPV	249	#define CONFIG_SYS_BANK0_START 0x00000000
	250	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
	251	#define CONFIG_SYS_BANK0_ENABLE 1
	252	#define CONFIG_SYS_BANK1_START 0x3ff00000
	253	#define CONFIG_SYS_BANK1_END 0x3fffffff
	254	#define CONFIG_SYS_BANK1_ENABLE 0
	255	#define CONFIG_SYS_BANK2_START 0x3ff00000
	256	#define CONFIG_SYS_BANK2_END 0x3fffffff
	257	#define CONFIG_SYS_BANK2_ENABLE 0
	258	#define CONFIG_SYS_BANK3_START 0x3ff00000
	259	#define CONFIG_SYS_BANK3_END 0x3fffffff
	260	#define CONFIG_SYS_BANK3_ENABLE 0
	261	#define CONFIG_SYS_BANK4_START 0x3ff00000
	262	#define CONFIG_SYS_BANK4_END 0x3fffffff
	263	#define CONFIG_SYS_BANK4_ENABLE 0
	264	#define CONFIG_SYS_BANK5_START 0x3ff00000
	265	#define CONFIG_SYS_BANK5_END 0x3fffffff
	266	#define CONFIG_SYS_BANK5_ENABLE 0
	267	#define CONFIG_SYS_BANK6_START 0x3ff00000
	268	#define CONFIG_SYS_BANK6_END 0x3fffffff
	269	#define CONFIG_SYS_BANK6_ENABLE 0
	270	#define CONFIG_SYS_BANK7_START 0x3ff00000
	271	#define CONFIG_SYS_BANK7_END 0x3fffffff
	272	#define CONFIG_SYS_BANK7_ENABLE 0
	273
	274	#define CONFIG_SYS_ODCR 0xff
	275
	276	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	277	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	278
	279	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	280	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	281
	282	#define CONFIG_SYS_IBAT2L (0x80000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	283	#define CONFIG_SYS_IBAT2U (0x80000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	284
	285	#define CONFIG_SYS_IBAT3L (0xF0000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT)
	286	#define CONFIG_SYS_IBAT3U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	287
	288	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	289	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	290	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	291	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	292	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	293	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	294	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	295	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
b4676a25 WD	296
	297	/*
	298	* For booting Linux, the board info and command line data
	299	* have to be in the first 8 MB of memory, since this is
	300	* the maximum mapped by the Linux kernel during initialization.
	301	*/
6d0f6bcf	302	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b4676a25 WD	303
	304	/*-----------------------------------------------------------------------
	305	* FLASH organization
	306	*/
6d0f6bcf JCPV	307	#undef CONFIG_SYS_FLASH_PROTECTION
	308	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
	309	#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
b4676a25	310
6d0f6bcf JCPV	311	#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
6d0f6bcf JCPV	312	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
b4676a25 WD	313
b4676a25 WD	314
5a1aceb0	315	#define CONFIG_ENV_IS_IN_FLASH
b4676a25	316
0e8d1586 JCPV	317	#define CONFIG_ENV_OFFSET 0x00010000
	318	#define CONFIG_ENV_SIZE 0x00010000
	319	#define CONFIG_ENV_SECT_SIZE 0x00010000
b4676a25 WD	320
	321	/*-----------------------------------------------------------------------
	322	* Cache Configuration
	323	*/
6d0f6bcf	324	#define CONFIG_SYS_CACHELINE_SIZE 32
8353e139	325	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	326	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
b4676a25	327	#endif
b4676a25	328	#endif /* __CONFIG_H */