[people/ms/u-boot.git] / include / configs / MVSMR.h

/*
 * (C) Copyright 2003-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2010
 * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <version.h>

#define CONFIG_MPC5xxx	1
#define CONFIG_MPC5200 	1

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFF800000
#endif
#define CONFIG_SYS_LDSCRIPT	"board/matrix_vision/mvsmr/u-boot.lds"

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000

#define CONFIG_MISC_INIT_R	1

#define CONFIG_SYS_CACHELINE_SIZE	32
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5
#endif

#define CONFIG_PSC_CONSOLE	1
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200,\
						230400}

#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#undef	CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_XLB_PIPELINING	1
#define CONFIG_HIGH_BATS	1

#define MV_CI			mvSMR
#define MV_VCI			mvSMR
#define MV_FPGA_DATA		0xff840000
#define MV_FPGA_SIZE		0x1ff88
#define MV_KERNEL_ADDR		0xfff00000
#define MV_SCRIPT_ADDR		0xff806000
#define MV_INITRD_ADDR		0xff880000
#define MV_INITRD_LENGTH	0x00240000
#define MV_SCRATCH_ADDR		0xffcc0000
#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH

#define CONFIG_SHOW_BOOT_PROGRESS 1

#define MV_KERNEL_ADDR_RAM	0x00100000
#define MV_INITRD_ADDR_RAM	0x00400000

/*
 * Supported commands
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FPGA
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SDRAM

#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_RANDOM_DELAY
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_VENDOREX

/*
 * Autoboot
 */
#define CONFIG_BOOTDELAY		1
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR 	"abcdefg"
#define CONFIG_ZERO_BOOTDELAY_CHECK

#define CONFIG_BOOTCOMMAND      "source ${script_addr}"
#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs" \
					" allocate=6M"

#define CONFIG_EXTRA_ENV_SETTINGS				\
	"console_nr=0\0"					\
	"console=no\0"						\
	"stdin=serial\0"					\
	"stdout=serial\0"					\
	"stderr=serial\0"					\
	"fpga=0\0"						\
	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
	"mv_version=" U_BOOT_VERSION "\0"			\
	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
	"netretry=no\0"						\
	"use_static_ipaddr=no\0"				\
	"static_ipaddr=192.168.0.101\0"				\
	"static_netmask=255.255.255.0\0"			\
	"static_gateway=0.0.0.0\0"				\
	"initrd_name=uInitrd.mvsmr-rfs\0"			\
	"zcip=yes\0"						\
	"netboot=no\0"						\
	""

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK

/*
 * Flash configuration
 */
#undef 	CONFIG_FLASH_16BIT
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
#define CONFIG_SYS_FLASH_WRITE_TOUT	1000

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	256

#define CONFIG_SYS_LOWBOOT
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_FLASH_SIZE		0x00800000

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH
#undef	CONFIG_SYS_FLASH_PROTECTION
#define	CONFIG_OVERWRITE_ETHADDR_ONCE

#define CONFIG_ENV_OFFSET	0x8000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000

/* used by linker script to wrap code around */
#define CONFIG_SCRIPT_OFFSET	0x6000
#define CONFIG_SCRIPT_SECT_SIZE	0x2000

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE	0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_MODULE	1
#define CONFIG_SYS_I2C_SPEED	86000
#define CONFIG_SYS_I2C_SLAVE	0x7F

/*
 * Ethernet configuration
 */
#define CONFIG_NET_RETRY_COUNT 5

#define CONFIG_MPC5xxx_FEC
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_NETDEV		eth0

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#undef 	CONFIG_SYS_LONGHELP
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE		1024
#else
#define CONFIG_SYS_CBSIZE		256
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_MEMTEST_START	0x00800000
#define CONFIG_SYS_MEMTEST_END		0x02f00000

/* default load address */
#define CONFIG_SYS_LOAD_ADDR		0x02000000
/* default location for tftp and bootm */
#define CONFIG_LOADADDR 		0x00200000

/*
 * Various low-level settings
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x00050044

#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#define CONFIG_SYS_CS_BURST		0x000000f0
#define CONFIG_SYS_CS_DEADCYCLE		0x33333303

#define CONFIG_SYS_RESET_ADDRESS	0x00000100

#undef FPGA_DEBUG
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX	1
#define CONFIG_FPGA_SPARTAN2	1
#define CONFIG_FPGA_COUNT	1

#endif
Commit	Line	Data
1f2463d7 AS	1	/*
	2	* (C) Copyright 2003-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004-2010
	6	* Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
1f2463d7 AS	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	#include <version.h>
	15
	16	#define CONFIG_MPC5xxx 1
	17	#define CONFIG_MPC5200 1
	18
2ae18241 WD	19	#ifndef CONFIG_SYS_TEXT_BASE
	20	#define CONFIG_SYS_TEXT_BASE 0xFF800000
	21	#endif
2ced53e1	22	#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds"
2ae18241	23
1f2463d7 AS	24	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
1f2463d7 AS	25
1f2463d7 AS	26	#define CONFIG_MISC_INIT_R 1
	27
	28	#define CONFIG_SYS_CACHELINE_SIZE 32
	29	#ifdef CONFIG_CMD_KGDB
	30	#define CONFIG_SYS_CACHELINE_SHIFT 5
	31	#endif
	32
	33	#define CONFIG_PSC_CONSOLE 1
	34	#define CONFIG_BAUDRATE 115200
	35	#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
	36	230400}
	37
	38	#define CONFIG_PCI 1
	39	#define CONFIG_PCI_PNP 1
	40	#undef CONFIG_PCI_SCAN_SHOW
	41	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
	42
	43	#define CONFIG_PCI_MEM_BUS 0x40000000
	44	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	45	#define CONFIG_PCI_MEM_SIZE 0x10000000
	46
	47	#define CONFIG_PCI_IO_BUS 0x50000000
	48	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	49	#define CONFIG_PCI_IO_SIZE 0x01000000
	50
	51	#define CONFIG_SYS_XLB_PIPELINING 1
	52	#define CONFIG_HIGH_BATS 1
	53
	54	#define MV_CI mvSMR
	55	#define MV_VCI mvSMR
	56	#define MV_FPGA_DATA 0xff840000
	57	#define MV_FPGA_SIZE 0x1ff88
	58	#define MV_KERNEL_ADDR 0xfff00000
	59	#define MV_SCRIPT_ADDR 0xff806000
	60	#define MV_INITRD_ADDR 0xff880000
	61	#define MV_INITRD_LENGTH 0x00240000
	62	#define MV_SCRATCH_ADDR 0xffcc0000
	63	#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
	64
	65	#define CONFIG_SHOW_BOOT_PROGRESS 1
	66
	67	#define MV_KERNEL_ADDR_RAM 0x00100000
	68	#define MV_INITRD_ADDR_RAM 0x00400000
	69
	70	/*
	71	* Supported commands
	72	*/
	73	#include <config_cmd_default.h>
	74
	75	#define CONFIG_CMD_CACHE
	76	#define CONFIG_CMD_DHCP
	77	#define CONFIG_CMD_FPGA
	78	#define CONFIG_CMD_I2C
	79	#define CONFIG_CMD_MII
	80	#define CONFIG_CMD_NET
	81	#define CONFIG_CMD_PCI
	82	#define CONFIG_CMD_PING
	83	#define CONFIG_CMD_SDRAM
	84
	85	#define CONFIG_BOOTP_BOOTFILESIZE
	86	#define CONFIG_BOOTP_BOOTPATH
	87	#define CONFIG_BOOTP_DNS
	88	#define CONFIG_BOOTP_DNS2
	89	#define CONFIG_BOOTP_GATEWAY
90	#define CONFIG_BOOTP_HOSTNAME
91	#define CONFIG_BOOTP_NTPSERVER
92	#define CONFIG_BOOTP_RANDOM_DELAY
93	#define CONFIG_BOOTP_SEND_HOSTNAME
94	#define CONFIG_BOOTP_SUBNETMASK
95	#define CONFIG_BOOTP_VENDOREX
96
97	/*
98	* Autoboot
99	*/
100	#define CONFIG_BOOTDELAY 1
101	#define CONFIG_AUTOBOOT_KEYED
102	#define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
103	#define CONFIG_ZERO_BOOTDELAY_CHECK
104
105	#define CONFIG_BOOTCOMMAND "source ${script_addr}"
106	#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
107	" allocate=6M"
108
1f2463d7 AS	109	#define CONFIG_EXTRA_ENV_SETTINGS \
	110	"console_nr=0\0" \
	111	"console=no\0" \
	112	"stdin=serial\0" \
	113	"stdout=serial\0" \
	114	"stderr=serial\0" \
	115	"fpga=0\0" \
5368c55d MV	116	"fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
	117	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
	118	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
	119	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
	120	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
	121	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
	122	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
	123	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
	124	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
	125	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
1f2463d7	126	"mv_version=" U_BOOT_VERSION "\0" \
5368c55d MV	127	"dhcp_client_id=" __stringify(MV_CI) "\0" \
5368c55d MV	128	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
1f2463d7 AS	129	"netretry=no\0" \
	130	"use_static_ipaddr=no\0" \
	131	"static_ipaddr=192.168.0.101\0" \
	132	"static_netmask=255.255.255.0\0" \
	133	"static_gateway=0.0.0.0\0" \
	134	"initrd_name=uInitrd.mvsmr-rfs\0" \
	135	"zcip=yes\0" \
	136	"netboot=no\0" \
	137	""
	138
1f2463d7 AS	139	/*
	140	* IPB Bus clocking configuration.
	141	*/
	142	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
	143
	144	/*
	145	* Flash configuration
	146	*/
	147	#undef CONFIG_FLASH_16BIT
	148	#define CONFIG_SYS_FLASH_CFI
	149	#define CONFIG_FLASH_CFI_DRIVER
	150	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
	151	#define CONFIG_SYS_FLASH_EMPTY_INFO
	152
	153	#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
	154	#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
	155
	156	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	157	#define CONFIG_SYS_MAX_FLASH_SECT 256
	158
	159	#define CONFIG_SYS_LOWBOOT
14d0a02a	160	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
1f2463d7 AS	161	#define CONFIG_SYS_FLASH_SIZE 0x00800000
	162
	163	/*
	164	* Environment settings
	165	*/
	166	#define CONFIG_ENV_IS_IN_FLASH
	167	#undef CONFIG_SYS_FLASH_PROTECTION
1f2463d7 AS	168	#define CONFIG_OVERWRITE_ETHADDR_ONCE
	169
	170	#define CONFIG_ENV_OFFSET 0x8000
	171	#define CONFIG_ENV_SIZE 0x2000
	172	#define CONFIG_ENV_SECT_SIZE 0x2000
	173
	174	/* used by linker script to wrap code around */
	175	#define CONFIG_SCRIPT_OFFSET 0x6000
	176	#define CONFIG_SCRIPT_SECT_SIZE 0x2000
	177
	178	/*
	179	* Memory map
	180	*/
	181	#define CONFIG_SYS_MBAR 0xF0000000
	182	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	183	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	184
	185	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982	186	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
1f2463d7	187
553f0982	188	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
25ddd1fb	189	GENERATED_GBL_DATA_SIZE)
1f2463d7 AS	190	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
1f2463d7 AS	191
14d0a02a	192	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
1f2463d7 AS	193	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	194	#define CONFIG_SYS_RAMBOOT 1
	195	#endif
	196
	197	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
	198	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
	199	#define CONFIG_SYS_MALLOC_LEN (512 << 10)
	200	#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	201
	202	/*
	203	* I2C configuration
	204	*/
	205	#define CONFIG_HARD_I2C 1
	206	#define CONFIG_SYS_I2C_MODULE 1
	207	#define CONFIG_SYS_I2C_SPEED 86000
	208	#define CONFIG_SYS_I2C_SLAVE 0x7F
	209
	210	/*
	211	* Ethernet configuration
	212	*/
	213	#define CONFIG_NET_RETRY_COUNT 5
	214
	215	#define CONFIG_MPC5xxx_FEC
	216	#define CONFIG_MPC5xxx_FEC_MII100
	217	#define CONFIG_PHY_ADDR 0x00
	218	#define CONFIG_NETDEV eth0
	219
	220	/*
	221	* Miscellaneous configurable options
	222	*/
	223	#define CONFIG_SYS_HUSH_PARSER
	224	#define CONFIG_CMDLINE_EDITING
1f2463d7	225	#undef CONFIG_SYS_LONGHELP
1f2463d7 AS	226	#ifdef CONFIG_CMD_KGDB
	227	#define CONFIG_SYS_CBSIZE 1024
	228	#else
	229	#define CONFIG_SYS_CBSIZE 256
	230	#endif
	231	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	232	#define CONFIG_SYS_MAXARGS 16
	233	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	234
	235	#define CONFIG_SYS_MEMTEST_START 0x00800000
	236	#define CONFIG_SYS_MEMTEST_END 0x02f00000
	237
1f2463d7 AS	238	/* default load address */
	239	#define CONFIG_SYS_LOAD_ADDR 0x02000000
	240	/* default location for tftp and bootm */
	241	#define CONFIG_LOADADDR 0x00200000
	242
	243	/*
	244	* Various low-level settings
	245	*/
	246	#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
	247
	248	#define CONFIG_SYS_HID0_INIT (HID0_ICE \| HID0_ICFI)
	249	#define CONFIG_SYS_HID0_FINAL HID0_ICE
	250
	251	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	252	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	253	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
	254	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	255	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	256
	257	#define CONFIG_SYS_CS_BURST 0x000000f0
	258	#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
	259
	260	#define CONFIG_SYS_RESET_ADDRESS 0x00000100
	261
	262	#undef FPGA_DEBUG
	263	#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
b03b25ca	264	#define CONFIG_FPGA
1f2463d7 AS	265	#define CONFIG_FPGA_XILINX 1
	266	#define CONFIG_FPGA_SPARTAN2 1
	267	#define CONFIG_FPGA_COUNT 1
	268
	269	#endif