[people/ms/u-boot.git] / include / configs / NC650.h

/*
 * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC852T		1
#define CONFIG_NC650		1

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/

/*
 * 10 MHz - PLL input clock
 */
#define CONFIG_8xx_OSCLK		10000000

/*
 * 50 MHz - default CPU clock
 */
#define CONFIG_8xx_CPUCLK_DEFAULT	50000000

/*
 * 15 MHz - CPU minimum clock
 */
#define CFG_8xx_CPUCLK_MIN		15000000

/*
 * 133 MHz - CPU maximum clock
 */
#define CFG_8xx_CPUCLK_MAX		133000000

#define CFG_MEASURE_CPUCLK
#define CFG_8XX_XIN			CONFIG_8xx_OSCLK

#define CONFIG_BOOTDELAY		5	/* autoboot after 5 seconds	*/
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT		\
	"\nEnter password - autoboot in %d seconds...\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR	"ids"
#define CONFIG_BOOT_RETRY_TIME		900
#define CONFIG_BOOT_RETRY_MIN		30

#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"bootp;"								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
	"bootm"

#define CONFIG_WATCHDOG			/* watchdog enabled		*/

#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
#define FEC_ENET
#define CONFIG_MII
#define CFG_DISCOVER_PHY	1


/* enable I2C and select the hardware/software driver */
#undef  CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
#define CFG_I2C_SPEED		100000	/* 100 kHz			*/
#define CFG_I2C_SLAVE		0x7f

/*
 * Software (bit-bang) I2C driver configuration
 */
#if defined(CONFIG_IDS852_REV1)

#define SCL		0x1000		/* PA 3 */
#define SDA		0x2000		/* PA 2 */

#define __I2C_DIR	immr->im_ioport.iop_padir
#define __I2C_DAT	immr->im_ioport.iop_padat
#define __I2C_PAR	immr->im_ioport.iop_papar

#elif defined(CONFIG_IDS852_REV2)

#define SCL		0x0002		/* PB 30 */
#define SDA		0x0001		/* PB 31 */

#define __I2C_PAR	immr->im_cpm.cp_pbpar
#define __I2C_DIR	immr->im_cpm.cp_pbdir
#define __I2C_DAT	immr->im_cpm.cp_pbdat

#endif

#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
			  __I2C_DIR |= (SDA|SCL);	}
#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
#define	I2C_DELAY	{ udelay(5); }
#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }

#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR		0x51


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NAND
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP


/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x00100000

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF0000000
#define CFG_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000

#define CFG_RESET_ADDRESS	0xFFF00100

#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE	TEXT_BASE
#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/


#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x00740000

#define CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
#define	CFG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*
 * NAND flash support
 */
#define CFG_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS		1

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration					11-6
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_COM00	| SCCR_DFSYNC00	| \
			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
			 SCCR_DFLCD000	| SCCR_DFALCD00)

 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER		0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: Default value of OR0 after reset */
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_MSK | OR_BI | \
				 OR_SCY_15_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)

/*
 * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
 * rev2 only uses the chipselect
 */
#define CFG_NAND_BASE		0x50000000
#define CFG_NAND_SIZE		0x04000000

#define CFG_OR_TIMING_NAND	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)

#define CFG_BR2_PRELIM  ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V  )
#define CFG_OR2_PRELIM  (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI )

/*
 * BR3 and OR3 (SDRAM)
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank		*/
#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

 /*
  * SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
  */
#define CFG_OR_TIMING_SDRAM	0x00000A00

#define CFG_OR3_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM)
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)

/*
 * BR4 and OR4 (CPLD)
 */
#define CFG_CPLD_BASE           0x80000000      /* CPLD                 */
#define CFG_CPLD_SIZE           0x10000         /* only 16 used         */

#define CFG_OR_TIMING_CPLD	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
				 OR_SCY_1_CLK)

#define CFG_BR4_PRELIM  ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CFG_OR4_PRELIM  (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD)

/*
 * BR5 and OR5 (SRAM)
 */
#define CFG_SRAM_BASE		0x60000000
#define CFG_SRAM_SIZE		0x00080000

#define CFG_OR_TIMING_SRAM	(OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
				 OR_SCY_15_CLK | OR_EHTR | OR_TRLX)

#define CFG_BR5_PRELIM  ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
#define CFG_OR5_PRELIM  (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM)

#if defined(CONFIG_CP850)
/*
 *  BR6 and OR6 (DPRAM) - only on CP850
 */
#define CFG_OR6_PRELIM          0xffff8170
#define CFG_BR6_PRELIM          0xa0000401
#define DPRAM_BASE_ADDR         0xa0000000

#define CONFIG_MISC_INIT_R      1
#endif

/*
 * 4096 Rows from SDRAM example configuration
 * 1000 factor s -> ms
 * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 * 4    Number of refresh cycles per period
 * 64   Refresh cycle in ms per number of rows
 */
#define CFG_PTA_PER_CLK		((4096 * 64 * 1000) / (4 * 64))

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA		39

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
			 MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)

/*
 * MBMR settings for NAND flash
 */

#define CFG_MBMR_NAND ( MBMR_WLFB_5X )

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */

/*
 * JFFS2 partitions
 */

/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nand0"
#define CONFIG_JFFS2_PART_SIZE		0x00400000
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=nc650-0,nand0=nc650-nand"

#define MTDPARTS_DEFAULT	"mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
					"4m(cramfs1),1m(cramfs2)," \
					"256k(u-boot),128k(env);" \
				"nc650-nand:4m(jffs1),28m(jffs2)"

#endif	/* __CONFIG_H */
Commit	Line	Data
7ca202f5	1	/*
6923565d	2	* (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
414eec35	3	* (C) Copyright 2005
7ca202f5 WD	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* board/config.h - configuration options, board specific
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36	#define CONFIG_MPC852T 1
	37	#define CONFIG_NC650 1
	38
	39	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	40	#undef CONFIG_8xx_CONS_SMC2
	41	#undef CONFIG_8xx_CONS_NONE
	42	#define CONFIG_BAUDRATE 115200
	43	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	44
	45	/*
	46	* 10 MHz - PLL input clock
	47	*/
cce625e5	48	#define CONFIG_8xx_OSCLK 10000000
7ca202f5 WD	49
	50	/*
	51	* 50 MHz - default CPU clock
	52	*/
66ca92a5	53	#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
7ca202f5 WD	54
	55	/*
	56	* 15 MHz - CPU minimum clock
	57	*/
66ca92a5	58	#define CFG_8xx_CPUCLK_MIN 15000000
7ca202f5 WD	59
	60	/*
	61	* 133 MHz - CPU maximum clock
	62	*/
66ca92a5	63	#define CFG_8xx_CPUCLK_MAX 133000000
7ca202f5 WD	64
7ca202f5 WD	65	#define CFG_MEASURE_CPUCLK
cce625e5	66	#define CFG_8XX_XIN CONFIG_8xx_OSCLK
7ca202f5	67
f2302d44	68	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
a367d426	69	#define CONFIG_AUTOBOOT_KEYED
f2302d44 SR	70	#define CONFIG_AUTOBOOT_PROMPT \
f2302d44 SR	71	"\nEnter password - autoboot in %d seconds...\n", bootdelay
a367d426	72	#define CONFIG_AUTOBOOT_DELAY_STR "ids"
	73	#define CONFIG_BOOT_RETRY_TIME 900
	74	#define CONFIG_BOOT_RETRY_MIN 30
7ca202f5	75
32bf3d14	76	#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
7ca202f5 WD	77
	78	#undef CONFIG_BOOTARGS
	79	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	80	"bootp;" \
	81	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	82	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
7ca202f5 WD	83	"bootm"
7ca202f5 WD	84
53677ef1	85	#define CONFIG_WATCHDOG /* watchdog enabled */
7ca202f5 WD	86
	87	#undef CONFIG_STATUS_LED /* Status LED disabled */
	88
7be044e4 JL	89	/*
	90	* BOOTP options
	91	*/
	92	#define CONFIG_BOOTP_SUBNETMASK
	93	#define CONFIG_BOOTP_GATEWAY
	94	#define CONFIG_BOOTP_HOSTNAME
	95	#define CONFIG_BOOTP_BOOTPATH
	96	#define CONFIG_BOOTP_BOOTFILESIZE
	97
7ca202f5 WD	98
	99	#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
	100	#define FEC_ENET
	101	#define CONFIG_MII
	102	#define CFG_DISCOVER_PHY 1
	103
	104
	105	/* enable I2C and select the hardware/software driver */
	106	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	107	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	108	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	109	#define CFG_I2C_SLAVE 0x7f
	110
	111	/*
	112	* Software (bit-bang) I2C driver configuration
	113	*/
a367d426	114	#if defined(CONFIG_IDS852_REV1)
a367d426	115
4cfaf55e WD	116	#define SCL 0x1000 /* PA 3 */
4cfaf55e WD	117	#define SDA 0x2000 /* PA 2 */
7ca202f5	118
f57f70aa WD	119	#define __I2C_DIR immr->im_ioport.iop_padir
	120	#define __I2C_DAT immr->im_ioport.iop_padat
	121	#define __I2C_PAR immr->im_ioport.iop_papar
a367d426	122
	123	#elif defined(CONFIG_IDS852_REV2)
	124
	125	#define SCL 0x0002 /* PB 30 */
	126	#define SDA 0x0001 /* PB 31 */
	127
	128	#define __I2C_PAR immr->im_cpm.cp_pbpar
	129	#define __I2C_DIR immr->im_cpm.cp_pbdir
	130	#define __I2C_DAT immr->im_cpm.cp_pbdat
	131
	132	#endif
	133
f57f70aa WD	134	#define I2C_INIT { __I2C_PAR &= ~(SDA\|SCL); \
	135	__I2C_DIR \|= (SDA\|SCL); }
	136	#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
	137	#define I2C_SDA(x) { if (x) __I2C_DAT \|= SDA; else __I2C_DAT &= ~SDA; }
	138	#define I2C_SCL(x) { if (x) __I2C_DAT \|= SCL; else __I2C_DAT &= ~SCL; }
	139	#define I2C_DELAY { udelay(5); }
	140	#define I2C_ACTIVE { __I2C_DIR \|= SDA; }
	141	#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
7ca202f5	142
4cfaf55e WD	143	#define CONFIG_RTC_PCF8563
4cfaf55e WD	144	#define CFG_I2C_RTC_ADDR 0x51
7ca202f5	145
e18a1061 JL	146
	147	/*
	148	* Command line configuration.
	149	*/
	150	#include <config_cmd_default.h>
	151
	152	#define CONFIG_CMD_ASKENV
	153	#define CONFIG_CMD_DATE
	154	#define CONFIG_CMD_DHCP
	155	#define CONFIG_CMD_I2C
	156	#define CONFIG_CMD_NAND
	157	#define CONFIG_CMD_JFFS2
	158	#define CONFIG_CMD_NFS
	159	#define CONFIG_CMD_SNTP
	160
7ca202f5 WD	161
	162	/*
	163	* Miscellaneous configurable options
	164	*/
	165	#define CFG_LONGHELP /* undef to save memory */
	166	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
e18a1061	167	#if defined(CONFIG_CMD_KGDB)
7ca202f5 WD	168	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	169	#else
	170	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	171	#endif
	172	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	173	#define CFG_MAXARGS 16 /* max number of command args */
	174	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	175
	176	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	177	#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
	178
53677ef1	179	#define CFG_LOAD_ADDR 0x00100000
7ca202f5 WD	180
	181	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	182
	183	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	184
	185	/*
	186	* Low Level Configuration Settings
	187	* (address mappings, register initial values, etc.)
	188	* You should know what you are doing if you make changes here.
	189	*/
	190	/*-----------------------------------------------------------------------
	191	* Internal Memory Mapped Register
	192	*/
	193	#define CFG_IMMR 0xF0000000
	194	#define CFG_IMMR_SIZE ((uint)(64 * 1024))
	195
	196	/*-----------------------------------------------------------------------
	197	* Definitions for initial stack pointer and data area (in DPRAM)
	198	*/
	199	#define CFG_INIT_RAM_ADDR CFG_IMMR
	200	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	201	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	202	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	203	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	204
	205	/*-----------------------------------------------------------------------
	206	* Start addresses for the final memory configuration
	207	* (Set up by the startup code)
	208	* Please note that CFG_SDRAM_BASE _must_ start at 0
	209	*/
	210	#define CFG_SDRAM_BASE 0x00000000
	211	#define CFG_FLASH_BASE 0x40000000
	212
	213	#define CFG_RESET_ADDRESS 0xFFF00100
	214
	215	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	216	#define CFG_MONITOR_BASE TEXT_BASE
	217	#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
	218
	219	/*
	220	* For booting Linux, the board info and command line data
	221	* have to be in the first 8 MB of memory, since this is
	222	* the maximum mapped by the Linux kernel during initialization.
	223	*/
	224	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	225	/*-----------------------------------------------------------------------
	226	* FLASH organization
	227	*/
	228	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	229	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	230
	231	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	232	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	233
	234
	235	#define CFG_ENV_IS_IN_FLASH 1
	236	#define CFG_ENV_OFFSET 0x00740000
	237
	238	#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
	239	#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment Sector */
	240
	241	/*-----------------------------------------------------------------------
	242	* Cache Configuration
	243	*/
244	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e18a1061	245	#if defined(CONFIG_CMD_KGDB)
7ca202f5 WD	246	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	247	#endif
	248
4cfaf55e WD	249	/*
	250	* NAND flash support
	251	*/
	252	#define CFG_MAX_NAND_DEVICE 1
4cfaf55e	253	#define NAND_MAX_CHIPS 1
4cfaf55e	254
7ca202f5 WD	255	/*-----------------------------------------------------------------------
	256	* SYPCR - System Protection Control 11-9
	257	* SYPCR can only be written once after reset!
	258	*-----------------------------------------------------------------------
	259	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	260	*/
	261	#if defined(CONFIG_WATCHDOG)
	262	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	263	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	264	#else
	265	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	266	#endif
	267
	268	/*-----------------------------------------------------------------------
	269	* SIUMCR - SIU Module Configuration 11-6
	270	*-----------------------------------------------------------------------
	271	*/
	272	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	273
	274	/*-----------------------------------------------------------------------
	275	* TBSCR - Time Base Status and Control 11-26
	276	*-----------------------------------------------------------------------
	277	* Clear Reference Interrupt Status, Timebase freezing enabled
	278	*/
	279	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
	280
	281	/*-----------------------------------------------------------------------
	282	* PISCR - Periodic Interrupt Status and Control 11-31
	283	*-----------------------------------------------------------------------
	284	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	285	*/
	286	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	287
	288	/*-----------------------------------------------------------------------
	289	* SCCR - System Clock and reset Control Register 15-27
	290	*-----------------------------------------------------------------------
	291	* Set clock output, timebase and RTC source and divider,
	292	* power management and some other internal clocks
	293	*/
	294	#define SCCR_MASK SCCR_EBDF11
	295	#define CFG_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| \
	296	SCCR_DFBRG00 \| SCCR_DFNL000 \| SCCR_DFNH000 \| \
	297	SCCR_DFLCD000 \| SCCR_DFALCD00)
	298
	299	/*-----------------------------------------------------------------------
	300	*
	301	*-----------------------------------------------------------------------
	302	*
	303	*/
	304	#define CFG_DER 0
	305
	306	/*
	307	* Init Memory Controller:
	308	*
	309	* BR0 and OR0 (FLASH)
	310	*/
	311
	312	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	313
	314	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
	315	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
	316
	317	/* FLASH timing: Default value of OR0 after reset */
	318	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_MSK \| OR_BI \| \
319	OR_SCY_15_CLK \| OR_TRLX)
320
321	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
322	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
323	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V)
324
4cfaf55e	325	/*
a367d426	326	* BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1
a367d426	327	* rev2 only uses the chipselect
4cfaf55e WD	328	*/
	329	#define CFG_NAND_BASE 0x50000000
	330	#define CFG_NAND_SIZE 0x04000000
	331
	332	#define CFG_OR_TIMING_NAND (OR_CSNT_SAM \| OR_ACS_DIV1 \| OR_BI \| \
	333	OR_SCY_15_CLK \| OR_EHTR \| OR_TRLX)
	334
c3fafecf	335	#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_MS_UPMB \| BR_V )
8f0b7cbe	336	#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) \| OR_BI )
4cfaf55e	337
7ca202f5 WD	338	/*
	339	* BR3 and OR3 (SDRAM)
	340	*/
	341	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
	342	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	343
	344	/*
	345	* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)
	346	*/
	347	#define CFG_OR_TIMING_SDRAM 0x00000A00
	348
	349	#define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM)
	350	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V)
	351
a367d426	352	/*
	353	* BR4 and OR4 (CPLD)
	354	*/
	355	#define CFG_CPLD_BASE 0x80000000 /* CPLD */
	356	#define CFG_CPLD_SIZE 0x10000 /* only 16 used */
	357
	358	#define CFG_OR_TIMING_CPLD (OR_CSNT_SAM \| OR_ACS_DIV1 \| OR_BI \| \
	359	OR_SCY_1_CLK)
	360
	361	#define CFG_BR4_PRELIM ((CFG_CPLD_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	362	#define CFG_OR4_PRELIM (((-CFG_CPLD_SIZE) & OR_AM_MSK) \| CFG_OR_TIMING_CPLD)
	363
cacfab58 WD	364	/*
	365	* BR5 and OR5 (SRAM)
	366	*/
	367	#define CFG_SRAM_BASE 0x60000000
	368	#define CFG_SRAM_SIZE 0x00080000
	369
	370	#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM \| OR_ACS_DIV1 \| OR_BI \| \
	371	OR_SCY_15_CLK \| OR_EHTR \| OR_TRLX)
	372
	373	#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
	374	#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) \| CFG_OR_TIMING_SRAM)
	375
a367d426	376	#if defined(CONFIG_CP850)
	377	/*
	378	* BR6 and OR6 (DPRAM) - only on CP850
	379	*/
	380	#define CFG_OR6_PRELIM 0xffff8170
	381	#define CFG_BR6_PRELIM 0xa0000401
	382	#define DPRAM_BASE_ADDR 0xa0000000
	383
	384	#define CONFIG_MISC_INIT_R 1
	385	#endif
cacfab58	386
7ca202f5 WD	387	/*
	388	* 4096 Rows from SDRAM example configuration
	389	* 1000 factor s -> ms
	390	* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
	391	* 4 Number of refresh cycles per period
	392	* 64 Refresh cycle in ms per number of rows
	393	*/
66ca92a5	394	#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
7ca202f5 WD	395
	396	/*
	397	* Memory Periodic Timer Prescaler
	398	*/
	399
	400	/* periodic timer for refresh */
	401	#define CFG_MAMR_PTA 39
	402
	403	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
	404	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
	405	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
	406
	407	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	408	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
	409	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	410
	411	/*
	412	* MAMR settings for SDRAM
	413	*/
	414
	415	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	416	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	417	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	418	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	419	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	420	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	421
c3fafecf WD	422	/*
	423	* MBMR settings for NAND flash
	424	*/
	425
	426	#define CFG_MBMR_NAND ( MBMR_WLFB_5X )
	427
7ca202f5 WD	428	/*
	429	* Internal Definitions
	430	*
	431	* Boot Flags
	432	*/
	433	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	434	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	435
07cc0999	436	#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
07cc0999	437	#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
7ca202f5	438
700a0c64 WD	439	/*
	440	* JFFS2 partitions
	441	*/
	442
	443	/* No command line, one static partition */
	444	#undef CONFIG_JFFS2_CMDLINE
	445	#define CONFIG_JFFS2_DEV "nand0"
	446	#define CONFIG_JFFS2_PART_SIZE 0x00400000
	447	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	448
	449	/* mtdparts command line support */
700a0c64 WD	450	#define CONFIG_JFFS2_CMDLINE
	451	#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand"
	452
	453	#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \
a367d426	454	"4m(cramfs1),1m(cramfs2)," \
	455	"256k(u-boot),128k(env);" \
	456	"nc650-nand:4m(jffs1),28m(jffs2)"
700a0c64	457
7ca202f5	458	#endif /* __CONFIG_H */