projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 04a85b3b | 1 | /* |
| cd0402a7 | 2 | * (C) Copyright 2000-2010 |
| 04a85b3b WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * Pantelis Antoniou, Intracom S.A., panto@intracom.gr | |
| 26 | * U-Boot port on NetTA4 board | |
| 27 | */ | |
| 28 | ||
| 29 | #ifndef __CONFIG_H | |
| 30 | #define __CONFIG_H | |
| 31 | ||
| c26e454d WD |
32 | #if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2 |
| 33 | #error Unsupported CONFIG_NETPHONE version | |
| 34 | #endif | |
| 35 | ||
| 04a85b3b WD |
36 | /* |
| 37 | * High Level Configuration Options | |
| 38 | * (easy to change) | |
| 39 | */ | |
| 40 | ||
| 41 | #define CONFIG_MPC870 1 /* This is a MPC885 CPU */ | |
| 42 | #define CONFIG_NETPHONE 1 /* ...on a NetPhone board */ | |
| 43 | ||
| 2ae18241 WD |
44 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 45 | ||
| 04a85b3b WD |
46 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
| 47 | #undef CONFIG_8xx_CONS_SMC2 | |
| 48 | #undef CONFIG_8xx_CONS_NONE | |
| 49 | ||
| 50 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
| 51 | ||
| 52 | /* #define CONFIG_XIN 10000000 */ | |
| 53 | #define CONFIG_XIN 50000000 | |
| 79fa88f3 WD |
54 | /* #define MPC8XX_HZ 120000000 */ |
| 55 | #define MPC8XX_HZ 66666666 | |
| 04a85b3b WD |
56 | |
| 57 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ | |
| 58 | ||
| 59 | #if 0 | |
| 60 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| 61 | #else | |
| 62 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 63 | #endif | |
| 64 | ||
| 65 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
| 66 | ||
| 67 | #define CONFIG_PREBOOT "echo;" | |
| 68 | ||
| 69 | #undef CONFIG_BOOTARGS | |
| 70 | #define CONFIG_BOOTCOMMAND \ | |
| 53677ef1 | 71 | "tftpboot; " \ |
| 79fa88f3 WD |
72 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
| 73 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
| 04a85b3b WD |
74 | "bootm" |
| 75 | ||
| 74de7aef | 76 | #define CONFIG_SOURCE |
| 04a85b3b | 77 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
| 6d0f6bcf | 78 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 04a85b3b WD |
79 | |
| 80 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 81 | ||
| 82 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
| 83 | ||
| 84 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
| 85 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
| 86 | ||
| 7be044e4 JL |
87 | /* |
| 88 | * BOOTP options | |
| 89 | */ | |
| 90 | #define CONFIG_BOOTP_SUBNETMASK | |
| 91 | #define CONFIG_BOOTP_GATEWAY | |
| 92 | #define CONFIG_BOOTP_HOSTNAME | |
| 93 | #define CONFIG_BOOTP_BOOTPATH | |
| 94 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 95 | #define CONFIG_BOOTP_NISDOMAIN | |
| 04a85b3b WD |
96 | |
| 97 | #undef CONFIG_MAC_PARTITION | |
| 98 | #undef CONFIG_DOS_PARTITION | |
| 99 | ||
| 100 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
| 101 | ||
| 04a85b3b | 102 | #define FEC_ENET 1 /* eth.c needs it that way... */ |
| 6d0f6bcf | 103 | #undef CONFIG_SYS_DISCOVER_PHY |
| 04a85b3b | 104 | #define CONFIG_MII 1 |
| 0f3ba7e9 | 105 | #define CONFIG_MII_INIT 1 |
| 04a85b3b WD |
106 | #define CONFIG_RMII 1 /* use RMII interface */ |
| 107 | ||
| 108 | #define CONFIG_ETHER_ON_FEC1 1 | |
| 53677ef1 | 109 | #define CONFIG_FEC1_PHY 8 /* phy address of FEC */ |
| 04a85b3b WD |
110 | #define CONFIG_FEC1_PHY_NORXERR 1 |
| 111 | ||
| 112 | #define CONFIG_ETHER_ON_FEC2 1 | |
| 113 | #define CONFIG_FEC2_PHY 4 | |
| 114 | #define CONFIG_FEC2_PHY_NORXERR 1 | |
| 115 | ||
| 116 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
| 117 | ||
| e18a1061 JL |
118 | |
| 119 | /* | |
| 120 | * Command line configuration. | |
| 121 | */ | |
| 122 | #include <config_cmd_default.h> | |
| 123 | ||
| e18a1061 JL |
124 | #define CONFIG_CMD_DHCP |
| 125 | #define CONFIG_CMD_PING | |
| 126 | #define CONFIG_CMD_MII | |
| 127 | #define CONFIG_CMD_CDP | |
| 128 | ||
| 04a85b3b WD |
129 | |
| 130 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 131 | #define CONFIG_MISC_INIT_R | |
| 132 | ||
| 04a85b3b WD |
133 | /* |
| 134 | * Miscellaneous configurable options | |
| 135 | */ | |
| 6d0f6bcf JCPV |
136 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 137 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 04a85b3b | 138 | |
| 6d0f6bcf | 139 | #define CONFIG_SYS_HUSH_PARSER 1 |
| 04a85b3b | 140 | |
| e18a1061 | 141 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 142 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 04a85b3b | 143 | #else |
| 6d0f6bcf | 144 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 04a85b3b | 145 | #endif |
| 6d0f6bcf JCPV |
146 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 147 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 148 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 04a85b3b | 149 | |
| 6d0f6bcf JCPV |
150 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
| 151 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
| 04a85b3b | 152 | |
| 6d0f6bcf | 153 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 04a85b3b | 154 | |
| 6d0f6bcf | 155 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 04a85b3b | 156 | |
| 04a85b3b WD |
157 | /* |
| 158 | * Low Level Configuration Settings | |
| 159 | * (address mappings, register initial values, etc.) | |
| 160 | * You should know what you are doing if you make changes here. | |
| 161 | */ | |
| 162 | /*----------------------------------------------------------------------- | |
| 163 | * Internal Memory Mapped Register | |
| 164 | */ | |
| 6d0f6bcf | 165 | #define CONFIG_SYS_IMMR 0xFF000000 |
| 04a85b3b WD |
166 | |
| 167 | /*----------------------------------------------------------------------- | |
| 168 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 169 | */ | |
| 6d0f6bcf | 170 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 553f0982 | 171 | #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
| 25ddd1fb | 172 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 173 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 04a85b3b WD |
174 | |
| 175 | /*----------------------------------------------------------------------- | |
| 176 | * Start addresses for the final memory configuration | |
| 177 | * (Set up by the startup code) | |
| 6d0f6bcf | 178 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 04a85b3b | 179 | */ |
| 6d0f6bcf JCPV |
180 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 181 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
| 04a85b3b | 182 | #if defined(DEBUG) |
| 6d0f6bcf | 183 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 04a85b3b | 184 | #else |
| 6d0f6bcf | 185 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 04a85b3b | 186 | #endif |
| 6d0f6bcf JCPV |
187 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 188 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| c26e454d | 189 | #if CONFIG_NETPHONE_VERSION == 2 |
| 6d0f6bcf | 190 | #define CONFIG_SYS_FLASH_BASE4 0x40080000 |
| c26e454d WD |
191 | #endif |
| 192 | ||
| 6d0f6bcf | 193 | #define CONFIG_SYS_RESET_ADDRESS 0x80000000 |
| 04a85b3b WD |
194 | |
| 195 | /* | |
| 196 | * For booting Linux, the board info and command line data | |
| 197 | * have to be in the first 8 MB of memory, since this is | |
| 198 | * the maximum mapped by the Linux kernel during initialization. | |
| 199 | */ | |
| 6d0f6bcf | 200 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 04a85b3b WD |
201 | |
| 202 | /*----------------------------------------------------------------------- | |
| 203 | * FLASH organization | |
| 204 | */ | |
| c26e454d | 205 | #if CONFIG_NETPHONE_VERSION == 1 |
| 6d0f6bcf | 206 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| c26e454d | 207 | #elif CONFIG_NETPHONE_VERSION == 2 |
| 6d0f6bcf | 208 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| c26e454d | 209 | #endif |
| 6d0f6bcf | 210 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ |
| 04a85b3b | 211 | |
| 6d0f6bcf JCPV |
212 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 213 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 04a85b3b | 214 | |
| 5a1aceb0 | 215 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 | 216 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 04a85b3b | 217 | |
| 6d0f6bcf | 218 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
| 0e8d1586 | 219 | #define CONFIG_ENV_SIZE 0x4000 |
| 04a85b3b | 220 | |
| 6d0f6bcf | 221 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
| 0e8d1586 | 222 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
| 04a85b3b WD |
223 | |
| 224 | /*----------------------------------------------------------------------- | |
| 225 | * Cache Configuration | |
| 226 | */ | |
| 6d0f6bcf | 227 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
| e18a1061 | 228 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 229 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
| 04a85b3b WD |
230 | #endif |
| 231 | ||
| 232 | /*----------------------------------------------------------------------- | |
| 233 | * SYPCR - System Protection Control 11-9 | |
| 234 | * SYPCR can only be written once after reset! | |
| 235 | *----------------------------------------------------------------------- | |
| 236 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| 237 | */ | |
| 238 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 239 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
| 04a85b3b WD |
240 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 241 | #else | |
| 6d0f6bcf | 242 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
| 04a85b3b WD |
243 | #endif |
| 244 | ||
| 245 | /*----------------------------------------------------------------------- | |
| 246 | * SIUMCR - SIU Module Configuration 11-6 | |
| 247 | *----------------------------------------------------------------------- | |
| 248 | * PCMCIA config., multi-function pin tri-state | |
| 249 | */ | |
| 250 | #ifndef CONFIG_CAN_DRIVER | |
| 6d0f6bcf | 251 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
| 04a85b3b | 252 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
| 6d0f6bcf | 253 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
| 04a85b3b WD |
254 | #endif /* CONFIG_CAN_DRIVER */ |
| 255 | ||
| 256 | /*----------------------------------------------------------------------- | |
| 257 | * TBSCR - Time Base Status and Control 11-26 | |
| 258 | *----------------------------------------------------------------------- | |
| 259 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
| 260 | */ | |
| 6d0f6bcf | 261 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
| 04a85b3b WD |
262 | |
| 263 | /*----------------------------------------------------------------------- | |
| 264 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
| 265 | *----------------------------------------------------------------------- | |
| 266 | */ | |
| 6d0f6bcf | 267 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
| 04a85b3b WD |
268 | |
| 269 | /*----------------------------------------------------------------------- | |
| 270 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
| 271 | *----------------------------------------------------------------------- | |
| 272 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| 273 | */ | |
| 6d0f6bcf | 274 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
| 04a85b3b WD |
275 | |
| 276 | /*----------------------------------------------------------------------- | |
| 277 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| 278 | *----------------------------------------------------------------------- | |
| 279 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| 280 | * interrupt status bit | |
| 281 | * | |
| 282 | */ | |
| 283 | ||
| 284 | #if CONFIG_XIN == 10000000 | |
| 285 | ||
| 286 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 287 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 288 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 289 | PLPRCR_TEXPS) |
| 04a85b3b | 290 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 291 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 292 | (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 293 | PLPRCR_TEXPS) |
| 04a85b3b | 294 | #elif MPC8XX_HZ == 50000000 |
| 6d0f6bcf | 295 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 296 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 297 | PLPRCR_TEXPS) |
| 04a85b3b | 298 | #elif MPC8XX_HZ == 25000000 |
| 6d0f6bcf | 299 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 300 | (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 301 | PLPRCR_TEXPS) |
| 04a85b3b | 302 | #elif MPC8XX_HZ == 40000000 |
| 6d0f6bcf | 303 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 304 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 305 | PLPRCR_TEXPS) |
| 04a85b3b | 306 | #elif MPC8XX_HZ == 75000000 |
| 6d0f6bcf | 307 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 308 | (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 309 | PLPRCR_TEXPS) |
| 04a85b3b WD |
310 | #else |
| 311 | #error unsupported CPU freq for XIN = 10MHz | |
| 312 | #endif | |
| 313 | ||
| 314 | #elif CONFIG_XIN == 50000000 | |
| 315 | ||
| 316 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 317 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 318 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 319 | PLPRCR_TEXPS) |
| 04a85b3b | 320 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 321 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 322 | (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 323 | PLPRCR_TEXPS) |
| c26e454d | 324 | #elif MPC8XX_HZ == 66666666 |
| 6d0f6bcf | 325 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| c26e454d | 326 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 327 | PLPRCR_TEXPS) |
| 04a85b3b WD |
328 | #else |
| 329 | #error unsupported CPU freq for XIN = 50MHz | |
| 330 | #endif | |
| 331 | ||
| 332 | #else | |
| 333 | ||
| 334 | #error unsupported XIN freq | |
| 335 | #endif | |
| 336 | ||
| 337 | ||
| 338 | /* | |
| 339 | *----------------------------------------------------------------------- | |
| 340 | * SCCR - System Clock and reset Control Register 15-27 | |
| 341 | *----------------------------------------------------------------------- | |
| 342 | * Set clock output, timebase and RTC source and divider, | |
| 343 | * power management and some other internal clocks | |
| 79fa88f3 WD |
344 | * |
| 345 | * Note: When TBS == 0 the timebase is independent of current cpu clock. | |
| 04a85b3b WD |
346 | */ |
| 347 | ||
| 348 | #define SCCR_MASK SCCR_EBDF11 | |
| 349 | #if MPC8XX_HZ > 66666666 | |
| 6d0f6bcf | 350 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
| 04a85b3b WD |
351 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| 352 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
| 353 | SCCR_DFALCD00 | SCCR_EBDF01) | |
| 354 | #else | |
| 6d0f6bcf | 355 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
| 04a85b3b WD |
356 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| 357 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
| 358 | SCCR_DFALCD00) | |
| 359 | #endif | |
| 360 | ||
| 361 | /*----------------------------------------------------------------------- | |
| 362 | * | |
| 363 | *----------------------------------------------------------------------- | |
| 364 | * | |
| 365 | */ | |
| 6d0f6bcf JCPV |
366 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
| 367 | #define CONFIG_SYS_DER 0 | |
| 04a85b3b WD |
368 | |
| 369 | /* | |
| 370 | * Init Memory Controller: | |
| 371 | * | |
| 372 | * BR0/1 and OR0/1 (FLASH) | |
| 373 | */ | |
| 374 | ||
| 375 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| 376 | ||
| 377 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
| 378 | * restrict access enough to keep SRAM working (if any) | |
| 379 | * but not too much to meddle with FLASH accesses | |
| 380 | */ | |
| 6d0f6bcf JCPV |
381 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 382 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
| 04a85b3b WD |
383 | |
| 384 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
| 6d0f6bcf | 385 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
| 04a85b3b | 386 | |
| 6d0f6bcf JCPV |
387 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 388 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| 389 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
| 04a85b3b | 390 | |
| c26e454d WD |
391 | #if CONFIG_NETPHONE_VERSION == 2 |
| 392 | ||
| 393 | #define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */ | |
| 394 | ||
| 6d0f6bcf JCPV |
395 | #define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 396 | #define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| 397 | #define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
| c26e454d WD |
398 | |
| 399 | #endif | |
| 400 | ||
| 04a85b3b WD |
401 | /* |
| 402 | * BR3 and OR3 (SDRAM) | |
| 403 | * | |
| 404 | */ | |
| 405 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
| 406 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ | |
| 407 | ||
| 408 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
| 6d0f6bcf | 409 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
| 04a85b3b | 410 | |
| 6d0f6bcf JCPV |
411 | #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
| 412 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) | |
| 04a85b3b WD |
413 | |
| 414 | /* | |
| 415 | * Memory Periodic Timer Prescaler | |
| 416 | */ | |
| 417 | ||
| 418 | /* | |
| 419 | * Memory Periodic Timer Prescaler | |
| 420 | * | |
| 421 | * The Divider for PTA (refresh timer) configuration is based on an | |
| 422 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
| 423 | * the number of chip selects (NCS) and the actually needed refresh | |
| 424 | * rate is done by setting MPTPR. | |
| 425 | * | |
| 426 | * PTA is calculated from | |
| 427 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
| 428 | * | |
| 429 | * gclk CPU clock (not bus clock!) | |
| 430 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 431 | * | |
| 432 | * 4096 Rows from SDRAM example configuration | |
| 433 | * 1000 factor s -> ms | |
| 434 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
| 435 | * 4 Number of refresh cycles per period | |
| 436 | * 64 Refresh cycle in ms per number of rows | |
| 437 | * -------------------------------------------- | |
| 438 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
| 439 | * | |
| 440 | * 50 MHz => 50.000.000 / Divider = 98 | |
| 441 | * 66 Mhz => 66.000.000 / Divider = 129 | |
| 442 | * 80 Mhz => 80.000.000 / Divider = 156 | |
| 443 | */ | |
| 444 | ||
| 6d0f6bcf | 445 | #define CONFIG_SYS_MAMR_PTA 234 |
| 04a85b3b WD |
446 | |
| 447 | /* | |
| 448 | * For 16 MBit, refresh rates could be 31.3 us | |
| 449 | * (= 64 ms / 2K = 125 / quad bursts). | |
| 450 | * For a simpler initialization, 15.6 us is used instead. | |
| 451 | * | |
| 6d0f6bcf JCPV |
452 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
| 453 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
| 04a85b3b | 454 | */ |
| 6d0f6bcf JCPV |
455 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 456 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
| 04a85b3b WD |
457 | |
| 458 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
| 6d0f6bcf JCPV |
459 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 460 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
| 04a85b3b WD |
461 | |
| 462 | /* | |
| 463 | * MAMR settings for SDRAM | |
| 464 | */ | |
| 465 | ||
| 466 | /* 8 column SDRAM */ | |
| 6d0f6bcf | 467 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 04a85b3b WD |
468 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 469 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 470 | ||
| 471 | /* 9 column SDRAM */ | |
| 6d0f6bcf | 472 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 04a85b3b WD |
473 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 474 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 475 | ||
| 04a85b3b WD |
476 | #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
| 477 | ||
| 478 | /****************************************************************/ | |
| 479 | ||
| 480 | #define DSP_SIZE 0x00010000 /* 64K */ | |
| 481 | #define NAND_SIZE 0x00010000 /* 64K */ | |
| 04a85b3b WD |
482 | |
| 483 | #define DSP_BASE 0xF1000000 | |
| 484 | #define NAND_BASE 0xF1010000 | |
| 04a85b3b | 485 | |
| 04a85b3b WD |
486 | /*****************************************************************************/ |
| 487 | ||
| 6d0f6bcf | 488 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
| 79fa88f3 WD |
489 | |
| 490 | /*****************************************************************************/ | |
| 491 | ||
| c26e454d | 492 | #if CONFIG_NETPHONE_VERSION == 1 |
| 04a85b3b | 493 | #define STATUS_LED_BIT 0x00000008 /* bit 28 */ |
| c26e454d WD |
494 | #elif CONFIG_NETPHONE_VERSION == 2 |
| 495 | #define STATUS_LED_BIT 0x00000080 /* bit 24 */ | |
| 496 | #endif | |
| 497 | ||
| 6d0f6bcf | 498 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
| 04a85b3b WD |
499 | #define STATUS_LED_STATE STATUS_LED_BLINKING |
| 500 | ||
| 501 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
| 502 | #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ | |
| 503 | ||
| 504 | #ifndef __ASSEMBLY__ | |
| 505 | ||
| 506 | /* LEDs */ | |
| 507 | ||
| 508 | /* led_id_t is unsigned int mask */ | |
| 509 | typedef unsigned int led_id_t; | |
| 510 | ||
| 511 | #define __led_toggle(_msk) \ | |
| 512 | do { \ | |
| 6d0f6bcf | 513 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \ |
| 04a85b3b WD |
514 | } while(0) |
| 515 | ||
| 516 | #define __led_set(_msk, _st) \ | |
| 517 | do { \ | |
| 518 | if ((_st)) \ | |
| 6d0f6bcf | 519 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \ |
| 04a85b3b | 520 | else \ |
| 6d0f6bcf | 521 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \ |
| 04a85b3b WD |
522 | } while(0) |
| 523 | ||
| 524 | #define __led_init(msk, st) __led_set(msk, st) | |
| 525 | ||
| 526 | #endif | |
| 527 | ||
| 528 | /*********************************************************************************************************** | |
| 529 | ||
| c26e454d WD |
530 | ---------------------------------------------------------------------------------------------- |
| 531 | ||
| 532 | (V1) version 1 of the board | |
| 533 | (V2) version 2 of the board | |
| 534 | ||
| 535 | ---------------------------------------------------------------------------------------------- | |
| 536 | ||
| 04a85b3b WD |
537 | Pin definitions: |
| 538 | ||
| 539 | +------+----------------+--------+------------------------------------------------------------ | |
| 540 | | # | Name | Type | Comment | |
| 541 | +------+----------------+--------+------------------------------------------------------------ | |
| 542 | | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select | |
| 543 | | PA7 | DSP_INT | Output | DSP interrupt | |
| 544 | | PA10 | DSP_RESET | Output | DSP reset | |
| 545 | | PA14 | USBOE | Output | USB (1) | |
| 546 | | PA15 | USBRXD | Output | USB (1) | |
| 547 | | PB19 | BT_RTS | Output | Bluetooth (0) | |
| 548 | | PB23 | BT_CTS | Output | Bluetooth (0) | |
| 549 | | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select | |
| 550 | | PB27 | SPICS_DISP | Output | Display chip select | |
| 551 | | PB28 | SPI_RXD_3V | Input | SPI Data Rx | |
| 552 | | PB29 | SPI_TXD | Output | SPI Data Tx | |
| 553 | | PB30 | SPI_CLK | Output | SPI Clock | |
| 554 | | PC10 | DISPA0 | Output | Display A0 | |
| 555 | | PC11 | BACKLIGHT | Output | Display backlit | |
| c26e454d WD |
556 | | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD |
| 557 | | | IO_RESET | Output | (V2) General I/O reset | |
| 558 | | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1) | |
| 559 | | | HOOK | Input | (V2) Hook input interrupt | |
| 560 | | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK | |
| 561 | | | F_RY_BY | Input | (V2) NAND F_RY_BY | |
| 04a85b3b WD |
562 | | PE17 | F_ALE | Output | NAND F_ALE |
| 563 | | PE18 | F_CLE | Output | NAND F_CLE | |
| 564 | | PE20 | F_CE | Output | NAND F_CE | |
| c26e454d WD |
565 | | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select |
| 566 | | | LED | Output | (V2) LED | |
| 04a85b3b | 567 | | PE27 | SPICS_ER | Output | External serial register CS |
| c26e454d WD |
568 | | PE28 | LEDIO1 | Output | (V1) LED |
| 569 | | | BKBR1 | Input | (V2) Keyboard input scan | |
| 570 | | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2) | |
| 571 | | | BKBR2 | Input | (V2) Keyboard input scan | |
| 572 | | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2) | |
| 573 | | | BKBR3 | Input | (V2) Keyboard input scan | |
| 574 | | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY | |
| 575 | | | BKBR4 | Input | (V2) Keyboard input scan | |
| 04a85b3b WD |
576 | +------+----------------+--------+--------------------------------------------------- |
| 577 | ||
| c26e454d WD |
578 | ---------------------------------------------------------------------------------------------- |
| 579 | ||
| 580 | Serial register input: | |
| 581 | ||
| 582 | +------+----------------+------------------------------------------------------------ | |
| 583 | | # | Name | Comment | |
| 584 | +------+----------------+------------------------------------------------------------ | |
| 6e592385 WD |
585 | | 0 | BKBR1 | (V1) Keyboard input scan |
| 586 | | 1 | BKBR3 | (V1) Keyboard input scan | |
| 587 | | 2 | BKBR4 | (V1) Keyboard input scan | |
| 588 | | 3 | BKBR2 | (V1) Keyboard input scan | |
| 589 | | 4 | HOOK | (V1) Hook switch | |
| c26e454d WD |
590 | | 5 | BT_LINK | (V1) Bluetooth link status |
| 591 | | 6 | HOST_WAKE | (V1) Bluetooth host wake up | |
| 592 | | 7 | OK_ETH | (V1) Cisco inline power OK status | |
| 593 | +------+----------------+------------------------------------------------------------ | |
| 594 | ||
| 595 | ---------------------------------------------------------------------------------------------- | |
| 596 | ||
| 597 | Serial register output: | |
| 598 | ||
| 599 | +------+----------------+------------------------------------------------------------ | |
| 600 | | # | Name | Comment | |
| 601 | +------+----------------+------------------------------------------------------------ | |
| 6e592385 WD |
602 | | 0 | KEY1 | Keyboard output scan |
| 603 | | 1 | KEY2 | Keyboard output scan | |
| 604 | | 2 | KEY3 | Keyboard output scan | |
| 605 | | 3 | KEY4 | Keyboard output scan | |
| 606 | | 4 | KEY5 | Keyboard output scan | |
| 607 | | 5 | KEY6 | Keyboard output scan | |
| 608 | | 6 | KEY7 | Keyboard output scan | |
| c26e454d WD |
609 | | 7 | BT_WAKE | Bluetooth wake up |
| 610 | +------+----------------+------------------------------------------------------------ | |
| 611 | ||
| 612 | ---------------------------------------------------------------------------------------------- | |
| 613 | ||
| 04a85b3b WD |
614 | Chip selects: |
| 615 | ||
| 616 | +------+----------------+------------------------------------------------------------ | |
| 617 | | # | Name | Comment | |
| 618 | +------+----------------+------------------------------------------------------------ | |
| 619 | | CS0 | CS0 | Boot flash | |
| 620 | | CS1 | CS_FLASH | NAND flash | |
| 621 | | CS2 | CS_DSP | DSP | |
| 622 | | CS3 | DCS_DRAM | DRAM | |
| c26e454d | 623 | | CS4 | CS_FLASH2 | (V2) 2nd flash |
| 04a85b3b WD |
624 | +------+----------------+------------------------------------------------------------ |
| 625 | ||
| c26e454d WD |
626 | ---------------------------------------------------------------------------------------------- |
| 627 | ||
| 04a85b3b WD |
628 | Interrupts: |
| 629 | ||
| 630 | +------+----------------+------------------------------------------------------------ | |
| 631 | | # | Name | Comment | |
| 632 | +------+----------------+------------------------------------------------------------ | |
| 633 | | IRQ1 | IRQ_DSP | DSP interrupt | |
| 634 | | IRQ3 | S_INTER | DUSLIC ??? | |
| 635 | | IRQ4 | F_RY_BY | NAND | |
| 636 | | IRQ7 | IRQ_MAX | MAX 3100 interrupt | |
| 637 | +------+----------------+------------------------------------------------------------ | |
| 638 | ||
| c26e454d WD |
639 | ---------------------------------------------------------------------------------------------- |
| 640 | ||
| 04a85b3b WD |
641 | Interrupts on PCMCIA pins: |
| 642 | ||
| 643 | +------+----------------+------------------------------------------------------------ | |
| 644 | | # | Name | Comment | |
| 645 | +------+----------------+------------------------------------------------------------ | |
| 646 | | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface | |
| 647 | | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface | |
| 648 | | IP_A2| RMII1_MDINT | PHY interrupt for #1 | |
| 649 | | IP_A3| RMII2_MDINT | PHY interrupt for #2 | |
| c26e454d WD |
650 | | IP_A5| HOST_WAKE | (V2) Bluetooth host wake |
| 651 | | IP_A6| OK_ETH | (V2) Cisco inline power OK | |
| 04a85b3b WD |
652 | +------+----------------+------------------------------------------------------------ |
| 653 | ||
| 654 | *************************************************************************************************/ | |
| 655 | ||
| 656 | #define CONFIG_SED156X 1 /* use SED156X */ | |
| 657 | #define CONFIG_SED156X_PG12864Q 1 /* type of display used */ | |
| 658 | ||
| 659 | /* serial interfacing macros */ | |
| 660 | ||
| 6d0f6bcf | 661 | #define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
| 04a85b3b WD |
662 | #define SED156X_SPI_RXD_MASK 0x00000008 |
| 663 | ||
| 6d0f6bcf | 664 | #define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
| 04a85b3b WD |
665 | #define SED156X_SPI_TXD_MASK 0x00000004 |
| 666 | ||
| 6d0f6bcf | 667 | #define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
| 04a85b3b WD |
668 | #define SED156X_SPI_CLK_MASK 0x00000002 |
| 669 | ||
| 6d0f6bcf | 670 | #define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |
| 04a85b3b WD |
671 | #define SED156X_CS_MASK 0x00000010 |
| 672 | ||
| 6d0f6bcf | 673 | #define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |
| 04a85b3b WD |
674 | #define SED156X_A0_MASK 0x0020 |
| 675 | ||
| 676 | /*************************************************************************************************/ | |
| 677 | ||
| 6d0f6bcf JCPV |
678 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
| 679 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 | |
| 680 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 | |
| 04a85b3b WD |
681 | |
| 682 | /*************************************************************************************************/ | |
| 683 | ||
| 684 | /* use board specific hardware */ | |
| 685 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 686 | #define CONFIG_HW_WATCHDOG | |
| 687 | #define CONFIG_SHOW_ACTIVITY | |
| 688 | ||
| 689 | /*************************************************************************************************/ | |
| 690 | ||
| 691 | /* phone console configuration */ | |
| 692 | ||
| 6d0f6bcf | 693 | #define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200) /* poll every 5ms */ |
| 04a85b3b WD |
694 | |
| 695 | /*************************************************************************************************/ | |
| 696 | ||
| 697 | #define CONFIG_CDP_DEVICE_ID 20 | |
| 698 | #define CONFIG_CDP_DEVICE_ID_PREFIX "NP" /* netphone */ | |
| 699 | #define CONFIG_CDP_PORT_ID "eth%d" | |
| 700 | #define CONFIG_CDP_CAPABILITIES 0x00000010 | |
| 561858ee | 701 | #define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME |
| 04a85b3b WD |
702 | #define CONFIG_CDP_PLATFORM "Intracom NetPhone" |
| 703 | #define CONFIG_CDP_TRIGGER 0x20020001 | |
| 704 | #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ | |
| 705 | #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone */ | |
| 706 | ||
| 707 | /*************************************************************************************************/ | |
| 708 | ||
| 709 | #define CONFIG_AUTO_COMPLETE 1 | |
| 710 | ||
| 711 | /*************************************************************************************************/ | |
| 712 | ||
| c26e454d WD |
713 | #define CONFIG_CRC32_VERIFY 1 |
| 714 | ||
| 715 | /*************************************************************************************************/ | |
| 716 | ||
| 717 | #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 | |
| 718 | ||
| 719 | /*************************************************************************************************/ | |
| 04a85b3b | 720 | #endif /* __CONFIG_H */ |