projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 04a85b3b WD |
1 | /* |
| 2 | * (C) Copyright 2000-2004 | |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * Pantelis Antoniou, Intracom S.A., panto@intracom.gr | |
| 26 | * U-Boot port on NetTA4 board | |
| 27 | */ | |
| 28 | ||
| 29 | #ifndef __CONFIG_H | |
| 30 | #define __CONFIG_H | |
| 31 | ||
| 32 | /* | |
| 33 | * High Level Configuration Options | |
| 34 | * (easy to change) | |
| 35 | */ | |
| 36 | ||
| 37 | #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ | |
| 38 | #define CONFIG_NETTA 1 /* ...on a NetTA board */ | |
| 39 | ||
| 40 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
| 41 | #undef CONFIG_8xx_CONS_SMC2 | |
| 42 | #undef CONFIG_8xx_CONS_NONE | |
| 43 | ||
| 44 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ | |
| 45 | ||
| 46 | /* #define CONFIG_XIN 10000000 */ | |
| 47 | #define CONFIG_XIN 50000000 | |
| 48 | #define MPC8XX_HZ 120000000 | |
| 49 | /* #define MPC8XX_HZ 100000000 */ | |
| 50 | /* #define MPC8XX_HZ 50000000 */ | |
| 51 | /* #define MPC8XX_HZ 80000000 */ | |
| 52 | ||
| 53 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ | |
| 54 | ||
| 55 | #if 0 | |
| 56 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
| 57 | #else | |
| 58 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
| 59 | #endif | |
| 60 | ||
| 61 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
| 62 | ||
| 32bf3d14 | 63 | #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" |
| 04a85b3b WD |
64 | |
| 65 | #undef CONFIG_BOOTARGS | |
| 66 | #define CONFIG_BOOTCOMMAND \ | |
| 53677ef1 | 67 | "tftpboot; " \ |
| 79fa88f3 WD |
68 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
| 69 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
| 04a85b3b WD |
70 | "bootm" |
| 71 | ||
| 72 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
| 6d0f6bcf | 73 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 04a85b3b WD |
74 | |
| 75 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 76 | #define CONFIG_HW_WATCHDOG | |
| 77 | ||
| 78 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
| 79 | ||
| 7be044e4 JL |
80 | /* |
| 81 | * BOOTP options | |
| 82 | */ | |
| 83 | #define CONFIG_BOOTP_SUBNETMASK | |
| 84 | #define CONFIG_BOOTP_GATEWAY | |
| 85 | #define CONFIG_BOOTP_HOSTNAME | |
| 86 | #define CONFIG_BOOTP_BOOTPATH | |
| 87 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 88 | #define CONFIG_BOOTP_NISDOMAIN | |
| 89 | ||
| 04a85b3b WD |
90 | |
| 91 | #undef CONFIG_MAC_PARTITION | |
| 92 | #undef CONFIG_DOS_PARTITION | |
| 93 | ||
| 94 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
| 95 | ||
| 53677ef1 | 96 | #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ |
| 04a85b3b | 97 | #define FEC_ENET 1 /* eth.c needs it that way... */ |
| 6d0f6bcf | 98 | #undef CONFIG_SYS_DISCOVER_PHY /* do not discover phys */ |
| 04a85b3b | 99 | #define CONFIG_MII 1 |
| 0f3ba7e9 | 100 | #define CONFIG_MII_INIT 1 |
| 04a85b3b WD |
101 | #define CONFIG_RMII 1 /* use RMII interface */ |
| 102 | ||
| 103 | #if defined(CONFIG_NETTA_ISDN) | |
| 104 | #define CONFIG_ETHER_ON_FEC1 1 | |
| 53677ef1 | 105 | #define CONFIG_FEC1_PHY 1 /* phy address of FEC1 */ |
| 04a85b3b WD |
106 | #define CONFIG_FEC1_PHY_NORXERR 1 |
| 107 | #undef CONFIG_ETHER_ON_FEC2 | |
| 108 | #else | |
| 109 | #define CONFIG_ETHER_ON_FEC1 1 | |
| 53677ef1 | 110 | #define CONFIG_FEC1_PHY 8 /* phy address of FEC1 */ |
| 04a85b3b WD |
111 | #define CONFIG_FEC1_PHY_NORXERR 1 |
| 112 | #define CONFIG_ETHER_ON_FEC2 1 | |
| 53677ef1 | 113 | #define CONFIG_FEC2_PHY 1 /* phy address of FEC2 */ |
| 04a85b3b WD |
114 | #define CONFIG_FEC2_PHY_NORXERR 1 |
| 115 | #endif | |
| 116 | ||
| 117 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
| 118 | ||
| 119 | /* POST support */ | |
| 6d0f6bcf JCPV |
120 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
| 121 | CONFIG_SYS_POST_CODEC | \ | |
| 122 | CONFIG_SYS_POST_DSP ) | |
| 04a85b3b | 123 | |
| e18a1061 JL |
124 | |
| 125 | /* | |
| 126 | * Command line configuration. | |
| 127 | */ | |
| 128 | #include <config_cmd_default.h> | |
| 129 | ||
| 130 | #define CONFIG_CMD_CDP | |
| 131 | #define CONFIG_CMD_DHCP | |
| 132 | #define CONFIG_CMD_DIAG | |
| 133 | #define CONFIG_CMD_FAT | |
| 134 | #define CONFIG_CMD_IDE | |
| 135 | #define CONFIG_CMD_JFFS2 | |
| 136 | #define CONFIG_CMD_MII | |
| e18a1061 JL |
137 | #define CONFIG_CMD_NFS |
| 138 | #define CONFIG_CMD_PCMCIA | |
| 139 | #define CONFIG_CMD_PING | |
| 140 | ||
| 04a85b3b WD |
141 | |
| 142 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 143 | #define CONFIG_MISC_INIT_R | |
| 144 | ||
| 04a85b3b WD |
145 | /* |
| 146 | * Miscellaneous configurable options | |
| 147 | */ | |
| 6d0f6bcf JCPV |
148 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 149 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 04a85b3b | 150 | |
| 6d0f6bcf JCPV |
151 | #define CONFIG_SYS_HUSH_PARSER 1 |
| 152 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 04a85b3b | 153 | |
| e18a1061 | 154 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 155 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 04a85b3b | 156 | #else |
| 6d0f6bcf | 157 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 04a85b3b | 158 | #endif |
| 6d0f6bcf JCPV |
159 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 160 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 161 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 04a85b3b | 162 | |
| 6d0f6bcf JCPV |
163 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
| 164 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
| 04a85b3b | 165 | |
| 6d0f6bcf | 166 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
| 04a85b3b | 167 | |
| 6d0f6bcf | 168 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 04a85b3b | 169 | |
| 6d0f6bcf | 170 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 04a85b3b WD |
171 | |
| 172 | /* | |
| 173 | * Low Level Configuration Settings | |
| 174 | * (address mappings, register initial values, etc.) | |
| 175 | * You should know what you are doing if you make changes here. | |
| 176 | */ | |
| 177 | /*----------------------------------------------------------------------- | |
| 178 | * Internal Memory Mapped Register | |
| 179 | */ | |
| 6d0f6bcf | 180 | #define CONFIG_SYS_IMMR 0xFF000000 |
| 04a85b3b WD |
181 | |
| 182 | /*----------------------------------------------------------------------- | |
| 183 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 184 | */ | |
| 6d0f6bcf JCPV |
185 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
| 186 | #define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ | |
| 187 | #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
| 188 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 189 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 04a85b3b WD |
190 | |
| 191 | /*----------------------------------------------------------------------- | |
| 192 | * Start addresses for the final memory configuration | |
| 193 | * (Set up by the startup code) | |
| 6d0f6bcf | 194 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 04a85b3b | 195 | */ |
| 6d0f6bcf JCPV |
196 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 197 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
| 04a85b3b | 198 | #if defined(DEBUG) |
| 6d0f6bcf | 199 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 04a85b3b | 200 | #else |
| 6d0f6bcf | 201 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
| 04a85b3b | 202 | #endif |
| 6d0f6bcf JCPV |
203 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 204 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 04a85b3b WD |
205 | |
| 206 | /* | |
| 207 | * For booting Linux, the board info and command line data | |
| 208 | * have to be in the first 8 MB of memory, since this is | |
| 209 | * the maximum mapped by the Linux kernel during initialization. | |
| 210 | */ | |
| 6d0f6bcf | 211 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 04a85b3b WD |
212 | |
| 213 | /*----------------------------------------------------------------------- | |
| 214 | * FLASH organization | |
| 215 | */ | |
| 6d0f6bcf JCPV |
216 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 217 | #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ | |
| 04a85b3b | 218 | |
| 6d0f6bcf JCPV |
219 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 220 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 04a85b3b | 221 | |
| 5a1aceb0 | 222 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 0e8d1586 | 223 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 04a85b3b | 224 | |
| 6d0f6bcf | 225 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000) |
| 0e8d1586 JCPV |
226 | #define CONFIG_ENV_OFFSET 0 |
| 227 | #define CONFIG_ENV_SIZE 0x4000 | |
| 04a85b3b | 228 | |
| 6d0f6bcf | 229 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000) |
| 0e8d1586 JCPV |
230 | #define CONFIG_ENV_OFFSET_REDUND 0 |
| 231 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
| 04a85b3b WD |
232 | |
| 233 | /*----------------------------------------------------------------------- | |
| 234 | * Cache Configuration | |
| 235 | */ | |
| 6d0f6bcf | 236 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
| e18a1061 | 237 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 238 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
| 04a85b3b WD |
239 | #endif |
| 240 | ||
| 241 | /*----------------------------------------------------------------------- | |
| 242 | * SYPCR - System Protection Control 11-9 | |
| 243 | * SYPCR can only be written once after reset! | |
| 244 | *----------------------------------------------------------------------- | |
| 245 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
| 246 | */ | |
| 247 | #if defined(CONFIG_WATCHDOG) | |
| 6d0f6bcf | 248 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
| 04a85b3b WD |
249 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 250 | #else | |
| 6d0f6bcf | 251 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
| 04a85b3b WD |
252 | #endif |
| 253 | ||
| 254 | /*----------------------------------------------------------------------- | |
| 255 | * SIUMCR - SIU Module Configuration 11-6 | |
| 256 | *----------------------------------------------------------------------- | |
| 257 | * PCMCIA config., multi-function pin tri-state | |
| 258 | */ | |
| 259 | #ifndef CONFIG_CAN_DRIVER | |
| 6d0f6bcf | 260 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
| 04a85b3b | 261 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
| 6d0f6bcf | 262 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC) |
| 04a85b3b WD |
263 | #endif /* CONFIG_CAN_DRIVER */ |
| 264 | ||
| 265 | /*----------------------------------------------------------------------- | |
| 266 | * TBSCR - Time Base Status and Control 11-26 | |
| 267 | *----------------------------------------------------------------------- | |
| 268 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
| 269 | */ | |
| 6d0f6bcf | 270 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
| 04a85b3b WD |
271 | |
| 272 | /*----------------------------------------------------------------------- | |
| 273 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
| 274 | *----------------------------------------------------------------------- | |
| 275 | */ | |
| 6d0f6bcf | 276 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
| 04a85b3b WD |
277 | |
| 278 | /*----------------------------------------------------------------------- | |
| 279 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
| 280 | *----------------------------------------------------------------------- | |
| 281 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
| 282 | */ | |
| 6d0f6bcf | 283 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
| 04a85b3b WD |
284 | |
| 285 | /*----------------------------------------------------------------------- | |
| 286 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
| 287 | *----------------------------------------------------------------------- | |
| 288 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
| 289 | * interrupt status bit | |
| 290 | * | |
| 291 | */ | |
| 292 | ||
| 293 | #if CONFIG_XIN == 10000000 | |
| 294 | ||
| 295 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 296 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 297 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 298 | PLPRCR_TEXPS) |
| 04a85b3b | 299 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 300 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 301 | (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 302 | PLPRCR_TEXPS) |
| 04a85b3b | 303 | #elif MPC8XX_HZ == 50000000 |
| 6d0f6bcf | 304 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 305 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 306 | PLPRCR_TEXPS) |
| 04a85b3b | 307 | #elif MPC8XX_HZ == 25000000 |
| 6d0f6bcf | 308 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 309 | (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 310 | PLPRCR_TEXPS) |
| 04a85b3b | 311 | #elif MPC8XX_HZ == 40000000 |
| 6d0f6bcf | 312 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 313 | (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 314 | PLPRCR_TEXPS) |
| 04a85b3b | 315 | #elif MPC8XX_HZ == 75000000 |
| 6d0f6bcf | 316 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 317 | (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 318 | PLPRCR_TEXPS) |
| 04a85b3b WD |
319 | #else |
| 320 | #error unsupported CPU freq for XIN = 10MHz | |
| 321 | #endif | |
| 322 | ||
| 323 | #elif CONFIG_XIN == 50000000 | |
| 324 | ||
| 325 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 326 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 327 | (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 328 | PLPRCR_TEXPS) |
| 04a85b3b | 329 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 330 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 331 | (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 332 | PLPRCR_TEXPS) |
| 04a85b3b | 333 | #elif MPC8XX_HZ == 80000000 |
| 6d0f6bcf | 334 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 335 | (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 336 | PLPRCR_TEXPS) |
| 04a85b3b | 337 | #elif MPC8XX_HZ == 50000000 |
| 6d0f6bcf | 338 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
| 04a85b3b | 339 | (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \ |
| 53677ef1 | 340 | PLPRCR_TEXPS) |
| 04a85b3b WD |
341 | #else |
| 342 | #error unsupported CPU freq for XIN = 50MHz | |
| 343 | #endif | |
| 344 | ||
| 345 | #else | |
| 346 | ||
| 347 | #error unsupported XIN freq | |
| 348 | #endif | |
| 349 | ||
| 350 | ||
| 351 | /* | |
| 352 | *----------------------------------------------------------------------- | |
| 353 | * SCCR - System Clock and reset Control Register 15-27 | |
| 354 | *----------------------------------------------------------------------- | |
| 355 | * Set clock output, timebase and RTC source and divider, | |
| 356 | * power management and some other internal clocks | |
| 79fa88f3 WD |
357 | * |
| 358 | * Note: When TBS == 0 the timebase is independent of current cpu clock. | |
| 04a85b3b WD |
359 | */ |
| 360 | ||
| 361 | #define SCCR_MASK SCCR_EBDF11 | |
| 362 | #if MPC8XX_HZ > 66666666 | |
| 6d0f6bcf | 363 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
| 04a85b3b | 364 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| 79fa88f3 | 365 | SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 04a85b3b WD |
366 | SCCR_DFALCD00 | SCCR_EBDF01) |
| 367 | #else | |
| 6d0f6bcf | 368 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
| 04a85b3b | 369 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
| 79fa88f3 | 370 | SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 04a85b3b WD |
371 | SCCR_DFALCD00) |
| 372 | #endif | |
| 373 | ||
| 374 | /*----------------------------------------------------------------------- | |
| 375 | * | |
| 376 | *----------------------------------------------------------------------- | |
| 377 | * | |
| 378 | */ | |
| 6d0f6bcf JCPV |
379 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
| 380 | #define CONFIG_SYS_DER 0 | |
| 04a85b3b WD |
381 | |
| 382 | /* | |
| 383 | * Init Memory Controller: | |
| 384 | * | |
| 385 | * BR0/1 and OR0/1 (FLASH) | |
| 386 | */ | |
| 387 | ||
| 388 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
| 389 | ||
| 390 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
| 391 | * restrict access enough to keep SRAM working (if any) | |
| 392 | * but not too much to meddle with FLASH accesses | |
| 393 | */ | |
| 6d0f6bcf JCPV |
394 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 395 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
| 04a85b3b WD |
396 | |
| 397 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
| 6d0f6bcf | 398 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
| 04a85b3b | 399 | |
| 6d0f6bcf JCPV |
400 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 401 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
| 402 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) | |
| 04a85b3b WD |
403 | |
| 404 | /* | |
| 405 | * BR3 and OR3 (SDRAM) | |
| 406 | * | |
| 407 | */ | |
| 408 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
| 409 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ | |
| 410 | ||
| 411 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
| 6d0f6bcf | 412 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
| 04a85b3b | 413 | |
| 6d0f6bcf JCPV |
414 | #define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
| 415 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V) | |
| 04a85b3b WD |
416 | |
| 417 | /* | |
| 418 | * Memory Periodic Timer Prescaler | |
| 419 | */ | |
| 420 | ||
| 421 | /* | |
| 422 | * Memory Periodic Timer Prescaler | |
| 423 | * | |
| 424 | * The Divider for PTA (refresh timer) configuration is based on an | |
| 425 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
| 426 | * the number of chip selects (NCS) and the actually needed refresh | |
| 427 | * rate is done by setting MPTPR. | |
| 428 | * | |
| 429 | * PTA is calculated from | |
| 430 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
| 431 | * | |
| 432 | * gclk CPU clock (not bus clock!) | |
| 433 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 434 | * | |
| 435 | * 4096 Rows from SDRAM example configuration | |
| 436 | * 1000 factor s -> ms | |
| 437 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
| 438 | * 4 Number of refresh cycles per period | |
| 439 | * 64 Refresh cycle in ms per number of rows | |
| 440 | * -------------------------------------------- | |
| 441 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
| 442 | * | |
| 443 | * 50 MHz => 50.000.000 / Divider = 98 | |
| 444 | * 66 Mhz => 66.000.000 / Divider = 129 | |
| 445 | * 80 Mhz => 80.000.000 / Divider = 156 | |
| 446 | */ | |
| 447 | ||
| 448 | #if MPC8XX_HZ == 120000000 | |
| 6d0f6bcf | 449 | #define CONFIG_SYS_MAMR_PTA 234 |
| 04a85b3b | 450 | #elif MPC8XX_HZ == 100000000 |
| 6d0f6bcf | 451 | #define CONFIG_SYS_MAMR_PTA 195 |
| 04a85b3b | 452 | #elif MPC8XX_HZ == 80000000 |
| 6d0f6bcf | 453 | #define CONFIG_SYS_MAMR_PTA 156 |
| 04a85b3b | 454 | #elif MPC8XX_HZ == 50000000 |
| 6d0f6bcf | 455 | #define CONFIG_SYS_MAMR_PTA 98 |
| 04a85b3b WD |
456 | #else |
| 457 | #error Unknown frequency | |
| 458 | #endif | |
| 459 | ||
| 460 | ||
| 461 | /* | |
| 462 | * For 16 MBit, refresh rates could be 31.3 us | |
| 463 | * (= 64 ms / 2K = 125 / quad bursts). | |
| 464 | * For a simpler initialization, 15.6 us is used instead. | |
| 465 | * | |
| 6d0f6bcf JCPV |
466 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
| 467 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
| 04a85b3b | 468 | */ |
| 6d0f6bcf JCPV |
469 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
| 470 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
| 04a85b3b WD |
471 | |
| 472 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
| 6d0f6bcf JCPV |
473 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
| 474 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
| 04a85b3b WD |
475 | |
| 476 | /* | |
| 477 | * MAMR settings for SDRAM | |
| 478 | */ | |
| 479 | ||
| 480 | /* 8 column SDRAM */ | |
| 6d0f6bcf | 481 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 04a85b3b WD |
482 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 483 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 484 | ||
| 485 | /* 9 column SDRAM */ | |
| 6d0f6bcf | 486 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
| 04a85b3b WD |
487 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 488 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
| 489 | ||
| 490 | /* | |
| 491 | * Internal Definitions | |
| 492 | * | |
| 493 | * Boot Flags | |
| 494 | */ | |
| 495 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 496 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 497 | ||
| 04a85b3b WD |
498 | #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
| 499 | ||
| 500 | /*********************************************************************************************************** | |
| 501 | ||
| 502 | Pin definitions: | |
| 503 | ||
| 504 | +------+----------------+--------+------------------------------------------------------------ | |
| 505 | | # | Name | Type | Comment | |
| 506 | +------+----------------+--------+------------------------------------------------------------ | |
| 507 | | PA3 | OK_ETH_3V | Input | CISCO Ethernet power OK | |
| 508 | | | | | (NetRoute: FEC1, TA: FEC2) (0=power OK) | |
| 509 | | PA6 | P_VCCD1 | Output | TPS2211A PCMCIA | |
| 510 | | PA7 | DCL1_3V | Periph | IDL1 PCM clock | |
| 511 | | PA8 | DSP_DR1 | Periph | IDL1 PCM Data Rx | |
| 512 | | PA9 | L1TXDA | Periph | IDL1 PCM Data Tx | |
| 513 | | PA10 | P_VCCD0 | Output | TPS2211A PCMCIA | |
| 514 | | PA12 | P_SHDN | Output | TPS2211A PCMCIA | |
| 515 | | PA13 | ETH_LOOP | Output | CISCO Loopback remote power | |
| 516 | | | | | (NetRoute: FEC1, TA: FEC2) (1=NORMAL) | |
| 517 | | PA14 | P_VPPD0 | Output | TPS2211A PCMCIA | |
| 518 | | PA15 | P_VPPD1 | Output | TPS2211A PCMCIA | |
| 519 | | PB14 | SPIEN_FXO | Output | SPI CS for FXO daughter-board | |
| 520 | | PB15 | SPIEN_S1 | Output | SPI CS for S-interface 1 (NetRoute only) | |
| 521 | | PB16 | DREQ1 | Output | D channel request for S-interface chip 1. | |
| 522 | | PB17 | L1ST3 | Periph | IDL1 timeslot enable signal for PPC | |
| 523 | | PB18 | L1ST2 | Periph | IDL1 timeslot enable signal for PPC | |
| 524 | | PB19 | SPIEN_S2 | Output | SPI CS for S-interface 2 (NetRoute only) | |
| 525 | | PB20 | SPIEN_SEEPROM | Output | SPI CS for serial eeprom | |
| 526 | | PB21 | LEDIO | Output | Led mode indication for PHY | |
| 527 | | PB22 | UART_CTS | Input | UART CTS | |
| 528 | | PB23 | UART_RTS | Output | UART RTS | |
| 529 | | PB24 | UART_RX | Periph | UART Data Rx | |
| 530 | | PB25 | UART_TX | Periph | UART Data Tx | |
| 531 | | PB26 | RMII-MDC | Periph | Free for future use (MII mgt clock) | |
| 532 | | PB27 | RMII-MDIO | Periph | Free for future use (MII mgt data) | |
| 533 | | PB28 | SPI_RXD_3V | Input | SPI Data Rx | |
| 534 | | PB29 | SPI_TXD | Output | SPI Data Tx | |
| 535 | | PB30 | SPI_CLK | Output | SPI Clock | |
| 536 | | PB31 | RMII1-REFCLK | Periph | RMII reference clock for FEC1 | |
| 537 | | PC4 | PHY1_LINK | Input | PHY link state FEC1 (interrupt) | |
| 538 | | PC5 | PHY2_LINK | Input | PHY link state FEC2 (interrupt) | |
| 539 | | PC6 | RMII1-MDINT | Input | PHY prog interrupt FEC1 (interrupt) | |
| 540 | | PC7 | RMII2-MDINT | Input | PHY prog interrupt FEC1 (interrupt) | |
| 541 | | PC8 | P_OC | Input | TPS2211A PCMCIA overcurrent (interrupt) (1=OK) | |
| 542 | | PC9 | COM_HOOK1 | Input | Codec interrupt chip #1 (interrupt) | |
| 543 | | PC10 | COM_HOOK2 | Input | Codec interrupt chip #2 (interrupt) | |
| 544 | | PC11 | COM_HOOK4 | Input | Codec interrupt chip #4 (interrupt) | |
| 545 | | PC12 | COM_HOOK3 | Input | Codec interrupt chip #3 (interrupt) | |
| 546 | | PC13 | F_RY_BY | Input | NAND ready signal (interrupt) | |
| 547 | | PC14 | FAN_OK | Input | Fan status signal (interrupt) (1=OK) | |
| 548 | | PC15 | PC15_DIRECT0 | Periph | PCMCIA DMA request. | |
| 549 | | PD3 | F_ALE | Output | NAND | |
| 550 | | PD4 | F_CLE | Output | NAND | |
| 551 | | PD5 | F_CE | Output | NAND | |
| 552 | | PD6 | DSP_INT | Output | DSP debug interrupt | |
| 553 | | PD7 | DSP_RESET | Output | DSP reset | |
| 554 | | PD8 | RMII_MDC | Periph | MII mgt clock | |
| 555 | | PD9 | SPIEN_C1 | Output | SPI CS for codec #1 | |
| 556 | | PD10 | SPIEN_C2 | Output | SPI CS for codec #2 | |
| 557 | | PD11 | SPIEN_C3 | Output | SPI CS for codec #3 | |
| 558 | | PD12 | FSC2 | Periph | IDL2 frame sync | |
| 559 | | PD13 | DGRANT2 | Input | D channel grant from S #2 | |
| 560 | | PD14 | SPIEN_C4 | Output | SPI CS for codec #4 | |
| 561 | | PD15 | TP700 | Output | Testpoint for software debugging | |
| 562 | | PE14 | RMII2-TXD0 | Periph | FEC2 transmit data | |
| 563 | | PE15 | RMII2-TXD1 | Periph | FEC2 transmit data | |
| 564 | | PE16 | RMII2-REFCLK | Periph | TA: RMII ref clock for | |
| 565 | | | DCL2 | Periph | NetRoute: PCM clock #2 | |
| 566 | | PE17 | TP703 | Output | Testpoint for software debugging | |
| 567 | | PE18 | DGRANT1 | Input | D channel grant from S #1 | |
| 568 | | PE19 | RMII2-TXEN | Periph | TA: FEC2 tx enable | |
| 569 | | | PCM2OUT | Periph | NetRoute: Tx data for IDL2 | |
| 570 | | PE20 | FSC1 | Periph | IDL1 frame sync | |
| 571 | | PE21 | RMII2-RXD0 | Periph | FEC2 receive data | |
| 572 | | PE22 | RMII2-RXD1 | Periph | FEC2 receive data | |
| 573 | | PE23 | L1ST1 | Periph | IDL1 timeslot enable signal for PPC | |
| 574 | | PE24 | U-N1 | Output | Select user/network for S #1 (0=user) | |
| 575 | | PE25 | U-N2 | Output | Select user/network for S #2 (0=user) | |
| 576 | | PE26 | RMII2-RXDV | Periph | FEC2 valid | |
| 577 | | PE27 | DREQ2 | Output | D channel request for S #2. | |
| 578 | | PE28 | FPGA_DONE | Input | FPGA done signal | |
| 579 | | PE29 | FPGA_INIT | Output | FPGA init signal | |
| 580 | | PE30 | UDOUT2_3V | Input | IDL2 PCM input | |
| 581 | | PE31 | | | Free | |
| 582 | +------+----------------+--------+--------------------------------------------------- | |
| 583 | ||
| 584 | Chip selects: | |
| 585 | ||
| 586 | +------+----------------+------------------------------------------------------------ | |
| 587 | | # | Name | Comment | |
| 588 | +------+----------------+------------------------------------------------------------ | |
| 589 | | CS0 | CS0 | Boot flash | |
| 590 | | CS1 | CS_FLASH | NAND flash | |
| 591 | | CS2 | CS_DSP | DSP | |
| 592 | | CS3 | DCS_DRAM | DRAM | |
| 593 | | CS4 | CS_ER1 | External output register | |
| 594 | +------+----------------+------------------------------------------------------------ | |
| 595 | ||
| 596 | Interrupts: | |
| 597 | ||
| 598 | +------+----------------+------------------------------------------------------------ | |
| 599 | | # | Name | Comment | |
| 600 | +------+----------------+------------------------------------------------------------ | |
| 601 | | IRQ1 | UINTER_3V | S interupt chips interrupt (common) | |
| 602 | | IRQ3 | IRQ_DSP | DSP interrupt | |
| 603 | | IRQ4 | IRQ_DSP1 | Extra DSP interrupt | |
| 604 | +------+----------------+------------------------------------------------------------ | |
| 605 | ||
| 606 | *************************************************************************************************/ | |
| 607 | ||
| 608 | #define DSP_SIZE 0x00010000 /* 64K */ | |
| 609 | #define NAND_SIZE 0x00010000 /* 64K */ | |
| 610 | #define ER_SIZE 0x00010000 /* 64K */ | |
| 611 | #define DUMMY_SIZE 0x00010000 /* 64K */ | |
| 612 | ||
| 613 | #define DSP_BASE 0xF1000000 | |
| 614 | #define NAND_BASE 0xF1010000 | |
| 615 | #define ER_BASE 0xF1020000 | |
| 616 | #define DUMMY_BASE 0xF1FF0000 | |
| 617 | ||
| 79fa88f3 WD |
618 | /*****************************************************************************/ |
| 619 | ||
| 6d0f6bcf JCPV |
620 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
| 621 | #define CONFIG_SYS_DIRECT_NAND_TFTP | |
| 79fa88f3 | 622 | |
| 04a85b3b WD |
623 | /*****************************************************************************/ |
| 624 | ||
| 625 | #if 1 | |
| 626 | /*----------------------------------------------------------------------- | |
| 627 | * PCMCIA stuff | |
| 628 | *----------------------------------------------------------------------- | |
| 629 | */ | |
| 630 | ||
| 6d0f6bcf JCPV |
631 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 632 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
| 633 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
| 634 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
| 635 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
| 636 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
| 637 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
| 638 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
| 04a85b3b WD |
639 | |
| 640 | /*----------------------------------------------------------------------- | |
| 641 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
| 642 | *----------------------------------------------------------------------- | |
| 643 | */ | |
| 644 | ||
| 645 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ | |
| 646 | ||
| 647 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 648 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
| 649 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
| 650 | ||
| 6d0f6bcf JCPV |
651 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 652 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
| 04a85b3b | 653 | |
| 6d0f6bcf | 654 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
| 04a85b3b | 655 | |
| 6d0f6bcf | 656 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
| 04a85b3b WD |
657 | |
| 658 | /* Offset for data I/O */ | |
| 6d0f6bcf | 659 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| 04a85b3b WD |
660 | |
| 661 | /* Offset for normal register accesses */ | |
| 6d0f6bcf | 662 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
| 04a85b3b WD |
663 | |
| 664 | /* Offset for alternate registers */ | |
| 6d0f6bcf | 665 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
| 04a85b3b WD |
666 | |
| 667 | #define CONFIG_MAC_PARTITION | |
| 668 | #define CONFIG_DOS_PARTITION | |
| 669 | #endif | |
| 670 | ||
| 671 | /*************************************************************************************************/ | |
| 672 | ||
| 673 | #define CONFIG_CDP_DEVICE_ID 20 | |
| 674 | #define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta */ | |
| 675 | #define CONFIG_CDP_PORT_ID "eth%d" | |
| 676 | #define CONFIG_CDP_CAPABILITIES 0x00000010 | |
| 561858ee | 677 | #define CONFIG_CDP_VERSION "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME |
| 04a85b3b WD |
678 | #define CONFIG_CDP_PLATFORM "Intracom NetTA" |
| 679 | #define CONFIG_CDP_TRIGGER 0x20020001 | |
| 680 | #define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */ | |
| 681 | #define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone? */ | |
| 682 | ||
| 683 | /*************************************************************************************************/ | |
| 684 | ||
| 685 | #define CONFIG_AUTO_COMPLETE 1 | |
| 686 | ||
| 687 | /*************************************************************************************************/ | |
| 688 | ||
| c26e454d WD |
689 | #define CONFIG_CRC32_VERIFY 1 |
| 690 | ||
| 691 | /*************************************************************************************************/ | |
| 692 | ||
| 693 | #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 | |
| 694 | ||
| 695 | /*************************************************************************************************/ | |
| 696 | ||
| 04a85b3b | 697 | #endif /* __CONFIG_H */ |